[llvm] [AArch64][NeoverseV1] Load/Store Register Half with scaling (PR #222282)

[Asher Dobrescu via llvm-commits]

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@@ -745,6 +754,13 @@ def : SchedAlias<WriteST, V1Write_1c_1L01_1D>;
 // Store register, immed offset, index
 def : SchedAlias<WriteSTIdx, V1Write_1c_1L01_1D>;
 
+// Store register, register offset, extend, scale by 2
+// Store register, register offset, extend
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Asher8118 wrote:

Should there be a similar entry for `Store register, register offset, scaled by 2` and `Store register, register offset, extend, scale by 1`? I see the SWOG mentions those instructions with latency 2.

https://github.com/llvm/llvm-project/pull/222282