[llvm] [AMDGPU][GISel] Do not scalarize uniform v2f16/v2bf16 operations (PR #222359)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 11 06:28:39 PDT 2026
https://github.com/LU-JOHN updated https://github.com/llvm/llvm-project/pull/222359
>From 38ffca66332ed799164a83b60d631f04b92c0b15 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Wed, 9 Sep 2026 10:10:52 -0500
Subject: [PATCH] Do not scalarize v2f16 operations
Signed-off-by: John Lu <John.Lu at amd.com>
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 25 +++----
llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll | 67 ++++++-------------
llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll | 19 ++----
llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll | 9 +--
llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll | 19 ++----
llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll | 67 ++++++-------------
llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll | 21 ++----
.../AMDGPU/GlobalISel/strict_fma.f16.ll | 55 +++------------
.../test/CodeGen/AMDGPU/llvm.fptrunc.round.ll | 15 ++---
llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll | 19 ++----
llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll | 19 ++----
llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll | 10 +--
12 files changed, 92 insertions(+), 253 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 8aafbbc4dfdf8..20e50deaf10d5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1495,9 +1495,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
.Uni(S64, {{UniInVgprS64}, {Vgpr64, Vgpr64}})
.Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}})
- .Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}}, !hasSALUFloat)
- .Uni(V2S16, {{SgprV2S16}, {SgprV2S16, SgprV2S16}, ScalarizeToS16},
- hasSALUFloat)
+ .Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}})
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
.Any({{UniV2S32}, {{UniInVgprV2S32}, {VgprV2S32, VgprV2S32}}})
.Any({{DivV2S32}, {{VgprV2S32}, {VgprV2S32, VgprV2S32}}})
@@ -1510,7 +1508,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S16, {{Sgpr16}, {Sgpr16, Sgpr16}}, hasSALUFloat)
.Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16}}, !hasSALUFloat)
.Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}}, hasSALUFloat)
- .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}}, !hasSALUFloat);
+ .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}}, !hasSALUFloat)
+ .Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}})
+ .Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}});
addRulesForGOpcs({G_FMAD}, Standard)
.Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16, Vgpr16}})
@@ -1527,22 +1527,18 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Div(S64, {{Vgpr64}, {Vgpr64, Vgpr32}});
addRulesForGOpcs({G_FMA, G_STRICT_FMA}, Standard)
+ .Uni(S16, {{Sgpr16}, {Sgpr16, Sgpr16, Sgpr16}}, hasSALUFloat)
+ .Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16, Vgpr16}}, !hasSALUFloat)
.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16, Vgpr16}})
+ .Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32, Sgpr32}}, hasSALUFloat)
+ .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32, Vgpr32}}, !hasSALUFloat)
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32, Vgpr32}})
.Uni(S64, {{UniInVgprS64}, {Vgpr64, Vgpr64, Vgpr64}})
.Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64, Vgpr64}})
+ .Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16, VgprV2S16}})
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16, VgprV2S16}})
.Any({{UniV2S32}, {{UniInVgprV2S32}, {VgprV2S32, VgprV2S32, VgprV2S32}}})
.Any({{DivV2S32}, {{VgprV2S32}, {VgprV2S32, VgprV2S32, VgprV2S32}}})
- .Uni(S16, {{Sgpr16}, {Sgpr16, Sgpr16, Sgpr16}}, hasSALUFloat)
- .Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16, Vgpr16}}, !hasSALUFloat)
- .Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32, Sgpr32}}, hasSALUFloat)
- .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32, Vgpr32}}, !hasSALUFloat)
- .Uni(V2S16,
- {{SgprV2S16}, {SgprV2S16, SgprV2S16, SgprV2S16}, ScalarizeToS16},
- hasSALUFloat)
- .Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16, VgprV2S16}},
- !hasSALUFloat)
.Any({{UniV2S64}, {{UniInVgprV2S64}, {VgprV2S64, VgprV2S64, VgprV2S64}}})
.Any({{DivV2S64}, {{VgprV2S64}, {VgprV2S64, VgprV2S64, VgprV2S64}}});
@@ -1572,8 +1568,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Div(S32, {{Vgpr32}, {Vgpr32}})
.Uni(S64, {{UniInVgprS64}, {Vgpr64}})
.Div(S64, {{Vgpr64}, {Vgpr64}})
- .Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16}}, !hasSALUFloat)
- .Uni(V2S16, {{SgprV2S16}, {SgprV2S16}, ScalarizeToS16}, hasSALUFloat)
+ .Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16}})
.Div(V2S16, {{VgprV2S16}, {VgprV2S16}})
.Any({{UniV2S32}, {{UniInVgprV2S32}, {VgprV2S32}}})
.Any({{DivV2S32}, {{VgprV2S32}, {VgprV2S32}}});
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
index fb1abd53ae2ef..86c4ee3158e96 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
@@ -170,58 +170,33 @@ define amdgpu_ps void @v_fabs_v2f16(<2 x half> %in, ptr addrspace(1) %out) {
store <2 x half> %fabs, ptr addrspace(1) %out
ret void
}
+
define amdgpu_ps void @s_fabs_v2f16(<2 x half> inreg %in) {
-; GFX11-LABEL: s_fabs_v2f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_and_b32_e64 v0, 0x7fff7fff, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ;;#ASMSTART
-; GFX11-NEXT: ; use s0
-; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: s_endpgm
-;
-; GFX12-LABEL: s_fabs_v2f16:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_lshr_b32 s1, s0, 16
-; GFX12-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX12-NEXT: s_and_b32 s1, s1, 0x7fff
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s1
-; GFX12-NEXT: ;;#ASMSTART
-; GFX12-NEXT: ; use s0
-; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_endpgm
+; GCN-LABEL: s_fabs_v2f16:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_and_b32_e64 v0, 0x7fff7fff, s0
+; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: ;;#ASMSTART
+; GCN-NEXT: ; use s0
+; GCN-NEXT: ;;#ASMEND
+; GCN-NEXT: s_endpgm
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
call void asm sideeffect "; use $0", "s"(<2 x half> %fabs)
ret void
}
define amdgpu_ps void @s_fabs_v2f16_salu_use(<2 x half> inreg %in, i32 inreg %val) {
-; GFX11-LABEL: s_fabs_v2f16_salu_use:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_and_b32_e64 v0, 0x7fff7fff, s0
-; GFX11-NEXT: s_cmp_eq_u32 s1, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: s_cselect_b32 s0, s0, 0
-; GFX11-NEXT: ;;#ASMSTART
-; GFX11-NEXT: ; use s0
-; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: s_endpgm
-;
-; GFX12-LABEL: s_fabs_v2f16_salu_use:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_lshr_b32 s2, s0, 16
-; GFX12-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX12-NEXT: s_and_b32 s2, s2, 0x7fff
-; GFX12-NEXT: s_cmp_eq_u32 s1, 0
-; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_cselect_b32 s0, s0, 0
-; GFX12-NEXT: ;;#ASMSTART
-; GFX12-NEXT: ; use s0
-; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_endpgm
+; GCN-LABEL: s_fabs_v2f16_salu_use:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_and_b32_e64 v0, 0x7fff7fff, s0
+; GCN-NEXT: s_cmp_eq_u32 s1, 0
+; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: s_cselect_b32 s0, s0, 0
+; GCN-NEXT: ;;#ASMSTART
+; GCN-NEXT: ; use s0
+; GCN-NEXT: ;;#ASMEND
+; GCN-NEXT: s_endpgm
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
%cond = icmp eq i32 %val, 0
%sel = select i1 %cond, <2 x half> %fabs, <2 x half> <half 0.0, half 0.0>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
index 808bb42378841..bdeacefca362f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
@@ -109,21 +109,10 @@ define amdgpu_ps void @fadd_s64_div(double %a, double %b, ptr addrspace(1) %ptr)
}
define amdgpu_ps <2 x half> @fadd_v2s16_uniform(<2 x half> inreg %a, <2 x half> inreg %b) {
-; GFX11-LABEL: fadd_v2s16_uniform:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_pk_add_f16 v0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
-;
-; GFX12-LABEL: fadd_v2s16_uniform:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_lshr_b32 s2, s0, 16
-; GFX12-NEXT: s_lshr_b32 s3, s1, 16
-; GFX12-NEXT: s_add_f16 s0, s0, s1
-; GFX12-NEXT: s_add_f16 s1, s2, s3
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s1
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-NEXT: ; return to shader part epilog
+; GCN-LABEL: fadd_v2s16_uniform:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_pk_add_f16 v0, s0, s1
+; GCN-NEXT: ; return to shader part epilog
%fadd = fadd <2 x half> %a, %b
ret <2 x half> %fadd
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
index 7505234fae8d2..639469de762b4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
@@ -1736,13 +1736,8 @@ define amdgpu_ps <2 x half> @fma_v2s16_uniform(<2 x half> inreg %a, <2 x half> i
;
; GFX12-LABEL: fma_v2s16_uniform:
; GFX12: ; %bb.0:
-; GFX12-NEXT: s_lshr_b32 s3, s0, 16
-; GFX12-NEXT: s_lshr_b32 s4, s1, 16
-; GFX12-NEXT: s_lshr_b32 s5, s2, 16
-; GFX12-NEXT: s_fmac_f16 s2, s0, s1
-; GFX12-NEXT: s_fmac_f16 s5, s3, s4
-; GFX12-NEXT: s_pack_ll_b32_b16 s0, s2, s5
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-NEXT: v_pk_fma_f16 v0, s0, s1, v0
; GFX12-NEXT: ; return to shader part epilog
%fma = call <2 x half> @llvm.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)
ret <2 x half> %fma
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
index a470767e80a39..f4fb2d4595236 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
@@ -109,21 +109,10 @@ define amdgpu_ps void @fmul_s64_div(double %a, double %b, ptr addrspace(1) %ptr)
}
define amdgpu_ps <2 x half> @fmul_v2s16_uniform(<2 x half> inreg %a, <2 x half> inreg %b) {
-; GFX11-LABEL: fmul_v2s16_uniform:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_pk_mul_f16 v0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
-;
-; GFX12-LABEL: fmul_v2s16_uniform:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_lshr_b32 s2, s0, 16
-; GFX12-NEXT: s_lshr_b32 s3, s1, 16
-; GFX12-NEXT: s_mul_f16 s0, s0, s1
-; GFX12-NEXT: s_mul_f16 s1, s2, s3
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s1
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-NEXT: ; return to shader part epilog
+; GCN-LABEL: fmul_v2s16_uniform:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_pk_mul_f16 v0, s0, s1
+; GCN-NEXT: ; return to shader part epilog
%result = fmul <2 x half> %a, %b
ret <2 x half> %result
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
index 571eb2e19c0d2..4f646ba290ffb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
@@ -170,58 +170,33 @@ define amdgpu_ps void @v_fneg_v2f16(<2 x half> %in, ptr addrspace(1) %out) {
store <2 x half> %fneg, ptr addrspace(1) %out
ret void
}
+
define amdgpu_ps void @s_fneg_v2f16(<2 x half> inreg %in) {
-; GFX11-LABEL: s_fneg_v2f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_xor_b32_e64 v0, 0x80008000, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ;;#ASMSTART
-; GFX11-NEXT: ; use s0
-; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: s_endpgm
-;
-; GFX12-LABEL: s_fneg_v2f16:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_lshr_b32 s1, s0, 16
-; GFX12-NEXT: s_xor_b32 s0, s0, 0x8000
-; GFX12-NEXT: s_xor_b32 s1, s1, 0x8000
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s1
-; GFX12-NEXT: ;;#ASMSTART
-; GFX12-NEXT: ; use s0
-; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_endpgm
+; GCN-LABEL: s_fneg_v2f16:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_xor_b32_e64 v0, 0x80008000, s0
+; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: ;;#ASMSTART
+; GCN-NEXT: ; use s0
+; GCN-NEXT: ;;#ASMEND
+; GCN-NEXT: s_endpgm
%fneg = fneg <2 x half> %in
call void asm sideeffect "; use $0", "s"(<2 x half> %fneg)
ret void
}
define amdgpu_ps void @s_fneg_v2f16_salu_use(<2 x half> inreg %in, i32 inreg %val) {
-; GFX11-LABEL: s_fneg_v2f16_salu_use:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_xor_b32_e64 v0, 0x80008000, s0
-; GFX11-NEXT: s_cmp_eq_u32 s1, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: s_cselect_b32 s0, s0, 0
-; GFX11-NEXT: ;;#ASMSTART
-; GFX11-NEXT: ; use s0
-; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: s_endpgm
-;
-; GFX12-LABEL: s_fneg_v2f16_salu_use:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_lshr_b32 s2, s0, 16
-; GFX12-NEXT: s_xor_b32 s0, s0, 0x8000
-; GFX12-NEXT: s_xor_b32 s2, s2, 0x8000
-; GFX12-NEXT: s_cmp_eq_u32 s1, 0
-; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_cselect_b32 s0, s0, 0
-; GFX12-NEXT: ;;#ASMSTART
-; GFX12-NEXT: ; use s0
-; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_endpgm
+; GCN-LABEL: s_fneg_v2f16_salu_use:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_xor_b32_e64 v0, 0x80008000, s0
+; GCN-NEXT: s_cmp_eq_u32 s1, 0
+; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: s_cselect_b32 s0, s0, 0
+; GCN-NEXT: ;;#ASMSTART
+; GCN-NEXT: ; use s0
+; GCN-NEXT: ;;#ASMEND
+; GCN-NEXT: s_endpgm
%fneg = fneg <2 x half> %in
%cond = icmp eq i32 %val, 0
%sel = select i1 %cond, <2 x half> %fneg, <2 x half> <half 0.0, half 0.0>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
index c26b2de6938fa..b5ac435b16940 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
@@ -109,23 +109,10 @@ define amdgpu_ps void @fsub_s64_div(double %a, double %b, ptr addrspace(1) %ptr)
}
define amdgpu_ps <2 x half> @fsub_v2s16_uniform(<2 x half> inreg %a, <2 x half> inreg %b) {
-; GFX11-LABEL: fsub_v2s16_uniform:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_pk_add_f16 v0, s0, s1 neg_lo:[0,1] neg_hi:[0,1]
-; GFX11-NEXT: ; return to shader part epilog
-;
-; GFX12-LABEL: fsub_v2s16_uniform:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_lshr_b32 s2, s1, 16
-; GFX12-NEXT: s_xor_b32 s1, s1, 0x8000
-; GFX12-NEXT: s_xor_b32 s2, s2, 0x8000
-; GFX12-NEXT: s_lshr_b32 s3, s0, 16
-; GFX12-NEXT: s_add_f16 s0, s0, s1
-; GFX12-NEXT: s_add_f16 s1, s3, s2
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s1
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-NEXT: ; return to shader part epilog
+; GCN-LABEL: fsub_v2s16_uniform:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_pk_add_f16 v0, s0, s1 neg_lo:[0,1] neg_hi:[0,1]
+; GCN-NEXT: ; return to shader part epilog
%fsub = fsub <2 x half> %a, %b
ret <2 x half> %fsub
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
index b833480c267f0..a94fb3a925c41 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
@@ -172,17 +172,9 @@ define void @v_constained_fma_v2f16_fpexcept_strict_uni(<2 x half> inreg %x, <2
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_lshr_b32 s3, s0, 16
-; GFX12-NEXT: s_lshr_b32 s4, s1, 16
-; GFX12-NEXT: s_lshr_b32 s5, s2, 16
-; GFX12-NEXT: s_fmac_f16 s2, s0, s1
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_fmac_f16 s5, s3, s4
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX12-NEXT: s_pack_ll_b32_b16 s0, s2, s5
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-NEXT: v_mov_b32_e32 v2, s2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_fma_f16 v2, s0, s1, v2
; GFX12-NEXT: global_store_b32 v[0:1], v2, off
; GFX12-NEXT: s_setpc_b64 s[30:31]
%val = call <2 x half> @llvm.experimental.constrained.fma.v2f16(<2 x half> %x, <2 x half> %y, <2 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
@@ -396,24 +388,10 @@ define void @v_constained_fma_v4f16_fpexcept_strict_uni(<4 x half> inreg %x, <4
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_lshr_b32 s4, s0, 16
-; GFX12-NEXT: s_lshr_b32 s5, s2, 16
-; GFX12-NEXT: s_lshr_b32 s6, s16, 16
-; GFX12-NEXT: s_fmac_f16 s16, s0, s2
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_fmac_f16 s6, s4, s5
-; GFX12-NEXT: s_lshr_b32 s0, s1, 16
-; GFX12-NEXT: s_lshr_b32 s2, s3, 16
-; GFX12-NEXT: s_lshr_b32 s4, s17, 16
-; GFX12-NEXT: s_fmac_f16 s17, s1, s3
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_fmac_f16 s4, s0, s2
-; GFX12-NEXT: s_pack_ll_b32_b16 s0, s16, s6
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_pack_ll_b32_b16 s1, s17, s4
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX12-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_pk_fma_f16 v2, s0, s2, v2
+; GFX12-NEXT: v_pk_fma_f16 v3, s1, s3, v3
; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX12-NEXT: s_setpc_b64 s[30:31]
%val = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %x, <4 x half> %y, <4 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
@@ -882,22 +860,9 @@ define void @v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_uni(<2 x half> inr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_lshr_b32 s3, s0, 16
-; GFX12-NEXT: s_lshr_b32 s4, s1, 16
-; GFX12-NEXT: s_xor_b32 s0, s0, 0x8000
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_xor_b32 s3, s3, 0x8000
-; GFX12-NEXT: s_xor_b32 s1, s1, 0x8000
-; GFX12-NEXT: s_xor_b32 s4, s4, 0x8000
-; GFX12-NEXT: s_lshr_b32 s5, s2, 16
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_fmac_f16 s2, s0, s1
-; GFX12-NEXT: s_fmac_f16 s5, s3, s4
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX12-NEXT: s_pack_ll_b32_b16 s0, s2, s5
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-NEXT: v_mov_b32_e32 v2, s1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_fma_f16 v2, s0, v2, s2 neg_lo:[1,1,0] neg_hi:[1,1,0]
; GFX12-NEXT: global_store_b32 v[0:1], v2, off
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.x = fneg <2 x half> %x
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
index 2ab76c99095f8..47e7cb77a84dd 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
@@ -1265,15 +1265,14 @@ define amdgpu_gs void @s_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls(<2 x
; GFX12-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 2
; GFX12-GISEL-NEXT: s_cvt_f16_f32 s2, s2
; GFX12-GISEL-NEXT: s_cvt_f16_f32 s3, s3
-; GFX12-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 3, 1), 0
-; GFX12-GISEL-NEXT: s_add_f16 s0, s0, s4
-; GFX12-GISEL-NEXT: s_add_f16 s1, s1, s5
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(SALU_CYCLE_2)
-; GFX12-GISEL-NEXT: s_add_f16 s0, s2, s0
-; GFX12-GISEL-NEXT: s_add_f16 s1, s3, s1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s1
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-GISEL-NEXT: s_pack_ll_b32_b16 s1, s4, s5
+; GFX12-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 3, 1), 0
+; GFX12-GISEL-NEXT: v_pk_add_f16 v2, s0, s1
+; GFX12-GISEL-NEXT: s_pack_ll_b32_b16 s0, s2, s3
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_pk_add_f16 v2, s0, v2
; GFX12-GISEL-NEXT: global_store_b32 v[0:1], v2, off
; GFX12-GISEL-NEXT: s_endpgm
%res1 = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %a, metadata !"round.upward")
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
index e0ebb7ff1927d..ba0a39244b326 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
@@ -585,21 +585,10 @@ define amdgpu_ps <2 x half> @s_constained_fadd_v2f16_fpexcept_strict(<2 x half>
; GFX11-NEXT: v_pk_add_f16 v0, s2, s3
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-SDAG-LABEL: s_constained_fadd_v2f16_fpexcept_strict:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: v_pk_add_f16 v0, s2, s3
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: s_constained_fadd_v2f16_fpexcept_strict:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_lshr_b32 s0, s2, 16
-; GFX12-GISEL-NEXT: s_lshr_b32 s1, s3, 16
-; GFX12-GISEL-NEXT: s_add_f16 s2, s2, s3
-; GFX12-GISEL-NEXT: s_add_f16 s0, s0, s1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: s_pack_ll_b32_b16 s0, s2, s0
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12-LABEL: s_constained_fadd_v2f16_fpexcept_strict:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_pk_add_f16 v0, s2, s3
+; GFX12-NEXT: ; return to shader part epilog
%val = call <2 x half> @llvm.experimental.constrained.fadd.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret <2 x half> %val
}
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
index d8925bf2c9a5f..204f635bfedad 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
@@ -660,21 +660,10 @@ define amdgpu_ps <2 x half> @s_constained_fmul_v2f16_fpexcept_strict(<2 x half>
; GFX10PLUS-NEXT: v_pk_mul_f16 v0, s2, s3
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-SDAG-LABEL: s_constained_fmul_v2f16_fpexcept_strict:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: v_pk_mul_f16 v0, s2, s3
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: s_constained_fmul_v2f16_fpexcept_strict:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_lshr_b32 s0, s2, 16
-; GFX12-GISEL-NEXT: s_lshr_b32 s1, s3, 16
-; GFX12-GISEL-NEXT: s_mul_f16 s2, s2, s3
-; GFX12-GISEL-NEXT: s_mul_f16 s0, s0, s1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: s_pack_ll_b32_b16 s0, s2, s0
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12-LABEL: s_constained_fmul_v2f16_fpexcept_strict:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_pk_mul_f16 v0, s2, s3
+; GFX12-NEXT: ; return to shader part epilog
%val = call <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret <2 x half> %val
}
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
index 3fa3a3c5a98e0..109d09e226768 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
@@ -873,15 +873,7 @@ define amdgpu_ps <2 x half> @s_constained_fsub_v2f16_fpexcept_strict(<2 x half>
;
; GFX12-GISEL-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_lshr_b32 s0, s3, 16
-; GFX12-GISEL-NEXT: s_xor_b32 s1, s3, 0x8000
-; GFX12-GISEL-NEXT: s_xor_b32 s0, s0, 0x8000
-; GFX12-GISEL-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-GISEL-NEXT: s_add_f16 s1, s2, s1
-; GFX12-GISEL-NEXT: s_add_f16 s0, s3, s0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: s_pack_ll_b32_b16 s0, s1, s0
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-GISEL-NEXT: v_pk_add_f16 v0, s2, s3 neg_lo:[0,1] neg_hi:[0,1]
; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret <2 x half> %val
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