[llvm] e0d944d - [AMDGPU] Adjust amdgpu fmax/fmin legalization for DAG (#203150)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 11 05:49:06 PDT 2026
Author: Shoreshen
Date: 2026-09-11T14:49:00+02:00
New Revision: e0d944d2dda0df304505947278304a628ff824fb
URL: https://github.com/llvm/llvm-project/commit/e0d944d2dda0df304505947278304a628ff824fb
DIFF: https://github.com/llvm/llvm-project/commit/e0d944d2dda0df304505947278304a628ff824fb.diff
LOG: [AMDGPU] Adjust amdgpu fmax/fmin legalization for DAG (#203150)
Implied by
https://github.com/llvm/llvm-project/pull/202917#discussion_r3388089034
This PR apply legalization change for DAG. Case changes can be explained
in https://github.com/llvm/llvm-project/pull/202917
---------
Co-authored-by: shore <shorshen at amd.com>
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
llvm/test/CodeGen/AMDGPU/clamp.ll
llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
llvm/test/CodeGen/AMDGPU/fmaxnum.ll
llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
llvm/test/CodeGen/AMDGPU/fmin3.ll
llvm/test/CodeGen/AMDGPU/fminnum.ll
llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
llvm/test/CodeGen/AMDGPU/maximumnum.ll
llvm/test/CodeGen/AMDGPU/minimumnum.ll
llvm/test/CodeGen/AMDGPU/minmax.ll
llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index db300b633958b..a0c968d5daea4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -196,8 +196,9 @@ defm FmaLegacy32Insts : AMDGPUSubtargetFeature<"fma-legacy32-insts",
>;
defm IEEEMinimumMaximumInsts : AMDGPUSubtargetFeature<"ieee-minimum-maximum-insts",
- "Has v_minimum/maximum_f16/f32/f64, v_minimummaximum/maximumminimum_f16/f32 and"
- "v_pk_minimum/maximum_f16 instructions"
+ "Has v_minimum/maximum_f16/f32/f64, v_minimummaximum/maximumminimum_f16/f32,"
+ "v_pk_minmax/maxmin_num_f16, v_min/max_num_f16/f32/f64 and"
+ "v_pk_min/max_num_f16 instructions"
>;
defm SALUMinimumMaximumInsts : AMDGPUSubtargetFeature<"salu-minimum-maximum-insts",
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 28193a52f71d2..434ad35f73499 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -261,6 +261,8 @@ def umin_oneuse : HasOneUseBinOp<umin>;
def fminnum_oneuse : HasOneUseBinOp<fminnum>;
def fmaxnum_oneuse : HasOneUseBinOp<fmaxnum>;
+def fminimumnum_oneuse : HasOneUseBinOp<fminimumnum>;
+def fmaximumnum_oneuse : HasOneUseBinOp<fmaximumnum>;
def fminimum_oneuse : HasOneUseBinOp<fminimum>;
def fmaximum_oneuse : HasOneUseBinOp<fmaximum>;
@@ -859,13 +861,15 @@ class RcpPat<Instruction RcpInst, ValueType vt> : AMDGPUPat <
// Instructions which select to the same v_min_f*
def fminnum_like : PatFrags<(ops node:$src0, node:$src1),
[(fminnum_ieee node:$src0, node:$src1),
- (fminnum node:$src0, node:$src1)]
+ (fminnum node:$src0, node:$src1),
+ (fminimumnum node:$src0, node:$src1)]
>;
// Instructions which select to the same v_max_f*
def fmaxnum_like : PatFrags<(ops node:$src0, node:$src1),
[(fmaxnum_ieee node:$src0, node:$src1),
- (fmaxnum node:$src0, node:$src1)]
+ (fmaxnum node:$src0, node:$src1),
+ (fmaximumnum node:$src0, node:$src1)]
>;
class NeverNaNPats<dag ops, list<dag> frags> : PatFrags<ops, frags> {
@@ -879,22 +883,26 @@ class NeverNaNPats<dag ops, list<dag> frags> : PatFrags<ops, frags> {
def fminnum_like_nnan : NeverNaNPats<(ops node:$src0, node:$src1),
[(fminnum_ieee node:$src0, node:$src1),
- (fminnum node:$src0, node:$src1)]
+ (fminnum node:$src0, node:$src1),
+ (fminimumnum node:$src0, node:$src1)]
>;
def fmaxnum_like_nnan : NeverNaNPats<(ops node:$src0, node:$src1),
[(fmaxnum_ieee node:$src0, node:$src1),
- (fmaxnum node:$src0, node:$src1)]
+ (fmaxnum node:$src0, node:$src1),
+ (fmaximumnum node:$src0, node:$src1)]
>;
def fminnum_like_oneuse : PatFrags<(ops node:$src0, node:$src1),
[(fminnum_ieee_oneuse node:$src0, node:$src1),
- (fminnum_oneuse node:$src0, node:$src1)]
+ (fminnum_oneuse node:$src0, node:$src1),
+ (fminimumnum_oneuse node:$src0, node:$src1)]
>;
def fmaxnum_like_oneuse : PatFrags<(ops node:$src0, node:$src1),
[(fmaxnum_ieee_oneuse node:$src0, node:$src1),
- (fmaxnum_oneuse node:$src0, node:$src1)]
+ (fmaxnum_oneuse node:$src0, node:$src1),
+ (fmaximumnum_oneuse node:$src0, node:$src1)]
>;
def any_fmad : PatFrags<(ops node:$src0, node:$src1, node:$src2),
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index a55208053099c..5a26953096c4b 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -561,15 +561,22 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, {MVT::i16, MVT::i32},
Legal);
- setOperationAction(
- {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
- {MVT::f32, MVT::f64}, Custom);
-
- // These are really only legal for ieee_mode functions. We should be avoiding
- // them for functions that don't have ieee_mode enabled, so just say they are
- // legal.
- setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE},
- {MVT::f32, MVT::f64}, Legal);
+ // Do not have s_{min|max}_*f64 instruction f64 will only be lowered to
+ // v_{min|max}_*f64
+ if (Subtarget->hasIEEEMinimumMaximumInsts()) {
+ setOperationAction(
+ {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ {MVT::f64, MVT::f32}, Legal);
+ } else {
+ setOperationAction(
+ {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ {MVT::f64, MVT::f32}, Custom);
+ // These are really only legal for ieee_mode functions. We should be
+ // avoiding them for functions that don't have ieee_mode enabled, so just
+ // say they are legal.
+ setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE},
+ {MVT::f64, MVT::f32}, Legal);
+ }
if (Subtarget->haveRoundOpsF64())
setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FROUNDEVEN}, MVT::f64,
@@ -840,20 +847,31 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
MVT::v8f16, MVT::v8bf16, MVT::v16f16, MVT::v16bf16,
MVT::v32f16, MVT::v32bf16},
Custom);
+ if (Subtarget->hasIEEEMinimumMaximumInsts()) {
+ setOperationAction(
+ {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ MVT::f16, Legal);
- setOperationAction(
- {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
- MVT::f16, Custom);
- setOperationAction({ISD::FMAXNUM_IEEE, ISD::FMINNUM_IEEE}, MVT::f16, Legal);
+ setOperationAction(
+ {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16}, Custom);
+ } else {
+ setOperationAction(
+ {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ MVT::f16, Custom);
- setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE, ISD::FMINIMUMNUM,
- ISD::FMAXIMUMNUM},
- {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16},
- Custom);
+ setOperationAction({ISD::FMAXNUM_IEEE, ISD::FMINNUM_IEEE}, MVT::f16,
+ Legal);
- setOperationAction({ISD::FMINNUM, ISD::FMAXNUM},
- {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16},
- Expand);
+ setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
+ ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16},
+ Custom);
+
+ setOperationAction({ISD::FMINNUM, ISD::FMAXNUM},
+ {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16},
+ Expand);
+ }
for (MVT Vec16 :
{MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, MVT::v16f16,
@@ -872,7 +890,6 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
MVT::v2i16, Legal);
setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG, ISD::FABS,
- ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
ISD::FCANONICALIZE},
MVT::v2f16, Legal);
@@ -899,23 +916,33 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
ISD::FCANONICALIZE},
VT, Custom);
- setOperationAction(
- {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
- {MVT::v2f16, MVT::v4f16}, Custom);
+ if (Subtarget->hasIEEEMinimumMaximumInsts()) {
+ setOperationAction(
+ {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ MVT::v2f16, Legal);
+ } else {
+ setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE}, MVT::v2f16,
+ Legal);
+ setOperationAction(
+ {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ {MVT::v2f16, MVT::v4f16}, Custom);
+ }
setOperationAction(ISD::FEXP, MVT::v2f16, Custom);
setOperationAction(ISD::SELECT, {MVT::v4i16, MVT::v4f16, MVT::v4bf16},
Custom);
if (Subtarget->hasBF16PackedInsts()) {
setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMAXNUM, ISD::FMINNUM,
- ISD::FMA, ISD::FNEG, ISD::FABS, ISD::FCANONICALIZE},
+ ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM, ISD::FMA,
+ ISD::FNEG, ISD::FABS, ISD::FCANONICALIZE},
MVT::v2bf16, Legal);
for (MVT VT : {MVT::v4bf16, MVT::v8bf16, MVT::v16bf16, MVT::v32bf16})
// Split vector operations.
setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FCANONICALIZE,
- ISD::FNEG, ISD::FABS},
+ ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM,
+ ISD::FMAXIMUMNUM, ISD::FNEG, ISD::FABS},
VT, Custom);
}
@@ -928,17 +955,31 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
}
if (Subtarget->hasAnyPackedFP64Ops()) {
setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG,
- ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
ISD::FCANONICALIZE, ISD::BUILD_VECTOR},
MVT::v2f64, Legal);
setOperationAction(
- {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
- MVT::v2f64, Custom);
- setOperationAction(
- {ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG, ISD::FMINNUM_IEEE,
- ISD::FMAXNUM_IEEE, ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM,
- ISD::FMAXIMUMNUM, ISD::FCANONICALIZE},
+ {ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG, ISD::FCANONICALIZE},
{MVT::v4f64, MVT::v8f64, MVT::v16f64, MVT::v32f64}, Custom);
+
+ if (Subtarget->hasIEEEMinimumMaximumInsts()) {
+ setOperationAction(
+ {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ MVT::v2f64, Legal);
+
+ setOperationAction(
+ {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ {MVT::v4f64, MVT::v8f64, MVT::v16f64, MVT::v32f64}, Custom);
+ } else {
+ setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE}, MVT::v2f64,
+ Legal);
+ setOperationAction(
+ {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ MVT::v2f64, Custom);
+ setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE, ISD::FMINNUM,
+ ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ {MVT::v4f64, MVT::v8f64, MVT::v16f64, MVT::v32f64},
+ Custom);
+ }
}
if (Subtarget->hasAnyPackedU64Ops()) {
@@ -8841,11 +8882,13 @@ SDValue SITargetLowering::lowerFMINNUM_FMAXNUM(SDValue Op,
// ieee_mode. Currently a combine can produce the ieee version for non-ieee
// mode functions, but this happens to be OK since it's only done in cases
// where there is known no sNaN.
- if (IsIEEEMode)
+ if (IsIEEEMode && !Subtarget->hasIEEEMinimumMaximumInsts())
return expandFMINNUM_FMAXNUM(Op.getNode(), DAG);
if (VT == MVT::v4f16 || VT == MVT::v8f16 || VT == MVT::v16f16 ||
- VT == MVT::v16bf16)
+ VT == MVT::v32f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16 ||
+ VT == MVT::v16bf16 || VT == MVT::v32bf16 || VT == MVT::v4f64 ||
+ VT == MVT::v8f64 || VT == MVT::v16f64 || VT == MVT::v32f64)
return splitBinaryVectorOp(Op, DAG);
return Op;
}
@@ -8858,11 +8901,13 @@ SITargetLowering::lowerFMINIMUMNUM_FMAXIMUMNUM(SDValue Op,
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
bool IsIEEEMode = Info->getMode().IEEE;
- if (IsIEEEMode)
+ if (IsIEEEMode && !Subtarget->hasIEEEMinimumMaximumInsts())
return expandFMINIMUMNUM_FMAXIMUMNUM(Op.getNode(), DAG);
if (VT == MVT::v4f16 || VT == MVT::v8f16 || VT == MVT::v16f16 ||
- VT == MVT::v32f16)
+ VT == MVT::v32f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16 ||
+ VT == MVT::v16bf16 || VT == MVT::v32bf16 || VT == MVT::v4f64 ||
+ VT == MVT::v8f64 || VT == MVT::v16f64 || VT == MVT::v32f64)
return splitBinaryVectorOp(Op, DAG);
return Op;
}
diff --git a/llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll b/llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
index 437cb100b26c1..6eff3ab333bab 100644
--- a/llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
@@ -849,42 +849,36 @@ define double @flat_system_atomic_fmin_f64(ptr %ptr, double %val) {
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
-; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
-; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1250-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v4
+; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX1250-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB38_3
-; GFX1250-NEXT: ; %bb.1: ; %Flow
-; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB38_4
-; GFX1250-NEXT: .LBB38_2: ; %atomicrmw.phi
-; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-; GFX1250-NEXT: .LBB38_3: ; %atomicrmw.global
-; GFX1250-NEXT: flat_atomic_min_num_f64 v[0:1], v[4:5], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX1250-NEXT: s_cbranch_execz .LBB38_2
+; GFX1250-NEXT: ; %bb.1: ; %atomicrmw.global
+; GFX1250-NEXT: flat_atomic_min_num_f64 v[4:5], v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1250-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX1250-NEXT: .LBB38_2: ; %Flow
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execz .LBB38_2
-; GFX1250-NEXT: .LBB38_4: ; %atomicrmw.private
-; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX1250-NEXT: s_cbranch_execz .LBB38_4
+; GFX1250-NEXT: ; %bb.3: ; %atomicrmw.private
+; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_subrev_nc_u32_e32 v0, src_flat_scratch_base_lo, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_dual_max_num_f64 v[2:3], v[2:3], v[2:3] :: v_dual_cndmask_b32 v6, -1, v0, vcc_lo
-; GFX1250-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX1250-NEXT: v_subrev_nc_u32_e32 v4, src_flat_scratch_base_lo, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
+; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX1250-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[2:3]
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
+; GFX1250-NEXT: .LBB38_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%result = atomicrmw fmin ptr %ptr, double %val monotonic
ret double %result
@@ -895,42 +889,36 @@ define double @flat_one_as_atomic_fmin_f64(ptr %ptr, double %val) {
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
-; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
-; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1250-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v4
+; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX1250-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB39_3
-; GFX1250-NEXT: ; %bb.1: ; %Flow
-; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB39_4
-; GFX1250-NEXT: .LBB39_2: ; %atomicrmw.phi
-; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-; GFX1250-NEXT: .LBB39_3: ; %atomicrmw.global
-; GFX1250-NEXT: flat_atomic_min_num_f64 v[0:1], v[4:5], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX1250-NEXT: s_cbranch_execz .LBB39_2
+; GFX1250-NEXT: ; %bb.1: ; %atomicrmw.global
+; GFX1250-NEXT: flat_atomic_min_num_f64 v[4:5], v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1250-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX1250-NEXT: .LBB39_2: ; %Flow
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execz .LBB39_2
-; GFX1250-NEXT: .LBB39_4: ; %atomicrmw.private
-; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX1250-NEXT: s_cbranch_execz .LBB39_4
+; GFX1250-NEXT: ; %bb.3: ; %atomicrmw.private
+; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_subrev_nc_u32_e32 v0, src_flat_scratch_base_lo, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_dual_max_num_f64 v[2:3], v[2:3], v[2:3] :: v_dual_cndmask_b32 v6, -1, v0, vcc_lo
-; GFX1250-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX1250-NEXT: v_subrev_nc_u32_e32 v4, src_flat_scratch_base_lo, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
+; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX1250-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[2:3]
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
+; GFX1250-NEXT: .LBB39_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%result = atomicrmw fmin ptr %ptr, double %val syncscope("one-as") monotonic
ret double %result
@@ -965,42 +953,36 @@ define double @flat_system_atomic_fmax_f64(ptr %ptr, double %val) {
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
-; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
-; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1250-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v4
+; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX1250-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB42_3
-; GFX1250-NEXT: ; %bb.1: ; %Flow
-; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB42_4
-; GFX1250-NEXT: .LBB42_2: ; %atomicrmw.phi
-; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-; GFX1250-NEXT: .LBB42_3: ; %atomicrmw.global
-; GFX1250-NEXT: flat_atomic_max_num_f64 v[0:1], v[4:5], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX1250-NEXT: s_cbranch_execz .LBB42_2
+; GFX1250-NEXT: ; %bb.1: ; %atomicrmw.global
+; GFX1250-NEXT: flat_atomic_max_num_f64 v[4:5], v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1250-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX1250-NEXT: .LBB42_2: ; %Flow
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execz .LBB42_2
-; GFX1250-NEXT: .LBB42_4: ; %atomicrmw.private
-; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX1250-NEXT: s_cbranch_execz .LBB42_4
+; GFX1250-NEXT: ; %bb.3: ; %atomicrmw.private
+; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_subrev_nc_u32_e32 v0, src_flat_scratch_base_lo, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_dual_max_num_f64 v[2:3], v[2:3], v[2:3] :: v_dual_cndmask_b32 v6, -1, v0, vcc_lo
-; GFX1250-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX1250-NEXT: v_subrev_nc_u32_e32 v4, src_flat_scratch_base_lo, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
+; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[2:3]
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
+; GFX1250-NEXT: .LBB42_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%result = atomicrmw fmax ptr %ptr, double %val monotonic
ret double %result
@@ -1011,42 +993,36 @@ define double @flat_one_as_atomic_fmax_f64(ptr %ptr, double %val) {
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
-; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
-; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1250-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v4
+; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX1250-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB43_3
-; GFX1250-NEXT: ; %bb.1: ; %Flow
-; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB43_4
-; GFX1250-NEXT: .LBB43_2: ; %atomicrmw.phi
-; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-; GFX1250-NEXT: .LBB43_3: ; %atomicrmw.global
-; GFX1250-NEXT: flat_atomic_max_num_f64 v[0:1], v[4:5], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX1250-NEXT: s_cbranch_execz .LBB43_2
+; GFX1250-NEXT: ; %bb.1: ; %atomicrmw.global
+; GFX1250-NEXT: flat_atomic_max_num_f64 v[4:5], v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1250-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX1250-NEXT: .LBB43_2: ; %Flow
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execz .LBB43_2
-; GFX1250-NEXT: .LBB43_4: ; %atomicrmw.private
-; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX1250-NEXT: s_cbranch_execz .LBB43_4
+; GFX1250-NEXT: ; %bb.3: ; %atomicrmw.private
+; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_subrev_nc_u32_e32 v0, src_flat_scratch_base_lo, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_dual_max_num_f64 v[2:3], v[2:3], v[2:3] :: v_dual_cndmask_b32 v6, -1, v0, vcc_lo
-; GFX1250-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX1250-NEXT: v_subrev_nc_u32_e32 v4, src_flat_scratch_base_lo, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
+; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[2:3]
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
+; GFX1250-NEXT: .LBB43_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%result = atomicrmw fmax ptr %ptr, double %val syncscope("one-as") monotonic
ret double %result
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
index fbfbf7249f2fd..0023d85264888 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
@@ -1172,26 +1172,24 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
+; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[8:9], v0, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB5_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[8:9], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
-; GFX12-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -1355,24 +1353,22 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
; GFX12-NEXT: v_mov_b32_e32 v6, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[2:3], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB6_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[0:1]
+; GFX12-NEXT: v_dual_mov_b32 v10, v5 :: v_dual_mov_b32 v9, v4
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v10, v3 :: v_dual_mov_b32 v9, v2
-; GFX12-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v7, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[7:10], v6, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v4, v7 :: v_dual_mov_b32 v5, v8
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -1555,20 +1551,18 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: s_cbranch_execnz .LBB7_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_mov_b32 exec_lo, s4
-; GFX12-NEXT: v_max_num_f64_e32 v[5:6], v[5:6], v[5:6]
; GFX12-NEXT: s_mov_b32 s4, 0
; GFX12-NEXT: .LBB7_3: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Loop Header: Depth=1
; GFX12-NEXT: ; Child Loop BB7_4 Depth 2
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[13:14], v[13:14]
+; GFX12-NEXT: v_max_num_f64_e32 v[11:12], v[13:14], v[5:6]
+; GFX12-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
; GFX12-NEXT: s_mov_b32 s5, exec_lo
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s6, s5
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_max_num_f64_e32 v[11:12], v[0:1], v[5:6]
-; GFX12-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
; GFX12-NEXT: .LBB7_4: ; Parent Loop BB7_3 Depth=1
; GFX12-NEXT: ; => This Inner Loop Header: Depth=2
@@ -1948,26 +1942,24 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_remot
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
+; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[8:9], v0, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[8:9], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
-; GFX12-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -2212,26 +2204,24 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
+; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[8:9], v0, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB9_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[8:9], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
-; GFX12-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -2399,7 +2389,6 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2418,14 +2407,13 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, s4, v2
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v0.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v1, v0.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[3:4], v5, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2449,46 +2437,44 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v0, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
-; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v4, s[0:3], null offen
+; GFX12-FAKE16-NEXT: buffer_load_b32 v2, v5, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
; GFX12-FAKE16-NEXT: s_mov_b32 s5, 0
; GFX12-FAKE16-NEXT: .LBB10_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, s4, v2
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], v4, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: v_and_or_b32 v1, v2, s6, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[3:4], v5, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v3
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v2
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v3
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_grained_memory:
@@ -2854,7 +2840,6 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2873,14 +2858,13 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, s4, v2
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v0.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v1, v0.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2903,39 +2887,37 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v0, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
-; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v2, s[0:3], null offen
+; GFX12-FAKE16-NEXT: buffer_load_b32 v2, v3, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
; GFX12-FAKE16-NEXT: s_mov_b32 s5, 0
; GFX12-FAKE16-NEXT: .LBB11_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, s4, v2
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: v_and_or_b32 v1, v2, s6, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
@@ -3297,17 +3279,17 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x200, v4
+; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x200, v4
; GFX12-TRUE16-NEXT: s_mov_b32 s4, exec_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_mov_b32 s5, s4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 3, v4
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, -4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 3, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 3, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, -4, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v9, 0xffff
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v11, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v7, v4, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v11, v7
; GFX12-TRUE16-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s1, v1
@@ -3318,31 +3300,28 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_b32 v6, v10, s[0:3], null offen
+; GFX12-TRUE16-NEXT: buffer_load_b32 v7, v10, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-TRUE16-NEXT: ; %bb.2:
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s4
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v5.l, v5.l
; GFX12-TRUE16-NEXT: s_mov_b32 s4, 0
; GFX12-TRUE16-NEXT: .LBB12_3: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-TRUE16-NEXT: ; Child Loop BB12_4 Depth 2
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v9, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, v4, v7
; GFX12-TRUE16-NEXT: s_mov_b32 s5, exec_lo
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_mov_b32 s6, s5
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v6.l, v5.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v4.h, v4.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v4.h
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v6, v5.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, v4, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v9, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v11, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v6, v7, v11, v6
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX12-TRUE16-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX12-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -3354,14 +3333,14 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[7:8], v10, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[8:9], v10, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_and_not1_wrexec_b32 s6, s6
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_4
; GFX12-TRUE16-NEXT: ; %bb.5: ; in Loop: Header=BB12_3 Depth=1
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s5
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v7, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v8, v7
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v8
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3369,7 +3348,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_3
; GFX12-TRUE16-NEXT: ; %bb.6: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v9, v7
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v4, v8
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu_no_fine_grained_memory:
@@ -3379,17 +3358,17 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x200, v4
+; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x200, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s4, exec_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_mov_b32 s5, s4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 3, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, -4, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 3, v6
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v6
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v10, -4, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v6, v7, 0xffff
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v9, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v7, v4, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v11, v7
; GFX12-FAKE16-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s1, v1
@@ -3400,31 +3379,28 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-FAKE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: buffer_load_b32 v6, v8, s[0:3], null offen
+; GFX12-FAKE16-NEXT: buffer_load_b32 v7, v10, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-FAKE16-NEXT: ; %bb.2:
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v10, v5, v5
; GFX12-FAKE16-NEXT: s_mov_b32 s4, 0
; GFX12-FAKE16-NEXT: .LBB12_3: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-FAKE16-NEXT: ; Child Loop BB12_4 Depth 2
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v7, v6
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, v4, v7
; GFX12-FAKE16-NEXT: s_mov_b32 s5, exec_lo
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_mov_b32 s6, s5
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v10
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, v4, v6
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
-; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
+; GFX12-FAKE16-NEXT: v_and_or_b32 v6, v7, v11, v6
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX12-FAKE16-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -3436,14 +3412,14 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-FAKE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v8, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[8:9], v10, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_and_not1_wrexec_b32 s6, s6
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_4
; GFX12-FAKE16-NEXT: ; %bb.5: ; in Loop: Header=BB12_3 Depth=1
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s5
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v8, v7
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, v8
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3451,7 +3427,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_3
; GFX12-FAKE16-NEXT: ; %bb.6: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v7, v4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v4, v8
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu_no_fine_grained_memory:
@@ -5604,24 +5580,22 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__amdgpu_no
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, s16
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, s16
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s16
; GFX12-TRUE16-NEXT: s_mov_b32 s4, 0
; GFX12-TRUE16-NEXT: s_clause 0x1
-; GFX12-TRUE16-NEXT: buffer_load_u16 v3, v0, s[0:3], null offen offset:1026
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, v0, s[0:3], null offen offset:1026
; GFX12-TRUE16-NEXT: buffer_load_u16 v0, v0, s[0:3], null offen offset:1024
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v2, v1, v1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX12-TRUE16-NEXT: .LBB16_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v0, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v4, v0, v2
+; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v4, v5, v2
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -5642,27 +5616,25 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__amdgpu_no
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, s16 :: v_dual_mov_b32 v2, s16
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v1, s16
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v3, s16
; GFX12-FAKE16-NEXT: s_mov_b32 s4, 0
; GFX12-FAKE16-NEXT: s_clause 0x1
-; GFX12-FAKE16-NEXT: buffer_load_u16 v1, v1, s[0:3], null offen offset:1024
-; GFX12-FAKE16-NEXT: buffer_load_u16 v3, v2, s[0:3], null offen offset:1026
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v2, v0, v0
+; GFX12-FAKE16-NEXT: buffer_load_u16 v0, v0, s[0:3], null offen offset:1024
+; GFX12-FAKE16-NEXT: buffer_load_u16 v1, v1, s[0:3], null offen offset:1026
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x1
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v3, 16, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, s16
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX12-FAKE16-NEXT: .LBB16_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v0, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v4, v0, v2
+; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v4, v5, v2
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -6014,29 +5986,27 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2f16__offset__amdgpu_no_fin
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, s16
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v2, v0, v0
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, s16 :: v_dual_mov_b32 v2, s16
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s16
; GFX12-TRUE16-NEXT: s_mov_b32 s4, 0
; GFX12-TRUE16-NEXT: s_clause 0x1
-; GFX12-TRUE16-NEXT: buffer_load_u16 v3, v1, s[0:3], null offen offset:1026
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, v1, s[0:3], null offen offset:1024
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, v1, s[0:3], null offen offset:1026
+; GFX12-TRUE16-NEXT: buffer_load_u16 v2, v2, s[0:3], null offen offset:1024
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX12-TRUE16-NEXT: .LBB17_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v0, v1, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v1, v2, v0
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v2
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v1
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v4
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-TRUE16-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -6053,31 +6023,29 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2f16__offset__amdgpu_no_fin
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, s16 :: v_dual_mov_b32 v2, s16
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, s16
; GFX12-FAKE16-NEXT: s_mov_b32 s4, 0
; GFX12-FAKE16-NEXT: s_clause 0x1
; GFX12-FAKE16-NEXT: buffer_load_u16 v1, v1, s[0:3], null offen offset:1024
-; GFX12-FAKE16-NEXT: buffer_load_u16 v3, v2, s[0:3], null offen offset:1026
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v2, v0, v0
+; GFX12-FAKE16-NEXT: buffer_load_u16 v2, v2, s[0:3], null offen offset:1026
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, s16
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v2, 16, v1
; GFX12-FAKE16-NEXT: .LBB17_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v0, v1, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v1, v2, v0
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v2
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v1
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-FAKE16-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -6431,7 +6399,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v7, v4, s[0:3], null offen offset:1024
+; GFX12-TRUE16-NEXT: buffer_load_u16 v8, v4, s[0:3], null offen offset:1024
; GFX12-TRUE16-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-TRUE16-NEXT: ; %bb.2:
@@ -6456,22 +6424,19 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-TRUE16-NEXT: ; %bb.4:
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s4
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.h, v6.l
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v8, v5, v5
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.h, v6.l
; GFX12-TRUE16-NEXT: s_mov_b32 s4, 0
; GFX12-TRUE16-NEXT: .LBB18_5: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-TRUE16-NEXT: ; Child Loop BB18_6 Depth 2
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v5, v7, v7
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v7, v8, v5
; GFX12-TRUE16-NEXT: s_mov_b32 s5, exec_lo
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_mov_b32 s6, s5
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v6, v5, v8
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v7 :: v_dual_mov_b32 v7, v8
; GFX12-TRUE16-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX12-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -6483,14 +6448,14 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
+; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[6:7], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_and_not1_wrexec_b32 s6, s6
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB18_6
; GFX12-TRUE16-NEXT: ; %bb.7: ; in Loop: Header=BB18_5 Depth=1
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s5
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v6, v8
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v8, v6
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6498,7 +6463,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB18_5
; GFX12-TRUE16-NEXT: ; %bb.8: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, v5
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, v6
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall__amdgpu_no_fine_grained_memory:
@@ -6546,22 +6511,19 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-FAKE16-NEXT: ; %bb.4:
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s4
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_perm_b32 v7, v7, v6, 0x5040100
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v8, v5, v5
+; GFX12-FAKE16-NEXT: v_perm_b32 v8, v7, v6, 0x5040100
; GFX12-FAKE16-NEXT: s_mov_b32 s4, 0
; GFX12-FAKE16-NEXT: .LBB18_5: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-FAKE16-NEXT: ; Child Loop BB18_6 Depth 2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v5, v7, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v7, v8, v5
; GFX12-FAKE16-NEXT: s_mov_b32 s5, exec_lo
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_mov_b32 s6, s5
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v6, v5, v8
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v6, v7 :: v_dual_mov_b32 v7, v8
; GFX12-FAKE16-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -6573,14 +6535,14 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-FAKE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-FAKE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[6:7], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_and_not1_wrexec_b32 s6, s6
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB18_6
; GFX12-FAKE16-NEXT: ; %bb.7: ; in Loop: Header=BB18_5 Depth=1
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s5
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, v5
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v6, v8
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v8, v6
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6588,7 +6550,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB18_5
; GFX12-FAKE16-NEXT: ; %bb.8: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, v5
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, v6
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall__amdgpu_no_fine_grained_memory:
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
index b7efd8ea18d8c..184ed3caef882 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
@@ -1172,26 +1172,24 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
+; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[8:9], v0, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB5_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[8:9], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
-; GFX12-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -1355,24 +1353,22 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
; GFX12-NEXT: v_mov_b32_e32 v6, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[2:3], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB6_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[0:1]
+; GFX12-NEXT: v_dual_mov_b32 v10, v5 :: v_dual_mov_b32 v9, v4
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v10, v3 :: v_dual_mov_b32 v9, v2
-; GFX12-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v7, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[7:10], v6, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v4, v7 :: v_dual_mov_b32 v5, v8
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -1555,20 +1551,18 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: s_cbranch_execnz .LBB7_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_mov_b32 exec_lo, s4
-; GFX12-NEXT: v_max_num_f64_e32 v[5:6], v[5:6], v[5:6]
; GFX12-NEXT: s_mov_b32 s4, 0
; GFX12-NEXT: .LBB7_3: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Loop Header: Depth=1
; GFX12-NEXT: ; Child Loop BB7_4 Depth 2
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[13:14], v[13:14]
+; GFX12-NEXT: v_min_num_f64_e32 v[11:12], v[13:14], v[5:6]
+; GFX12-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
; GFX12-NEXT: s_mov_b32 s5, exec_lo
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s6, s5
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_min_num_f64_e32 v[11:12], v[0:1], v[5:6]
-; GFX12-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
; GFX12-NEXT: .LBB7_4: ; Parent Loop BB7_3 Depth=1
; GFX12-NEXT: ; => This Inner Loop Header: Depth=2
@@ -1948,26 +1942,24 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_remot
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
+; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[8:9], v0, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[8:9], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
-; GFX12-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -2212,26 +2204,24 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
+; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[8:9], v0, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB9_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[8:9], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
-; GFX12-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -2399,7 +2389,6 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2418,14 +2407,13 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, s4, v2
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v0.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v1, v0.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[3:4], v5, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2449,46 +2437,44 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v0, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
-; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v4, s[0:3], null offen
+; GFX12-FAKE16-NEXT: buffer_load_b32 v2, v5, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
; GFX12-FAKE16-NEXT: s_mov_b32 s5, 0
; GFX12-FAKE16-NEXT: .LBB10_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, s4, v2
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], v4, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: v_and_or_b32 v1, v2, s6, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[3:4], v5, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v3
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v2
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v3
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_grained_memory:
@@ -2854,7 +2840,6 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2873,14 +2858,13 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, s4, v2
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v0.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v1, v0.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2903,39 +2887,37 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v0, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
-; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v2, s[0:3], null offen
+; GFX12-FAKE16-NEXT: buffer_load_b32 v2, v3, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
; GFX12-FAKE16-NEXT: s_mov_b32 s5, 0
; GFX12-FAKE16-NEXT: .LBB11_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, s4, v2
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: v_and_or_b32 v1, v2, s6, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
@@ -3297,17 +3279,17 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x200, v4
+; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x200, v4
; GFX12-TRUE16-NEXT: s_mov_b32 s4, exec_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_mov_b32 s5, s4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 3, v4
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, -4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 3, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 3, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, -4, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v9, 0xffff
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v11, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v7, v4, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v11, v7
; GFX12-TRUE16-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s1, v1
@@ -3318,31 +3300,28 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_b32 v6, v10, s[0:3], null offen
+; GFX12-TRUE16-NEXT: buffer_load_b32 v7, v10, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-TRUE16-NEXT: ; %bb.2:
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s4
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v5.l, v5.l
; GFX12-TRUE16-NEXT: s_mov_b32 s4, 0
; GFX12-TRUE16-NEXT: .LBB12_3: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-TRUE16-NEXT: ; Child Loop BB12_4 Depth 2
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v9, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, v4, v7
; GFX12-TRUE16-NEXT: s_mov_b32 s5, exec_lo
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_mov_b32 s6, s5
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.h, v6.l, v5.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v4.h, v4.h, v4.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v4.h
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v6, v5.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, v4, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v9, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v11, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v6, v7, v11, v6
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX12-TRUE16-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX12-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -3354,14 +3333,14 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[7:8], v10, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[8:9], v10, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_and_not1_wrexec_b32 s6, s6
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_4
; GFX12-TRUE16-NEXT: ; %bb.5: ; in Loop: Header=BB12_3 Depth=1
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s5
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v7, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v8, v7
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v8
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3369,7 +3348,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_3
; GFX12-TRUE16-NEXT: ; %bb.6: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v9, v7
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v4, v8
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu_no_fine_grained_memory:
@@ -3379,17 +3358,17 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x200, v4
+; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x200, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s4, exec_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_mov_b32 s5, s4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 3, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, -4, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 3, v6
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v6
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v10, -4, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v6, v7, 0xffff
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v9, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v7, v4, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v11, v7
; GFX12-FAKE16-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s1, v1
@@ -3400,31 +3379,28 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-FAKE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: buffer_load_b32 v6, v8, s[0:3], null offen
+; GFX12-FAKE16-NEXT: buffer_load_b32 v7, v10, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-FAKE16-NEXT: ; %bb.2:
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v10, v5, v5
; GFX12-FAKE16-NEXT: s_mov_b32 s4, 0
; GFX12-FAKE16-NEXT: .LBB12_3: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-FAKE16-NEXT: ; Child Loop BB12_4 Depth 2
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v7, v6
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, v4, v7
; GFX12-FAKE16-NEXT: s_mov_b32 s5, exec_lo
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_mov_b32 s6, s5
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v6, v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v4, v4, v10
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, v4, v6
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
-; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
+; GFX12-FAKE16-NEXT: v_and_or_b32 v6, v7, v11, v6
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX12-FAKE16-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -3436,14 +3412,14 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-FAKE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v8, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[8:9], v10, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_and_not1_wrexec_b32 s6, s6
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_4
; GFX12-FAKE16-NEXT: ; %bb.5: ; in Loop: Header=BB12_3 Depth=1
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s5
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v8, v7
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, v8
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3451,7 +3427,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_3
; GFX12-FAKE16-NEXT: ; %bb.6: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v7, v4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v4, v8
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu_no_fine_grained_memory:
@@ -5604,24 +5580,22 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__amdgpu_no
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, s16
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, s16
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s16
; GFX12-TRUE16-NEXT: s_mov_b32 s4, 0
; GFX12-TRUE16-NEXT: s_clause 0x1
-; GFX12-TRUE16-NEXT: buffer_load_u16 v3, v0, s[0:3], null offen offset:1026
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, v0, s[0:3], null offen offset:1026
; GFX12-TRUE16-NEXT: buffer_load_u16 v0, v0, s[0:3], null offen offset:1024
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v2, v1, v1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX12-TRUE16-NEXT: .LBB16_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v0, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_pk_min_num_f16 v4, v0, v2
+; GFX12-TRUE16-NEXT: v_pk_min_num_f16 v4, v5, v2
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -5642,27 +5616,25 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__amdgpu_no
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, s16 :: v_dual_mov_b32 v2, s16
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v1, s16
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v3, s16
; GFX12-FAKE16-NEXT: s_mov_b32 s4, 0
; GFX12-FAKE16-NEXT: s_clause 0x1
-; GFX12-FAKE16-NEXT: buffer_load_u16 v1, v1, s[0:3], null offen offset:1024
-; GFX12-FAKE16-NEXT: buffer_load_u16 v3, v2, s[0:3], null offen offset:1026
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v2, v0, v0
+; GFX12-FAKE16-NEXT: buffer_load_u16 v0, v0, s[0:3], null offen offset:1024
+; GFX12-FAKE16-NEXT: buffer_load_u16 v1, v1, s[0:3], null offen offset:1026
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x1
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v3, 16, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, s16
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX12-FAKE16-NEXT: .LBB16_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v0, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_pk_min_num_f16 v4, v0, v2
+; GFX12-FAKE16-NEXT: v_pk_min_num_f16 v4, v5, v2
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -6014,29 +5986,27 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2f16__offset__amdgpu_no_fin
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, s16
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v2, v0, v0
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, s16 :: v_dual_mov_b32 v2, s16
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s16
; GFX12-TRUE16-NEXT: s_mov_b32 s4, 0
; GFX12-TRUE16-NEXT: s_clause 0x1
-; GFX12-TRUE16-NEXT: buffer_load_u16 v3, v1, s[0:3], null offen offset:1026
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, v1, s[0:3], null offen offset:1024
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, v1, s[0:3], null offen offset:1026
+; GFX12-TRUE16-NEXT: buffer_load_u16 v2, v2, s[0:3], null offen offset:1024
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX12-TRUE16-NEXT: .LBB17_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v0, v1, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_pk_min_num_f16 v1, v2, v0
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v2
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v1
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v4
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-TRUE16-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -6053,31 +6023,29 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2f16__offset__amdgpu_no_fin
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, s16 :: v_dual_mov_b32 v2, s16
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, s16
; GFX12-FAKE16-NEXT: s_mov_b32 s4, 0
; GFX12-FAKE16-NEXT: s_clause 0x1
; GFX12-FAKE16-NEXT: buffer_load_u16 v1, v1, s[0:3], null offen offset:1024
-; GFX12-FAKE16-NEXT: buffer_load_u16 v3, v2, s[0:3], null offen offset:1026
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v2, v0, v0
+; GFX12-FAKE16-NEXT: buffer_load_u16 v2, v2, s[0:3], null offen offset:1026
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, s16
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v2, 16, v1
; GFX12-FAKE16-NEXT: .LBB17_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v0, v1, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_pk_min_num_f16 v1, v2, v0
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v2
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v1
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-FAKE16-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -6431,7 +6399,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v7, v4, s[0:3], null offen offset:1024
+; GFX12-TRUE16-NEXT: buffer_load_u16 v8, v4, s[0:3], null offen offset:1024
; GFX12-TRUE16-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-TRUE16-NEXT: ; %bb.2:
@@ -6456,22 +6424,19 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-TRUE16-NEXT: ; %bb.4:
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s4
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.h, v6.l
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v8, v5, v5
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.h, v6.l
; GFX12-TRUE16-NEXT: s_mov_b32 s4, 0
; GFX12-TRUE16-NEXT: .LBB18_5: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-TRUE16-NEXT: ; Child Loop BB18_6 Depth 2
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v5, v7, v7
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_pk_min_num_f16 v7, v8, v5
; GFX12-TRUE16-NEXT: s_mov_b32 s5, exec_lo
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_mov_b32 s6, s5
-; GFX12-TRUE16-NEXT: v_pk_min_num_f16 v6, v5, v8
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v7 :: v_dual_mov_b32 v7, v8
; GFX12-TRUE16-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX12-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -6483,14 +6448,14 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-TRUE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
+; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[6:7], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_and_not1_wrexec_b32 s6, s6
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB18_6
; GFX12-TRUE16-NEXT: ; %bb.7: ; in Loop: Header=BB18_5 Depth=1
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s5
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v6, v8
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v8, v6
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6498,7 +6463,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB18_5
; GFX12-TRUE16-NEXT: ; %bb.8: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, v5
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, v6
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall__amdgpu_no_fine_grained_memory:
@@ -6546,22 +6511,19 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-FAKE16-NEXT: ; %bb.4:
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s4
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_perm_b32 v7, v7, v6, 0x5040100
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v8, v5, v5
+; GFX12-FAKE16-NEXT: v_perm_b32 v8, v7, v6, 0x5040100
; GFX12-FAKE16-NEXT: s_mov_b32 s4, 0
; GFX12-FAKE16-NEXT: .LBB18_5: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-FAKE16-NEXT: ; Child Loop BB18_6 Depth 2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v5, v7, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_pk_min_num_f16 v7, v8, v5
; GFX12-FAKE16-NEXT: s_mov_b32 s5, exec_lo
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_mov_b32 s6, s5
-; GFX12-FAKE16-NEXT: v_pk_min_num_f16 v6, v5, v8
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v6, v7 :: v_dual_mov_b32 v7, v8
; GFX12-FAKE16-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -6573,14 +6535,14 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-FAKE16-NEXT: v_cmpx_eq_u64_e32 s[0:1], v[0:1]
; GFX12-FAKE16-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[6:7], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_and_not1_wrexec_b32 s6, s6
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB18_6
; GFX12-FAKE16-NEXT: ; %bb.7: ; in Loop: Header=BB18_5 Depth=1
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s5
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, v5
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v6, v8
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v8, v6
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6588,7 +6550,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB18_5
; GFX12-FAKE16-NEXT: ; %bb.8: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, v5
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, v6
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall__amdgpu_no_fine_grained_memory:
diff --git a/llvm/test/CodeGen/AMDGPU/clamp.ll b/llvm/test/CodeGen/AMDGPU/clamp.ll
index ec8e5654356ed..4b4597d72e6a7 100644
--- a/llvm/test/CodeGen/AMDGPU/clamp.ll
+++ b/llvm/test/CodeGen/AMDGPU/clamp.ll
@@ -415,12 +415,11 @@ define amdgpu_kernel void @v_clamp_negzero_maybe_snan_f32(ptr addrspace(1) %out,
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX12-NEXT: v_maxmin_num_f32 v1, v1, 0x80000000, 1.0
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-NEXT: s_endpgm
@@ -520,9 +519,7 @@ define amdgpu_kernel void @v_clamp_multi_use_max_f32(ptr addrspace(1) %out, ptr
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX12-NEXT: v_max_num_f32_e32 v1, 0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v2, 1.0, v1
; GFX12-NEXT: global_store_b32 v0, v2, s[0:1]
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -3266,9 +3263,7 @@ define amdgpu_kernel void @v_clamp_v2f16_not_zero(ptr addrspace(1) %out, ptr add
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, 2.0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, 1.0 op_sel_hi:[1,0]
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-NEXT: s_endpgm
@@ -3373,9 +3368,7 @@ define amdgpu_kernel void @v_clamp_v2f16_not_one(ptr addrspace(1) %out, ptr addr
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, 0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, 1.0 op_sel:[0,1] op_sel_hi:[1,0]
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
index 91d75d7077259..808cc8eb99b22 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
@@ -2802,29 +2802,27 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB18_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB18_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2833,7 +2831,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB18_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -2842,16 +2840,14 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB18_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory:
@@ -3192,7 +3188,6 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0x7f8, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
@@ -3218,9 +3213,8 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[8:9], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[4:5], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3240,13 +3234,11 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX12-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -3604,7 +3596,6 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v1, vcc_lo
@@ -3630,9 +3621,8 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[8:9], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[4:5], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3652,13 +3642,11 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX12-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4017,7 +4005,6 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4033,20 +4020,18 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB21_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB21_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4055,19 +4040,17 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB21_2
; GFX12-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4403,14 +4386,13 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0x7f8, v0
+; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0x7f8, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v1, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v7
+; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
@@ -4422,20 +4404,18 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB22_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB22_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4443,20 +4423,18 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execnz .LBB22_4
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB22_2
; GFX12-NEXT: .LBB22_6: ; %atomicrmw.private
-; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4808,14 +4786,13 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0xfffff800, v0
+; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, -1, v1, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v7
+; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
@@ -4827,20 +4804,18 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB23_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB23_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4848,20 +4823,18 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execnz .LBB23_4
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB23_2
; GFX12-NEXT: .LBB23_6: ; %atomicrmw.private
-; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -5214,29 +5187,27 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB24_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -5245,7 +5216,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB24_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -5254,16 +5225,14 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory:
@@ -5638,29 +5607,27 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB25_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB25_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -5669,7 +5636,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB25_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -5678,16 +5645,14 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB25_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
@@ -6033,9 +5998,8 @@ define half @flat_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
@@ -6049,12 +6013,11 @@ define half @flat_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6079,9 +6042,8 @@ define half @flat_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
@@ -6095,12 +6057,11 @@ define half @flat_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6421,35 +6382,31 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -6460,7 +6417,7 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -6473,15 +6430,13 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6489,12 +6444,11 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6827,35 +6781,31 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -6866,7 +6816,7 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grained_memory:
@@ -6879,15 +6829,13 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6895,12 +6843,11 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7235,9 +7182,8 @@ define void @flat_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
@@ -7250,12 +7196,10 @@ define void @flat_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v3.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7280,9 +7224,8 @@ define void @flat_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
@@ -7295,12 +7238,10 @@ define void @flat_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7613,38 +7554,33 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v6, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7661,37 +7597,33 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8009,38 +7941,33 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v6, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8057,37 +7984,33 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8407,17 +8330,15 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: flat_load_b32 v3, v[0:1] offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -8442,17 +8363,15 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1] offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -8708,16 +8627,13 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1] offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -8741,24 +8657,21 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1] offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v2, v2
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1] offset:2046
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v3, v3
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -9001,36 +8914,32 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -9041,7 +8950,7 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -9054,15 +8963,13 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9070,12 +8977,11 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -9412,39 +9318,34 @@ define void @flat_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v6, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -9461,38 +9362,34 @@ define void @flat_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -13271,15 +13168,13 @@ define <2 x half> @flat_agent_atomic_fmax_ret_v2f16__amdgpu_no_fine_grained_memo
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -13502,15 +13397,13 @@ define <2 x half> @flat_agent_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no_fi
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB47_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -13738,15 +13631,13 @@ define <2 x half> @flat_agent_atomic_fmax_ret_v2f16__offset12b_neg__amdgpu_no_fi
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB48_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -13988,21 +13879,18 @@ define void @flat_agent_atomic_fmax_noret_v2f16__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB49_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14209,21 +14097,18 @@ define void @flat_agent_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1] offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB50_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14437,21 +14322,18 @@ define void @flat_agent_atomic_fmax_noret_v2f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1] offset:-2048
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB51_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14685,15 +14567,13 @@ define <2 x half> @flat_system_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no_f
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -14924,22 +14804,19 @@ define void @flat_system_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fine_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1] offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
index f5564f14eee24..a9cbf9c450f6a 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
@@ -2802,29 +2802,27 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB18_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB18_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2833,7 +2831,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB18_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -2842,16 +2840,14 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB18_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory:
@@ -3192,7 +3188,6 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0x7f8, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
@@ -3218,9 +3213,8 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[8:9], v[8:9]
-; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[8:9], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[4:5], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3240,13 +3234,11 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX12-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -3604,7 +3596,6 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v1, vcc_lo
@@ -3630,9 +3621,8 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[8:9], v[8:9]
-; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[8:9], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[4:5], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3652,13 +3642,11 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX12-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4017,7 +4005,6 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4033,20 +4020,18 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB21_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB21_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4055,19 +4040,17 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB21_2
; GFX12-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4403,14 +4386,13 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0x7f8, v0
+; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0x7f8, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v1, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v7
+; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
@@ -4422,20 +4404,18 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB22_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB22_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4443,20 +4423,18 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execnz .LBB22_4
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB22_2
; GFX12-NEXT: .LBB22_6: ; %atomicrmw.private
-; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4808,14 +4786,13 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0xfffff800, v0
+; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, -1, v1, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v7
+; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
@@ -4827,20 +4804,18 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB23_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB23_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4848,20 +4823,18 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execnz .LBB23_4
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB23_2
; GFX12-NEXT: .LBB23_6: ; %atomicrmw.private
-; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -5214,29 +5187,27 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB24_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -5245,7 +5216,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB24_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -5254,16 +5225,14 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory:
@@ -5638,29 +5607,27 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e32 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB25_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB25_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -5669,7 +5636,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB25_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -5678,16 +5645,14 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB25_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
@@ -6033,9 +5998,8 @@ define half @flat_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
@@ -6049,12 +6013,11 @@ define half @flat_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v2.h, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6079,9 +6042,8 @@ define half @flat_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
@@ -6095,12 +6057,11 @@ define half @flat_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6421,35 +6382,31 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -6460,7 +6417,7 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -6473,15 +6430,13 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6489,12 +6444,11 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6827,35 +6781,31 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -6866,7 +6816,7 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grained_memory:
@@ -6879,15 +6829,13 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6895,12 +6843,11 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7235,9 +7182,8 @@ define void @flat_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
@@ -7250,12 +7196,10 @@ define void @flat_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v3.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.l, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7280,9 +7224,8 @@ define void @flat_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
@@ -7295,12 +7238,10 @@ define void @flat_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7613,38 +7554,33 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v6, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7661,37 +7597,33 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8009,38 +7941,33 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v6, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8057,37 +7984,33 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8407,17 +8330,15 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: flat_load_b32 v3, v[0:1] offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v4.l, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -8442,17 +8363,15 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1] offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v4
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -8708,16 +8627,13 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1] offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v4.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v2.h, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -8741,24 +8657,21 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1] offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v2, v2
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1] offset:2046
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v3, v3
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -9001,36 +8914,32 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -9041,7 +8950,7 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -9054,15 +8963,13 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9070,12 +8977,11 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -9412,39 +9318,34 @@ define void @flat_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v6, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -9461,38 +9362,34 @@ define void @flat_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -13271,15 +13168,13 @@ define <2 x half> @flat_agent_atomic_fmin_ret_v2f16__amdgpu_no_fine_grained_memo
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -13502,15 +13397,13 @@ define <2 x half> @flat_agent_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no_fi
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB47_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -13738,15 +13631,13 @@ define <2 x half> @flat_agent_atomic_fmin_ret_v2f16__offset12b_neg__amdgpu_no_fi
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB48_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -13988,21 +13879,18 @@ define void @flat_agent_atomic_fmin_noret_v2f16__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB49_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14209,21 +14097,18 @@ define void @flat_agent_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1] offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB50_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14437,21 +14322,18 @@ define void @flat_agent_atomic_fmin_noret_v2f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1] offset:-2048
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB51_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14685,15 +14567,13 @@ define <2 x half> @flat_system_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no_f
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -14924,22 +14804,19 @@ define void @flat_system_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fine_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1] offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
index fef768a24355e..f40b209b77da7 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
@@ -13957,13 +13957,10 @@ define double @flat_atomic_fmax_f64_saddr_rtn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: ; %bb.4: ; %atomicrmw.private
; GFX1250-SDAG-NEXT: s_sub_co_i32 s2, s0, src_flat_scratch_base_lo
; GFX1250-SDAG-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-SDAG-NEXT: s_cselect_b32 s0, s2, -1
; GFX1250-SDAG-NEXT: scratch_load_b64 v[2:3], off, s0
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[0:1]
+; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-SDAG-NEXT: .LBB112_5: ; %atomicrmw.end
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
@@ -14115,12 +14112,9 @@ define void @flat_atomic_fmax_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: ; %bb.3: ; %atomicrmw.private
; GFX1250-SDAG-NEXT: s_sub_co_i32 s2, s0, src_flat_scratch_base_lo
; GFX1250-SDAG-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-SDAG-NEXT: s_cselect_b32 s0, s2, -1
; GFX1250-SDAG-NEXT: scratch_load_b64 v[2:3], off, s0
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-SDAG-NEXT: .LBB113_4: ; %atomicrmw.phi
@@ -14264,13 +14258,10 @@ define double @flat_atomic_fmin_f64_saddr_rtn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: ; %bb.4: ; %atomicrmw.private
; GFX1250-SDAG-NEXT: s_sub_co_i32 s2, s0, src_flat_scratch_base_lo
; GFX1250-SDAG-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-SDAG-NEXT: s_cselect_b32 s0, s2, -1
; GFX1250-SDAG-NEXT: scratch_load_b64 v[2:3], off, s0
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[0:1]
+; GFX1250-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-SDAG-NEXT: .LBB114_5: ; %atomicrmw.end
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
@@ -14422,12 +14413,9 @@ define void @flat_atomic_fmin_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: ; %bb.3: ; %atomicrmw.private
; GFX1250-SDAG-NEXT: s_sub_co_i32 s2, s0, src_flat_scratch_base_lo
; GFX1250-SDAG-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-SDAG-NEXT: s_cselect_b32 s0, s2, -1
; GFX1250-SDAG-NEXT: scratch_load_b64 v[2:3], off, s0
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-SDAG-NEXT: .LBB115_4: ; %atomicrmw.phi
@@ -14824,29 +14812,27 @@ define <2 x half> @flat_atomic_fmax_v2f16_saddr_rtn(ptr inreg %ptr, <2 x half> %
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, 0
+; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_mov_b32 s2, 0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-NEXT: flat_load_b32 v0, v2, s[0:1] offset:40
+; GFX1250-NEXT: flat_load_b32 v1, v2, s[0:1] offset:40
; GFX1250-NEXT: .LBB124_1: ; %atomicrmw.start
; GFX1250-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_mov_b32_e32 v5, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_max_num_f16 v0, v5, v5
-; GFX1250-NEXT: v_pk_max_num_f16 v4, v0, v1
+; GFX1250-NEXT: v_mov_b32_e32 v5, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_pk_max_num_f16 v4, v5, v0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v2, v[4:5], s[0:1] offset:40 th:TH_ATOMIC_RETURN
+; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v2, v[4:5], s[0:1] offset:40 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v5
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v5
; GFX1250-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1250-NEXT: s_cbranch_execnz .LBB124_1
; GFX1250-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1250-NEXT: v_mov_b32_e32 v0, v1
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
; GFX950-LABEL: flat_atomic_fmax_v2f16_saddr_rtn:
@@ -14883,22 +14869,19 @@ define void @flat_atomic_fmax_v2f16_saddr_nortn(ptr inreg %ptr, <2 x half> %data
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
-; GFX1250-NEXT: v_pk_max_num_f16 v3, v0, v0
+; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: s_mov_b32 s2, 0
-; GFX1250-NEXT: flat_load_b32 v1, v2, s[0:1] offset:40
+; GFX1250-NEXT: flat_load_b32 v3, v1, s[0:1] offset:40
; GFX1250-NEXT: .LBB125_1: ; %atomicrmw.start
; GFX1250-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_pk_max_num_f16 v0, v1, v1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_max_num_f16 v0, v0, v3
+; GFX1250-NEXT: v_pk_max_num_f16 v2, v3, v0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v2, v[0:1], s[0:1] offset:40 th:TH_ATOMIC_RETURN
+; GFX1250-NEXT: flat_atomic_cmpswap_b32 v2, v1, v[2:3], s[0:1] offset:40 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_mov_b32_e32 v1, v0
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_mov_b32_e32 v3, v2
; GFX1250-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_not1_b32 exec_lo, exec_lo, s2
@@ -14941,29 +14924,27 @@ define <2 x half> @flat_atomic_fmin_v2f16_saddr_rtn(ptr inreg %ptr, <2 x half> %
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, 0
+; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_mov_b32 s2, 0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-NEXT: flat_load_b32 v0, v2, s[0:1] offset:40
+; GFX1250-NEXT: flat_load_b32 v1, v2, s[0:1] offset:40
; GFX1250-NEXT: .LBB126_1: ; %atomicrmw.start
; GFX1250-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_mov_b32_e32 v5, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_max_num_f16 v0, v5, v5
-; GFX1250-NEXT: v_pk_min_num_f16 v4, v0, v1
+; GFX1250-NEXT: v_mov_b32_e32 v5, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_pk_min_num_f16 v4, v5, v0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v2, v[4:5], s[0:1] offset:40 th:TH_ATOMIC_RETURN
+; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v2, v[4:5], s[0:1] offset:40 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v5
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v5
; GFX1250-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1250-NEXT: s_cbranch_execnz .LBB126_1
; GFX1250-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1250-NEXT: v_mov_b32_e32 v0, v1
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
; GFX950-LABEL: flat_atomic_fmin_v2f16_saddr_rtn:
@@ -15000,22 +14981,19 @@ define void @flat_atomic_fmin_v2f16_saddr_nortn(ptr inreg %ptr, <2 x half> %data
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
-; GFX1250-NEXT: v_pk_max_num_f16 v3, v0, v0
+; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: s_mov_b32 s2, 0
-; GFX1250-NEXT: flat_load_b32 v1, v2, s[0:1] offset:40
+; GFX1250-NEXT: flat_load_b32 v3, v1, s[0:1] offset:40
; GFX1250-NEXT: .LBB127_1: ; %atomicrmw.start
; GFX1250-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_pk_max_num_f16 v0, v1, v1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_min_num_f16 v0, v0, v3
+; GFX1250-NEXT: v_pk_min_num_f16 v2, v3, v0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v2, v[0:1], s[0:1] offset:40 th:TH_ATOMIC_RETURN
+; GFX1250-NEXT: flat_atomic_cmpswap_b32 v2, v1, v[2:3], s[0:1] offset:40 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_mov_b32_e32 v1, v0
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_mov_b32_e32 v3, v2
; GFX1250-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_not1_b32 exec_lo, exec_lo, s2
diff --git a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
index cb64b3de060ff..7f6c62a5e0baf 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
@@ -1239,12 +1239,9 @@ define <2 x half> @v_max3_v2f16_maximumnum_maximumnum__v_v_v_0(<2 x half> %a, <2
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX12-NEXT: v_pk_max_num_f16 v1, v2, v2
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call <2 x half> @llvm.maximumnum.v2f16(<2 x half> %a, <2 x half> %b)
%max3 = call <2 x half> @llvm.maximumnum.v2f16(<2 x half> %tmp0, <2 x half> %c)
@@ -1411,18 +1408,11 @@ define <3 x half> @v_max3_v3f16_maximumnum_maximumnum__v_v_v_0(<3 x half> %a, <3
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_max_num_f16 v2, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v4, v5, v5
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v4
+; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call <3 x half> @llvm.maximumnum.v3f16(<3 x half> %a, <3 x half> %b)
%max3 = call <3 x half> @llvm.maximumnum.v3f16(<3 x half> %tmp0, <3 x half> %c)
@@ -1621,18 +1611,11 @@ define <4 x half> @v_max3_v4f16_maximumnum_maximumnum__v_v_v_0(<4 x half> %a, <4
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_max_num_f16 v2, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v4, v5, v5
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v4
+; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call <4 x half> @llvm.maximumnum.v4f16(<4 x half> %a, <4 x half> %b)
%max3 = call <4 x half> @llvm.maximumnum.v4f16(<4 x half> %tmp0, <4 x half> %c)
@@ -1718,11 +1701,8 @@ define double @v_max3_f64_maximumnum_maximumnum__v_v_v_0(double %a, double %b, d
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call double @llvm.maximumnum.f64(double %a, double %b)
@@ -3196,11 +3176,7 @@ define float @v_min3_f32_maximumnum_neg_maximumnum__v_v_v_0(float %a, float %b,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2
+; GFX12-NEXT: v_minmax_num_f32 v0, v0, -v1, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%tmp0 = call float @llvm.maximumnum.f32(float %neg.a, float %b)
@@ -3284,13 +3260,9 @@ define float @v_min3_f32_maximumnum_fabs_maximumnum__v_v_v_0(float %a, float %b,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
-; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v2
-; GFX12-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_max_num_f32_e64 v0, |v0|, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%tmp0 = call float @llvm.maximumnum.f32(float %neg.a, float %b)
@@ -3374,13 +3346,9 @@ define float @v_min3_f32_maximumnum_fneg_fabs_maximumnum__v_v_v_0(float %a, floa
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
-; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v2
-; GFX12-NEXT: v_or_b32_e32 v0, 0x80000000, v0
+; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_max_num_f32_e64 v0, -|v0|, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%tmp0 = call float @llvm.maximumnum.f32(float %neg.a, float %b)
diff --git a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
index 58b3ae94b5434..2a7198e579d42 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
@@ -62,12 +62,11 @@ define amdgpu_kernel void @test_fmax_f32_ieee_mode_on(ptr addrspace(1) %out, flo
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s2, s2
+; GFX12-SDAG-NEXT: s_max_num_f32 s2, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v1, v0
; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -185,12 +184,10 @@ define amdgpu_kernel void @test_fmax_v2f32(ptr addrspace(1) %out, <2 x float> %a
; GFX12-SDAG-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s6, -1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s1, s1
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v3, s0, s0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v0 :: v_dual_max_num_f32 v0, v3, v2
+; GFX12-SDAG-NEXT: s_max_num_f32 s0, s0, s2
+; GFX12-SDAG-NEXT: s_max_num_f32 s1, s1, s3
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -306,18 +303,15 @@ define amdgpu_kernel void @test_fmax_v3f32(ptr addrspace(1) %out, <3 x float> %a
; GFX12-SDAG-NEXT: s_clause 0x1
; GFX12-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_max_num_f32 s2, s8, s12
+; GFX12-SDAG-NEXT: s_max_num_f32 s3, s9, s13
+; GFX12-SDAG-NEXT: s_max_num_f32 s4, s10, s14
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, s4
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v3, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s12, s12
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s8, s8
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v2, v1, v0 :: v_dual_max_num_f32 v1, v4, v3
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v6, v5
; GFX12-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -448,20 +442,16 @@ define amdgpu_kernel void @test_fmax_v4f32(ptr addrspace(1) %out, <4 x float> %a
; GFX12-SDAG-NEXT: s_clause 0x1
; GFX12-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_max_num_f32 s2, s8, s12
+; GFX12-SDAG-NEXT: s_max_num_f32 s3, s9, s13
+; GFX12-SDAG-NEXT: s_max_num_f32 s4, s10, s14
+; GFX12-SDAG-NEXT: s_max_num_f32 s5, s11, s15
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s15, s15
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s12, s12
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s8, s8
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v1, v0 :: v_dual_max_num_f32 v2, v4, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v6, v5 :: v_dual_max_num_f32 v0, v8, v7
; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -649,33 +639,24 @@ define amdgpu_kernel void @test_fmax_v8f32(ptr addrspace(1) %out, <8 x float> %a
; GFX12-SDAG-NEXT: s_clause 0x1
; GFX12-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x44
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_max_num_f32 s4, s9, s17
+; GFX12-SDAG-NEXT: s_max_num_f32 s5, s8, s16
+; GFX12-SDAG-NEXT: s_max_num_f32 s6, s12, s20
+; GFX12-SDAG-NEXT: s_max_num_f32 s7, s13, s21
+; GFX12-SDAG-NEXT: s_max_num_f32 s8, s14, s22
+; GFX12-SDAG-NEXT: s_max_num_f32 s9, s15, s23
+; GFX12-SDAG-NEXT: s_max_num_f32 s2, s11, s19
+; GFX12-SDAG-NEXT: s_max_num_f32 s3, s10, s18
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, s4
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v7, s2
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s19, s19
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s18, s18
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s17, s17
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s23, s23
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v10, s15, s15
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v11, s22, s22
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s21, s21
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v14, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v15, s20, s20
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v16, s12, s12
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s16, s16
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s8, s8
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v1, v0 :: v_dual_max_num_f32 v2, v4, v2
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v6, v5 :: v_dual_max_num_f32 v6, v12, v11
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v7, v10, v7 :: v_dual_max_num_f32 v0, v9, v8
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v5, v14, v13 :: v_dual_max_num_f32 v4, v16, v15
; GFX12-SDAG-NEXT: s_clause 0x1
-; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
-; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:16
+; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: test_fmax_v8f32:
@@ -992,63 +973,42 @@ define amdgpu_kernel void @test_fmax_v16f32(ptr addrspace(1) %out, <16 x float>
; GFX12-SDAG-LABEL: test_fmax_v16f32:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x2
-; GFX12-SDAG-NEXT: s_load_b512 s[36:51], s[4:5], 0xa4
; GFX12-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x64
+; GFX12-SDAG-NEXT: s_load_b512 s[36:51], s[4:5], 0xa4
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s39, s39
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s38, s38
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s37, s37
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s43, s43
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s15, s15
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s42, s42
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v10, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v11, s41, s41
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s47, s47
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v14, s19, s19
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v1, v0 :: v_dual_max_num_f32 v2, v4, v2
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v7, v8, v7
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s46, s46
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s18, s18
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v1, v6, v5
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v6, v10, v9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s45, s45
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s17, s17
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v5, v12, v11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v18, s40, s40
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v19, s12, s12
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v10, v4, v0
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v9, v9, v8
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s51, s51
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s23, s23
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s50, s50
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v20, s49, s49
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v21, s21, s21
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v22, s48, s48
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v23, s20, s20
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v11, v14, v13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s22, s22
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s44, s44
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v24, s16, s16
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v16, s36, s36
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v17, s8, s8
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v15, v8, v4
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v14, v13, v12
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v13, v21, v20 :: v_dual_max_num_f32 v12, v23, v22
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v8, v24, v0
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v4, v19, v18
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v17, v16
+; GFX12-SDAG-NEXT: s_max_num_f32 s4, s11, s39
+; GFX12-SDAG-NEXT: s_max_num_f32 s5, s10, s38
+; GFX12-SDAG-NEXT: s_max_num_f32 s6, s9, s37
+; GFX12-SDAG-NEXT: s_max_num_f32 s7, s8, s36
+; GFX12-SDAG-NEXT: s_max_num_f32 s8, s15, s43
+; GFX12-SDAG-NEXT: s_max_num_f32 s9, s14, s42
+; GFX12-SDAG-NEXT: s_max_num_f32 s10, s13, s41
+; GFX12-SDAG-NEXT: s_max_num_f32 s11, s12, s40
+; GFX12-SDAG-NEXT: s_max_num_f32 s12, s19, s47
+; GFX12-SDAG-NEXT: s_max_num_f32 s13, s18, s46
+; GFX12-SDAG-NEXT: s_max_num_f32 s14, s17, s45
+; GFX12-SDAG-NEXT: s_max_num_f32 s15, s16, s44
+; GFX12-SDAG-NEXT: s_max_num_f32 s16, s20, s48
+; GFX12-SDAG-NEXT: s_max_num_f32 s17, s21, s49
+; GFX12-SDAG-NEXT: s_max_num_f32 s18, s22, s50
+; GFX12-SDAG-NEXT: s_max_num_f32 s19, s23, s51
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s17
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s18 :: v_dual_mov_b32 v3, s19
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v4, s15 :: v_dual_mov_b32 v5, s14
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v6, s13 :: v_dual_mov_b32 v7, s12
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v8, s11 :: v_dual_mov_b32 v9, s10
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v11, s8
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v12, s7 :: v_dual_mov_b32 v13, s6
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v14, s5 :: v_dual_mov_b32 v15, s4
; GFX12-SDAG-NEXT: s_clause 0x3
-; GFX12-SDAG-NEXT: buffer_store_b128 v[12:15], off, s[0:3], null offset:48
-; GFX12-SDAG-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null offset:32
-; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
-; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:48
+; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:32
+; GFX12-SDAG-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null offset:16
+; GFX12-SDAG-NEXT: buffer_store_b128 v[12:15], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: test_fmax_v16f32:
@@ -1832,10 +1792,6 @@ define <3 x float> @test_func_fmax_v3f32(<3 x float> %a, <3 x float> %b) #0 {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
; GFX12-SDAG-NEXT: v_max_num_f32_e32 v2, v2, v5
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -1920,12 +1876,11 @@ define amdgpu_kernel void @test_fmax_f16_v_ieee_on(ptr addrspace(1) %out, half %
; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s3, s3
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: s_max_num_f16 s2, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2039,12 +1994,11 @@ define amdgpu_kernel void @test_fmax_f16_s_ieee_on(ptr addrspace(1) %out, half i
; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s3, s3
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: s_max_num_f16 s2, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2152,12 +2106,11 @@ define amdgpu_kernel void @test_fmax_f32_s_ieee_on(ptr addrspace(1) %out, float
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s2, s2
+; GFX12-SDAG-NEXT: s_max_num_f32 s2, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v1, v0
; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2281,12 +2234,9 @@ define amdgpu_kernel void @test_fmax_v2f16_v_ieee_on(ptr addrspace(1) %out, <2 x
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s3, s3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, s2, s2
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v1, v0
; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2411,14 +2361,13 @@ define amdgpu_kernel void @test_fmax_v2f16_s_ieee_on(ptr addrspace(1) %out, <2 x
; GFX12-SDAG-LABEL: test_fmax_v2f16_s_ieee_on:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_mov_b32 s7, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s6, -1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s3, s3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, s2, s2
-; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v1, v0
-; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s2, s3
+; GFX12-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX12-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[4:7], null
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: test_fmax_v2f16_s_ieee_on:
@@ -2538,15 +2487,12 @@ define amdgpu_kernel void @test_fmax_f64_v_ieee_on(ptr addrspace(1) %out, double
; GFX12-SDAG-LABEL: test_fmax_f64_v_ieee_on:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x1
-; GFX12-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[6:7], s[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
+; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[4:5]
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2651,15 +2597,12 @@ define amdgpu_kernel void @test_fmax_f64_s_ieee_on(ptr addrspace(1) %out, double
; GFX12-SDAG-LABEL: test_fmax_f64_s_ieee_on:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x1
-; GFX12-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[6:7], s[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
+; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[4:5]
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
index da7f46a2a0613..16ab69303e62e 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
@@ -1239,12 +1239,9 @@ define <2 x half> @v_min3_v2f16_minimumnum_minimumnum__v_v_v_0(<2 x half> %a, <2
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX12-NEXT: v_pk_max_num_f16 v1, v2, v2
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> %a, <2 x half> %b)
%min3 = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> %tmp0, <2 x half> %c)
@@ -1411,18 +1408,11 @@ define <3 x half> @v_min3_v3f16_minimumnum_minimumnum__v_v_v_0(<3 x half> %a, <3
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_max_num_f16 v2, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v4, v5, v5
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v4
+; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call <3 x half> @llvm.minimumnum.v3f16(<3 x half> %a, <3 x half> %b)
%min3 = call <3 x half> @llvm.minimumnum.v3f16(<3 x half> %tmp0, <3 x half> %c)
@@ -1621,18 +1611,11 @@ define <4 x half> @v_min3_v4f16_minimumnum_minimumnum__v_v_v_0(<4 x half> %a, <4
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_max_num_f16 v2, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v4, v5, v5
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v4
+; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call <4 x half> @llvm.minimumnum.v4f16(<4 x half> %a, <4 x half> %b)
%min3 = call <4 x half> @llvm.minimumnum.v4f16(<4 x half> %tmp0, <4 x half> %c)
@@ -1718,11 +1701,8 @@ define double @v_min3_f64_minimumnum_minimumnum__v_v_v_0(double %a, double %b, d
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call double @llvm.minimumnum.f64(double %a, double %b)
@@ -3201,11 +3181,7 @@ define float @v_min3_f32_minimumnum_neg_minimumnum__v_v_v_0(float %a, float %b,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
+; GFX12-NEXT: v_maxmin_num_f32 v0, v0, -v1, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%tmp0 = call float @llvm.minimumnum.f32(float %neg.a, float %b)
@@ -3289,13 +3265,9 @@ define float @v_min3_f32_minimumnum_fabs_minimumnum__v_v_v_0(float %a, float %b,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
-; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v2
-; GFX12-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX12-NEXT: v_min_num_f32_e64 v0, -v0, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_min_num_f32_e64 v0, |v0|, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%tmp0 = call float @llvm.minimumnum.f32(float %neg.a, float %b)
@@ -3379,13 +3351,9 @@ define float @v_min3_f32_minimumnum_fneg_fabs_minimumnum__v_v_v_0(float %a, floa
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
-; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v2
-; GFX12-NEXT: v_or_b32_e32 v0, 0x80000000, v0
+; GFX12-NEXT: v_min_num_f32_e64 v0, -v0, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_min_num_f32_e64 v0, -|v0|, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%tmp0 = call float @llvm.minimumnum.f32(float %neg.a, float %b)
diff --git a/llvm/test/CodeGen/AMDGPU/fmin3.ll b/llvm/test/CodeGen/AMDGPU/fmin3.ll
index b19fa69c259d3..c03e81e6b7129 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin3.ll
@@ -1427,18 +1427,17 @@ define amdgpu_kernel void @test_fmin3_olt_0_f64(ptr addrspace(1) %out, ptr addrs
; GFX1170-NEXT: s_waitcnt vmcnt(0)
; GFX1170-NEXT: buffer_load_b64 v[2:3], off, s[16:19], 0 glc dlc
; GFX1170-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-NEXT: s_mov_b32 s12, s6
-; GFX1170-NEXT: s_mov_b32 s13, s7
+; GFX1170-NEXT: s_mov_b32 s4, s6
+; GFX1170-NEXT: s_mov_b32 s5, s7
+; GFX1170-NEXT: s_mov_b32 s6, s10
+; GFX1170-NEXT: s_mov_b32 s7, s11
; GFX1170-NEXT: s_mov_b32 s8, s0
-; GFX1170-NEXT: buffer_load_b64 v[4:5], off, s[12:15], 0 glc dlc
+; GFX1170-NEXT: buffer_load_b64 v[4:5], off, s[4:7], 0 glc dlc
; GFX1170-NEXT: s_waitcnt vmcnt(0)
; GFX1170-NEXT: s_mov_b32 s9, s1
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[4:5], v[4:5]
; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
; GFX1170-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX1170-NEXT: s_endpgm
;
@@ -1460,18 +1459,17 @@ define amdgpu_kernel void @test_fmin3_olt_0_f64(ptr addrspace(1) %out, ptr addrs
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_load_b64 v[2:3], off, s[16:19], null scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: s_mov_b32 s12, s6
-; GFX12-NEXT: s_mov_b32 s13, s7
+; GFX12-NEXT: s_mov_b32 s4, s6
+; GFX12-NEXT: s_mov_b32 s5, s7
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
; GFX12-NEXT: s_mov_b32 s8, s0
-; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[4:7], null scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_mov_b32 s9, s1
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-NEXT: s_endpgm
;
@@ -1503,12 +1501,9 @@ define amdgpu_kernel void @test_fmin3_olt_0_f64(ptr addrspace(1) %out, ptr addrs
; GFX1250-NEXT: buffer_load_b64 v[4:5], off, s[4:7], null scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_mov_b32 s1, s9
-; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX1250-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX1250-NEXT: s_endpgm
%a = load volatile double, ptr addrspace(1) %aptr, align 4
@@ -1673,18 +1668,17 @@ define amdgpu_kernel void @test_fmin3_olt_1_f64(ptr addrspace(1) %out, ptr addrs
; GFX1170-NEXT: s_waitcnt vmcnt(0)
; GFX1170-NEXT: buffer_load_b64 v[2:3], off, s[16:19], 0 glc dlc
; GFX1170-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-NEXT: s_mov_b32 s12, s6
-; GFX1170-NEXT: s_mov_b32 s13, s7
+; GFX1170-NEXT: s_mov_b32 s4, s6
+; GFX1170-NEXT: s_mov_b32 s5, s7
+; GFX1170-NEXT: s_mov_b32 s6, s10
+; GFX1170-NEXT: s_mov_b32 s7, s11
; GFX1170-NEXT: s_mov_b32 s8, s0
-; GFX1170-NEXT: buffer_load_b64 v[4:5], off, s[12:15], 0 glc dlc
+; GFX1170-NEXT: buffer_load_b64 v[4:5], off, s[4:7], 0 glc dlc
; GFX1170-NEXT: s_waitcnt vmcnt(0)
; GFX1170-NEXT: s_mov_b32 s9, s1
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[4:5], v[4:5]
-; GFX1170-NEXT: v_min_num_f64 v[0:1], v[2:3], v[0:1]
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[4:5], v[0:1]
; GFX1170-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX1170-NEXT: s_endpgm
;
@@ -1706,18 +1700,17 @@ define amdgpu_kernel void @test_fmin3_olt_1_f64(ptr addrspace(1) %out, ptr addrs
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_load_b64 v[2:3], off, s[16:19], null scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: s_mov_b32 s12, s6
-; GFX12-NEXT: s_mov_b32 s13, s7
+; GFX12-NEXT: s_mov_b32 s4, s6
+; GFX12-NEXT: s_mov_b32 s5, s7
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
; GFX12-NEXT: s_mov_b32 s8, s0
-; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[4:7], null scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_mov_b32 s9, s1
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[0:1]
; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-NEXT: s_endpgm
;
@@ -1749,12 +1742,9 @@ define amdgpu_kernel void @test_fmin3_olt_1_f64(ptr addrspace(1) %out, ptr addrs
; GFX1250-NEXT: buffer_load_b64 v[4:5], off, s[4:7], null scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_mov_b32 s1, s9
-; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[0:1]
; GFX1250-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX1250-NEXT: s_endpgm
%a = load volatile double, ptr addrspace(1) %aptr, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/fminnum.ll b/llvm/test/CodeGen/AMDGPU/fminnum.ll
index da95199b070ee..1e308160adb0a 100644
--- a/llvm/test/CodeGen/AMDGPU/fminnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminnum.ll
@@ -62,12 +62,11 @@ define amdgpu_kernel void @test_fmin_f32_ieee_mode_on(ptr addrspace(1) %out, flo
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s2, s2
+; GFX12-SDAG-NEXT: s_min_num_f32 s2, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v1, v0
; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -230,12 +229,10 @@ define amdgpu_kernel void @test_fmin_v2f32(ptr addrspace(1) %out, <2 x float> %a
; GFX12-SDAG-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s6, -1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s1, s1
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v3, s0, s0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v1, v1, v0 :: v_dual_min_num_f32 v0, v3, v2
+; GFX12-SDAG-NEXT: s_min_num_f32 s0, s0, s2
+; GFX12-SDAG-NEXT: s_min_num_f32 s1, s1, s3
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -363,20 +360,16 @@ define amdgpu_kernel void @test_fmin_v4f32(ptr addrspace(1) %out, <4 x float> %a
; GFX12-SDAG-NEXT: s_clause 0x1
; GFX12-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_min_num_f32 s2, s8, s12
+; GFX12-SDAG-NEXT: s_min_num_f32 s3, s9, s13
+; GFX12-SDAG-NEXT: s_min_num_f32 s4, s10, s14
+; GFX12-SDAG-NEXT: s_min_num_f32 s5, s11, s15
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s15, s15
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s12, s12
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s8, s8
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v3, v1, v0 :: v_dual_min_num_f32 v2, v4, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v1, v6, v5 :: v_dual_min_num_f32 v0, v8, v7
; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -564,33 +557,24 @@ define amdgpu_kernel void @test_fmin_v8f32(ptr addrspace(1) %out, <8 x float> %a
; GFX12-SDAG-NEXT: s_clause 0x1
; GFX12-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x44
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_min_num_f32 s4, s9, s17
+; GFX12-SDAG-NEXT: s_min_num_f32 s5, s8, s16
+; GFX12-SDAG-NEXT: s_min_num_f32 s6, s12, s20
+; GFX12-SDAG-NEXT: s_min_num_f32 s7, s13, s21
+; GFX12-SDAG-NEXT: s_min_num_f32 s8, s14, s22
+; GFX12-SDAG-NEXT: s_min_num_f32 s9, s15, s23
+; GFX12-SDAG-NEXT: s_min_num_f32 s2, s11, s19
+; GFX12-SDAG-NEXT: s_min_num_f32 s3, s10, s18
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, s4
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v7, s2
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s19, s19
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s18, s18
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s17, s17
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s23, s23
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v10, s15, s15
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v11, s22, s22
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s21, s21
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v14, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v15, s20, s20
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v16, s12, s12
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s16, s16
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s8, s8
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v3, v1, v0 :: v_dual_min_num_f32 v2, v4, v2
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v1, v6, v5 :: v_dual_min_num_f32 v6, v12, v11
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v7, v10, v7 :: v_dual_min_num_f32 v0, v9, v8
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v5, v14, v13 :: v_dual_min_num_f32 v4, v16, v15
; GFX12-SDAG-NEXT: s_clause 0x1
-; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
-; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:16
+; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: test_fmin_v8f32:
@@ -907,63 +891,42 @@ define amdgpu_kernel void @test_fmin_v16f32(ptr addrspace(1) %out, <16 x float>
; GFX12-SDAG-LABEL: test_fmin_v16f32:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x2
-; GFX12-SDAG-NEXT: s_load_b512 s[36:51], s[4:5], 0xa4
; GFX12-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x64
+; GFX12-SDAG-NEXT: s_load_b512 s[36:51], s[4:5], 0xa4
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s39, s39
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s38, s38
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s37, s37
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s43, s43
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s15, s15
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s42, s42
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v10, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v11, s41, s41
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s47, s47
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v14, s19, s19
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v3, v1, v0 :: v_dual_min_num_f32 v2, v4, v2
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v7, v8, v7
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s46, s46
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s18, s18
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v1, v6, v5
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v6, v10, v9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s45, s45
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s17, s17
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v5, v12, v11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v18, s40, s40
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v19, s12, s12
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v10, v4, v0
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v9, v9, v8
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s51, s51
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s23, s23
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s50, s50
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v20, s49, s49
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v21, s21, s21
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v22, s48, s48
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v23, s20, s20
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v11, v14, v13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s22, s22
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s44, s44
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v24, s16, s16
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v16, s36, s36
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v17, s8, s8
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v15, v8, v4
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v14, v13, v12
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v13, v21, v20 :: v_dual_min_num_f32 v12, v23, v22
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v8, v24, v0
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v4, v19, v18
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v17, v16
+; GFX12-SDAG-NEXT: s_min_num_f32 s4, s11, s39
+; GFX12-SDAG-NEXT: s_min_num_f32 s5, s10, s38
+; GFX12-SDAG-NEXT: s_min_num_f32 s6, s9, s37
+; GFX12-SDAG-NEXT: s_min_num_f32 s7, s8, s36
+; GFX12-SDAG-NEXT: s_min_num_f32 s8, s15, s43
+; GFX12-SDAG-NEXT: s_min_num_f32 s9, s14, s42
+; GFX12-SDAG-NEXT: s_min_num_f32 s10, s13, s41
+; GFX12-SDAG-NEXT: s_min_num_f32 s11, s12, s40
+; GFX12-SDAG-NEXT: s_min_num_f32 s12, s19, s47
+; GFX12-SDAG-NEXT: s_min_num_f32 s13, s18, s46
+; GFX12-SDAG-NEXT: s_min_num_f32 s14, s17, s45
+; GFX12-SDAG-NEXT: s_min_num_f32 s15, s16, s44
+; GFX12-SDAG-NEXT: s_min_num_f32 s16, s20, s48
+; GFX12-SDAG-NEXT: s_min_num_f32 s17, s21, s49
+; GFX12-SDAG-NEXT: s_min_num_f32 s18, s22, s50
+; GFX12-SDAG-NEXT: s_min_num_f32 s19, s23, s51
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s17
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s18 :: v_dual_mov_b32 v3, s19
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v4, s15 :: v_dual_mov_b32 v5, s14
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v6, s13 :: v_dual_mov_b32 v7, s12
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v8, s11 :: v_dual_mov_b32 v9, s10
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v11, s8
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v12, s7 :: v_dual_mov_b32 v13, s6
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v14, s5 :: v_dual_mov_b32 v15, s4
; GFX12-SDAG-NEXT: s_clause 0x3
-; GFX12-SDAG-NEXT: buffer_store_b128 v[12:15], off, s[0:3], null offset:48
-; GFX12-SDAG-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null offset:32
-; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
-; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:48
+; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:32
+; GFX12-SDAG-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null offset:16
+; GFX12-SDAG-NEXT: buffer_store_b128 v[12:15], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: test_fmin_v16f32:
@@ -1745,10 +1708,6 @@ define <3 x float> @test_func_fmin_v3f32(<3 x float> %a, <3 x float> %b) nounwin
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
; GFX12-SDAG-NEXT: v_min_num_f32_e32 v2, v2, v5
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -1833,12 +1792,11 @@ define amdgpu_kernel void @test_fmin_f16_v_ieee_on(ptr addrspace(1) %out, half %
; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s3, s3
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: s_min_num_f16 s2, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.h, v0.l
; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -1952,12 +1910,11 @@ define amdgpu_kernel void @test_fmin_f16_s_ieee_on(ptr addrspace(1) %out, half i
; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s3, s3
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: s_min_num_f16 s2, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.h, v0.l
; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2065,12 +2022,11 @@ define amdgpu_kernel void @test_fmin_f32_s_ieee_on(ptr addrspace(1) %out, float
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s2, s2
+; GFX12-SDAG-NEXT: s_min_num_f32 s2, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v1, v0
; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2194,12 +2150,9 @@ define amdgpu_kernel void @test_fmin_v2f16_v_ieee_on(ptr addrspace(1) %out, <2 x
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s3, s3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, s2, s2
+; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v1, v0
; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2324,14 +2277,13 @@ define amdgpu_kernel void @test_fmin_v2f16_s_ieee_on(ptr addrspace(1) %out, <2 x
; GFX12-SDAG-LABEL: test_fmin_v2f16_s_ieee_on:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_mov_b32 s7, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s6, -1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s3, s3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, s2, s2
-; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v1, v0
-; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, s2, s3
+; GFX12-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX12-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[4:7], null
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: test_fmin_v2f16_s_ieee_on:
@@ -2451,15 +2403,12 @@ define amdgpu_kernel void @test_fmin_f64_v_ieee_on(ptr addrspace(1) %out, double
; GFX12-SDAG-LABEL: test_fmin_f64_v_ieee_on:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x1
-; GFX12-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[6:7], s[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
+; GFX12-SDAG-NEXT: v_min_num_f64_e64 v[0:1], s[2:3], s[4:5]
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2564,15 +2513,12 @@ define amdgpu_kernel void @test_fmin_f64_s_ieee_on(ptr addrspace(1) %out, double
; GFX12-SDAG-LABEL: test_fmin_f64_s_ieee_on:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x1
-; GFX12-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[6:7], s[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
+; GFX12-SDAG-NEXT: v_min_num_f64_e64 v[0:1], s[2:3], s[4:5]
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
index 2b5feeb686731..816a5a63daa90 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
@@ -3015,15 +3015,13 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB18_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3188,15 +3186,13 @@ define double @global_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:2040
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB19_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:2040 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3362,15 +3358,13 @@ define double @global_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:-2048
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3535,21 +3529,18 @@ define void @global_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3698,21 +3689,18 @@ define void @global_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:2040
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off offset:2040
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB22_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off offset:2040 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:2040 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3864,21 +3852,18 @@ define void @global_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:-2048
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off offset:-2048
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB23_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4031,15 +4016,13 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr add
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB24_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4279,15 +4262,13 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB25_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4456,9 +4437,8 @@ define half @global_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
@@ -4472,12 +4452,11 @@ define half @global_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -4502,9 +4481,8 @@ define half @global_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
@@ -4518,12 +4496,11 @@ define half @global_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -4892,35 +4869,31 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v5, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -4931,7 +4904,7 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -4944,15 +4917,13 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4960,12 +4931,11 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -5348,35 +5318,31 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v5, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -5387,7 +5353,7 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grained_memory:
@@ -5400,15 +5366,13 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5416,12 +5380,11 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -5806,9 +5769,8 @@ define void @global_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
@@ -5821,12 +5783,10 @@ define void @global_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v3.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -5851,9 +5811,8 @@ define void @global_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
@@ -5866,12 +5825,10 @@ define void @global_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6232,38 +6189,33 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v6, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6280,37 +6232,33 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6677,38 +6625,33 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v6, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6725,37 +6668,33 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7124,17 +7063,15 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7159,17 +7096,15 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7464,16 +7399,13 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7497,24 +7429,21 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v2, v2
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off offset:2046
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v3, v3
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7793,36 +7722,32 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v5, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -7833,7 +7758,7 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -7846,15 +7771,13 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7862,12 +7785,11 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -8254,39 +8176,34 @@ define void @global_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v6, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8303,38 +8220,34 @@ define void @global_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -12660,15 +12573,13 @@ define <2 x half> @global_agent_atomic_fmax_ret_v2f16__amdgpu_no_fine_grained_me
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -12942,15 +12853,13 @@ define <2 x half> @global_agent_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB47_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -13226,15 +13135,13 @@ define <2 x half> @global_agent_atomic_fmax_ret_v2f16__offset12b_neg__amdgpu_no_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB48_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -13517,21 +13424,18 @@ define void @global_agent_atomic_fmax_noret_v2f16__amdgpu_no_fine_grained_memory
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB49_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -13786,21 +13690,18 @@ define void @global_agent_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fine
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB50_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14058,21 +13959,18 @@ define void @global_agent_atomic_fmax_noret_v2f16__offset12b_neg__amdgpu_no_fine
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off offset:-2048
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB51_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14339,15 +14237,13 @@ define <2 x half> @global_system_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -14626,22 +14522,19 @@ define void @global_system_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fin
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
index 1510e0efeeee2..82cc3046a58ee 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
@@ -3015,15 +3015,13 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB18_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3188,15 +3186,13 @@ define double @global_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:2040
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB19_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:2040 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3362,15 +3358,13 @@ define double @global_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:-2048
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3535,21 +3529,18 @@ define void @global_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3698,21 +3689,18 @@ define void @global_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:2040
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off offset:2040
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB22_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off offset:2040 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:2040 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3864,21 +3852,18 @@ define void @global_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:-2048
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off offset:-2048
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB23_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4031,15 +4016,13 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr add
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB24_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4279,15 +4262,13 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB25_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4456,9 +4437,8 @@ define half @global_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
@@ -4472,12 +4452,11 @@ define half @global_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v2.h, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -4502,9 +4481,8 @@ define half @global_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
@@ -4518,12 +4496,11 @@ define half @global_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -4892,35 +4869,31 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v5, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -4931,7 +4904,7 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -4944,15 +4917,13 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4960,12 +4931,11 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -5348,35 +5318,31 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v5, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -5387,7 +5353,7 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grained_memory:
@@ -5400,15 +5366,13 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5416,12 +5380,11 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -5806,9 +5769,8 @@ define void @global_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
@@ -5821,12 +5783,10 @@ define void @global_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v3.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.l, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -5851,9 +5811,8 @@ define void @global_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
@@ -5866,12 +5825,10 @@ define void @global_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6232,38 +6189,33 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v6, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6280,37 +6232,33 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6677,38 +6625,33 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v6, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6725,37 +6668,33 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7124,17 +7063,15 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v4.l, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7159,17 +7096,15 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v4
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7464,16 +7399,13 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v4.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v2.h, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7497,24 +7429,21 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v2, v2
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off offset:2046
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v3, v3
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7793,36 +7722,32 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v5, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -7833,7 +7758,7 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -7846,15 +7771,13 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7862,12 +7785,11 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -8254,39 +8176,34 @@ define void @global_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v6, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v5, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8303,38 +8220,34 @@ define void @global_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -12660,15 +12573,13 @@ define <2 x half> @global_agent_atomic_fmin_ret_v2f16__amdgpu_no_fine_grained_me
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -12942,15 +12853,13 @@ define <2 x half> @global_agent_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB47_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -13226,15 +13135,13 @@ define <2 x half> @global_agent_atomic_fmin_ret_v2f16__offset12b_neg__amdgpu_no_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB48_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -13517,21 +13424,18 @@ define void @global_agent_atomic_fmin_noret_v2f16__amdgpu_no_fine_grained_memory
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB49_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -13786,21 +13690,18 @@ define void @global_agent_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fine
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB50_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14058,21 +13959,18 @@ define void @global_agent_atomic_fmin_noret_v2f16__offset12b_neg__amdgpu_no_fine
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off offset:-2048
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB51_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14339,15 +14237,13 @@ define <2 x half> @global_system_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -14626,22 +14522,19 @@ define void @global_system_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fin
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
index 369b06bb29697..a83b33ee56f1c 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
@@ -778,30 +778,29 @@ define half @local_atomic_fmax_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, -4, v0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: ds_load_b32 v3, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v2, v0, 0xffff
+; GFX12-TRUE16-NEXT: ds_load_b32 v2, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v0, 0xffff
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 24, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v2
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v3, v3
; GFX12-TRUE16-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, 4.0, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v3.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, v0, v4
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, 4.0, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v2, v3
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v2, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, v0, v2
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v2, v4, v3, v2
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v3, v1, v3, v4
+; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v1, v2, v4
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -809,7 +808,7 @@ define half @local_atomic_fmax_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v0, v3
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v0, v2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: local_atomic_fmax_ret_f16:
@@ -822,30 +821,29 @@ define half @local_atomic_fmax_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, -4, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: ds_load_b32 v3, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v2, v0, 0xffff
+; GFX12-FAKE16-NEXT: ds_load_b32 v2, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v0, 0xffff
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 24, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v2, v2
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v3, v3
; GFX12-FAKE16-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, 4.0, v3
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v0, v4
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, 4.0, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v2, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v0, v2
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v4, v3, v2
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v3, v1, v3, v4
+; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v2, v1, v2, v4
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -853,7 +851,7 @@ define half @local_atomic_fmax_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v0, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v0, v2
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: local_atomic_fmax_ret_f16:
@@ -1183,12 +1181,11 @@ define half @local_atomic_fmax_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v1, v4
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, 4.0, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v3.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v3.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v1, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v2, v3
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -1229,12 +1226,11 @@ define half @local_atomic_fmax_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v1, v4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, 4.0, v3
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v1, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v2, v3
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -1588,12 +1584,11 @@ define void @local_atomic_fmax_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, v0, v2
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, 4.0, v4.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v4, v4.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v4, v4.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v0, v4
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v4, v2, v3, v4
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -1631,12 +1626,11 @@ define void @local_atomic_fmax_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v0, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, 4.0, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v0, v4
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v4, v2, v3, v4
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -1971,12 +1965,10 @@ define void @local_atomic_fmax_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, v1, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, 4.0, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v4, v4.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v1, v4
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v4, v3, v2, v4
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -2016,12 +2008,10 @@ define void @local_atomic_fmax_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v1, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, 4.0, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v1, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v4, v3, v2, v4
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -2360,10 +2350,9 @@ define half @local_atomic_fmax_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, 4.0, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, 4.0, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v1, v1.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, 0xffff0000, v2, v1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -2395,10 +2384,9 @@ define half @local_atomic_fmax_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, 4.0, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, 4.0, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v1, 0xffff0000, v2, v1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -2668,11 +2656,9 @@ define void @local_atomic_fmax_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: .LBB13_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v1.l, v1.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, 4.0, v1.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, 4.0, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v2, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v2, 0xffff0000, v1, v2
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -2702,11 +2688,9 @@ define void @local_atomic_fmax_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: .LBB13_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v1, v1
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, 4.0, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, 4.0, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v1, v2
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -5054,15 +5038,13 @@ define <2 x half> @local_atomic_fmax_ret_v2f16(ptr addrspace(3) %ptr, <2 x half>
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v2, v0, v2, v3
@@ -5318,15 +5300,13 @@ define <2 x half> @local_atomic_fmax_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0 offset:65532
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v2, v0, v2, v3 offset:65532
@@ -5584,14 +5564,11 @@ define void @local_atomic_fmax_noret_v2f16(ptr addrspace(3) %ptr, <2 x half> %va
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB22_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v1
+; GFX12-NEXT: v_pk_max_num_f16 v3, v2, v1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v3, v0, v3, v2
@@ -5834,14 +5811,11 @@ define void @local_atomic_fmax_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0 offset:65532
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB23_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v1
+; GFX12-NEXT: v_pk_max_num_f16 v3, v2, v1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v3, v0, v3, v2 offset:65532
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
index 88e1469580618..aaa7188882977 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
@@ -778,30 +778,29 @@ define half @local_atomic_fmin_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, -4, v0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: ds_load_b32 v3, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v2, v0, 0xffff
+; GFX12-TRUE16-NEXT: ds_load_b32 v2, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v0, 0xffff
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 24, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v2
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v3, v3
; GFX12-TRUE16-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, 4.0, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v3.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, v0, v4
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.l, 4.0, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v2, v3
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v2, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, v0, v2
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v2, v4, v3, v2
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v3, v1, v3, v4
+; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v1, v2, v4
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -809,7 +808,7 @@ define half @local_atomic_fmin_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v0, v3
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v0, v2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: local_atomic_fmin_ret_f16:
@@ -822,30 +821,29 @@ define half @local_atomic_fmin_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, -4, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: ds_load_b32 v3, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v2, v0, 0xffff
+; GFX12-FAKE16-NEXT: ds_load_b32 v2, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v0, 0xffff
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 24, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v2, v2
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v3, v3
; GFX12-FAKE16-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, 4.0, v3
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v0, v4
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, 4.0, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v2, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v0, v2
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v4, v3, v2
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v3, v1, v3, v4
+; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v2, v1, v2, v4
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -853,7 +851,7 @@ define half @local_atomic_fmin_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v0, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v0, v2
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: local_atomic_fmin_ret_f16:
@@ -1183,12 +1181,11 @@ define half @local_atomic_fmin_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v1, v4
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, 4.0, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v3.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v3, v3.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v1, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v2, v3
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -1229,12 +1226,11 @@ define half @local_atomic_fmin_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v1, v4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, 4.0, v3
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v1, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v2, v3
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -1588,12 +1584,11 @@ define void @local_atomic_fmin_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, v0, v2
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v4.l, 4.0, v4.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v4, v4.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v4, v4.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v0, v4
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v4, v2, v3, v4
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -1631,12 +1626,11 @@ define void @local_atomic_fmin_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v0, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v4, 4.0, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v0, v4
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v4, v2, v3, v4
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -1971,12 +1965,10 @@ define void @local_atomic_fmin_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, v1, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v4.l, 4.0, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v4, v4.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v1, v4
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v4, v3, v2, v4
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -2016,12 +2008,10 @@ define void @local_atomic_fmin_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v1, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v4, 4.0, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v1, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v4, v3, v2, v4
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -2360,10 +2350,9 @@ define half @local_atomic_fmin_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v1.l, 4.0, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v1.l, 4.0, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v1, v1.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, 0xffff0000, v2, v1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -2395,10 +2384,9 @@ define half @local_atomic_fmin_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v1, 4.0, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v1, 4.0, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v1, 0xffff0000, v2, v1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -2668,11 +2656,9 @@ define void @local_atomic_fmin_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: .LBB13_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v1.l, v1.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.l, 4.0, v1.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.l, 4.0, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u32_u16_e32 v2, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v2, 0xffff0000, v1, v2
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -2702,11 +2688,9 @@ define void @local_atomic_fmin_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: .LBB13_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v1, v1
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, 4.0, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, 4.0, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v1, v2
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -5054,15 +5038,13 @@ define <2 x half> @local_atomic_fmin_ret_v2f16(ptr addrspace(3) %ptr, <2 x half>
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v2, v3, v1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v2, v0, v2, v3
@@ -5318,15 +5300,13 @@ define <2 x half> @local_atomic_fmin_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0 offset:65532
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v2, v3, v1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v2, v0, v2, v3 offset:65532
@@ -5584,14 +5564,11 @@ define void @local_atomic_fmin_noret_v2f16(ptr addrspace(3) %ptr, <2 x half> %va
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB22_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v1
+; GFX12-NEXT: v_pk_min_num_f16 v3, v2, v1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v3, v0, v3, v2
@@ -5834,14 +5811,11 @@ define void @local_atomic_fmin_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0 offset:65532
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB23_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v1
+; GFX12-NEXT: v_pk_min_num_f16 v3, v2, v1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v3, v0, v3, v2 offset:65532
diff --git a/llvm/test/CodeGen/AMDGPU/maximumnum.ll b/llvm/test/CodeGen/AMDGPU/maximumnum.ll
index 3773ca20c3a68..7a527a126e379 100644
--- a/llvm/test/CodeGen/AMDGPU/maximumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/maximumnum.ll
@@ -93,18 +93,12 @@ define half @v_maximumnum_f16(half %x, half %y) #1 {
; GFX1170-TRUE16-LABEL: v_maximumnum_f16:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_maximumnum_f16:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -115,10 +109,7 @@ define half @v_maximumnum_f16(half %x, half %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_f16:
@@ -128,9 +119,6 @@ define half @v_maximumnum_f16(half %x, half %y) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -138,19 +126,13 @@ define half @v_maximumnum_f16(half %x, half %y) #1 {
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_maximumnum_f16:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f16:
@@ -406,16 +388,12 @@ define half @v_maximumnum_f16_1.0(half %x) #1 {
; GFX1170-TRUE16-LABEL: v_maximumnum_f16_1.0:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, 1.0, v0.l
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_maximumnum_f16_1.0:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, 1.0, v0
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -426,8 +404,6 @@ define half @v_maximumnum_f16_1.0(half %x) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, 1.0, v0.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -438,8 +414,6 @@ define half @v_maximumnum_f16_1.0(half %x) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, 1.0, v0
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -447,8 +421,6 @@ define half @v_maximumnum_f16_1.0(half %x) #1 {
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, 1.0, v0.l
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -456,8 +428,6 @@ define half @v_maximumnum_f16_1.0(half %x) #1 {
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, 1.0, v0
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
%result = call half @llvm.maximumnum.f16(half %x, half 1.0)
@@ -508,8 +478,6 @@ define float @v_maximumnum_f32(float %x, float %y) #1 {
; GFX1170-LABEL: v_maximumnum_f32:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -520,8 +488,6 @@ define float @v_maximumnum_f32(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -529,8 +495,6 @@ define float @v_maximumnum_f32(float %x, float %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f32:
@@ -700,9 +664,6 @@ define double @v_maximumnum_f64(double %x, double %y) #1 {
; GFX1170-LABEL: v_maximumnum_f64:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -713,9 +674,6 @@ define double @v_maximumnum_f64(double %x, double %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -723,9 +681,6 @@ define double @v_maximumnum_f64(double %x, double %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f64:
@@ -894,8 +849,6 @@ define float @v_maximumnum_f32_1.0(float %x) #1 {
; GFX1170-LABEL: v_maximumnum_f32_1.0:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_max_num_f32_e32 v0, 1.0, v0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -906,8 +859,6 @@ define float @v_maximumnum_f32_1.0(float %x) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f32_e32 v0, 1.0, v0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -915,8 +866,6 @@ define float @v_maximumnum_f32_1.0(float %x) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_max_num_f32_e32 v0, 1.0, v0
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
%result = call float @llvm.maximumnum.f32(float %x, float 1.0)
@@ -967,7 +916,7 @@ define float @v_maximumnum_f32_rhs_not_snan(float %x, float %y) #1 {
; GFX1170-LABEL: v_maximumnum_f32_rhs_not_snan:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
+; GFX1170-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -979,7 +928,7 @@ define float @v_maximumnum_f32_rhs_not_snan(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
+; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -988,7 +937,7 @@ define float @v_maximumnum_f32_rhs_not_snan(float %x, float %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
+; GFX1251-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -1041,7 +990,7 @@ define float @v_maximumnum_f32_lhs_not_snan(float %x, float %y) #1 {
; GFX1170-LABEL: v_maximumnum_f32_lhs_not_snan:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -1053,7 +1002,7 @@ define float @v_maximumnum_f32_lhs_not_snan(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -1062,7 +1011,7 @@ define float @v_maximumnum_f32_lhs_not_snan(float %x, float %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v0
; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -1186,8 +1135,6 @@ define double @v_maximumnum_f64_1.0(double %x) #1 {
; GFX1170-LABEL: v_maximumnum_f64_1.0:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], 1.0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -1198,8 +1145,6 @@ define double @v_maximumnum_f64_1.0(double %x) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], 1.0, v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -1207,8 +1152,6 @@ define double @v_maximumnum_f64_1.0(double %x) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], 1.0, v[0:1]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
%result = call double @llvm.maximumnum.f64(double %x, double 1.0)
@@ -1278,19 +1221,13 @@ define half @v_maximumnum_f16_s_v(half inreg %x, half %y) #1 {
; GFX1170-TRUE16-LABEL: v_maximumnum_f16_s_v:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, s0, v0.l
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_maximumnum_f16_s_v:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v1, v0
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, s0, v0
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: v_maximumnum_f16_s_v:
@@ -1300,10 +1237,7 @@ define half @v_maximumnum_f16_s_v(half inreg %x, half %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, s0, v0.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_f16_s_v:
@@ -1313,30 +1247,21 @@ define half @v_maximumnum_f16_s_v(half inreg %x, half %y) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v1, v0
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, s0, v0
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-TRUE16-LABEL: v_maximumnum_f16_s_v:
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
+; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, s0, v0.l
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_maximumnum_f16_s_v:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v1, v0
+; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, s0, v0
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f16_s_v:
; GFX7-GISEL: ; %bb.0:
@@ -1515,19 +1440,13 @@ define half @v_maximumnum_f16_v_s(half %x, half inreg %y) #1 {
; GFX1170-TRUE16-LABEL: v_maximumnum_f16_v_s:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, s0, v0.l
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_maximumnum_f16_v_s:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, s0, v0
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: v_maximumnum_f16_v_s:
@@ -1537,10 +1456,7 @@ define half @v_maximumnum_f16_v_s(half %x, half inreg %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, s0, v0.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_f16_v_s:
@@ -1550,30 +1466,21 @@ define half @v_maximumnum_f16_v_s(half %x, half inreg %y) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, s0, v0
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-TRUE16-LABEL: v_maximumnum_f16_v_s:
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, s0, v0.l
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_maximumnum_f16_v_s:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, s0, v0
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f16_v_s:
; GFX7-GISEL: ; %bb.0:
@@ -1749,69 +1656,35 @@ define half @v_maximumnum_f16_s_s(half inreg %x, half inreg %y) #1 {
; GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-LABEL: v_maximumnum_f16_s_s:
-; GFX1170-TRUE16: ; %bb.0:
-; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, s1, s1
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
-; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-LABEL: v_maximumnum_f16_s_s:
-; GFX1170-FAKE16: ; %bb.0:
-; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, s1, s1
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v1, v0
-; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-LABEL: v_maximumnum_f16_s_s:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, s1, s1
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-LABEL: v_maximumnum_f16_s_s:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, s1, s1
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v1, v0
-; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f16_s_s:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: s_max_f16 s0, s0, s1
+; GFX1170-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1170-NEXT: v_mov_b32_e32 v0, s0
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1251-TRUE16-LABEL: v_maximumnum_f16_s_s:
-; GFX1251-TRUE16: ; %bb.0:
-; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.l, s1, s1
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
-; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+; GFX12-LABEL: v_maximumnum_f16_s_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_max_num_f16 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1251-FAKE16-LABEL: v_maximumnum_f16_s_s:
-; GFX1251-FAKE16: ; %bb.0:
-; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v0, s1, s1
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v1, v0
-; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+; GFX1251-LABEL: v_maximumnum_f16_s_s:
+; GFX1251: ; %bb.0:
+; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1251-NEXT: s_wait_kmcnt 0x0
+; GFX1251-NEXT: s_max_num_f16 s0, s0, s1
+; GFX1251-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1251-NEXT: v_mov_b32_e32 v0, s0
+; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f16_s_s:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1997,10 +1870,7 @@ define float @v_maximumnum_f32_s_v(float inreg %x, float %y) #1 {
; GFX1170-LABEL: v_maximumnum_f32_s_v:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v1, v0
+; GFX1170-NEXT: v_max_num_f32_e32 v0, s0, v0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_f32_s_v:
@@ -2010,20 +1880,14 @@ define float @v_maximumnum_f32_s_v(float inreg %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f32_e32 v0, v1, v0
+; GFX12-NEXT: v_max_num_f32_e32 v0, s0, v0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_f32_s_v:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1251-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v1, v0
+; GFX1251-NEXT: v_max_num_f32_e32 v0, s0, v0
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f32_s_v:
; GFX7-GISEL: ; %bb.0:
@@ -2154,10 +2018,7 @@ define float @v_maximumnum_f32_v_s(float %x, float inreg %y) #1 {
; GFX1170-LABEL: v_maximumnum_f32_v_s:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: v_max_num_f32_e32 v0, s0, v0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_f32_v_s:
@@ -2167,20 +2028,14 @@ define float @v_maximumnum_f32_v_s(float %x, float inreg %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_max_num_f32_e32 v0, s0, v0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_f32_v_s:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1251-NEXT: v_max_num_f32_e32 v0, s0, v0
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f32_v_s:
; GFX7-GISEL: ; %bb.0:
@@ -2311,10 +2166,9 @@ define float @v_maximumnum_f32_s_s(float inreg %x, float inreg %y) #1 {
; GFX1170-LABEL: v_maximumnum_f32_s_s:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e64 v0, s1, s1
-; GFX1170-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v1, v0
+; GFX1170-NEXT: s_max_f32 s0, s0, s1
+; GFX1170-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1170-NEXT: v_mov_b32_e32 v0, s0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_f32_s_s:
@@ -2324,20 +2178,19 @@ define float @v_maximumnum_f32_s_s(float inreg %x, float inreg %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v0, s1, s1
-; GFX12-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f32_e32 v0, v1, v0
+; GFX12-NEXT: s_max_num_f32 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_f32_s_s:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e64 v0, s1, s1
-; GFX1251-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v1, v0
+; GFX1251-NEXT: s_max_num_f32 s0, s0, s1
+; GFX1251-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1251-NEXT: v_mov_b32_e32 v0, s0
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f32_s_s:
; GFX7-GISEL: ; %bb.0:
@@ -2477,10 +2330,7 @@ define double @v_maximumnum_f64_s_v(double inreg %x, double %y) #1 {
; GFX1170-LABEL: v_maximumnum_f64_s_v:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], s[0:1], s[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[2:3], v[0:1]
+; GFX1170-NEXT: v_max_num_f64 v[0:1], s[0:1], v[0:1]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_f64_s_v:
@@ -2490,20 +2340,14 @@ define double @v_maximumnum_f64_s_v(double inreg %x, double %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], s[0:1], v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_f64_s_v:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], s[0:1], v[0:1]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f64_s_v:
; GFX7-GISEL: ; %bb.0:
@@ -2590,10 +2434,7 @@ define double @v_maximumnum_f64_v_s(double %x, double inreg %y) #1 {
; GFX1170-LABEL: v_maximumnum_f64_v_s:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], s[0:1], s[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], s[0:1]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_f64_v_s:
@@ -2603,20 +2444,14 @@ define double @v_maximumnum_f64_v_s(double %x, double inreg %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], s[0:1], v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_f64_v_s:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], s[0:1], v[0:1]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f64_v_s:
; GFX7-GISEL: ; %bb.0:
@@ -2703,10 +2538,7 @@ define double @v_maximumnum_f64_s_s(double inreg %x, double inreg %y) #1 {
; GFX1170-LABEL: v_maximumnum_f64_s_s:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[0:1], s[2:3], s[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], s[0:1], s[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[2:3], v[0:1]
+; GFX1170-NEXT: v_max_num_f64 v[0:1], s[0:1], s[2:3]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_f64_s_s:
@@ -2716,20 +2548,14 @@ define double @v_maximumnum_f64_s_s(double inreg %x, double inreg %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
-; GFX12-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e64 v[0:1], s[0:1], s[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_f64_s_s:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
-; GFX1251-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX1251-NEXT: v_max_num_f64_e64 v[0:1], s[0:1], s[2:3]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f64_s_s:
; GFX7-GISEL: ; %bb.0:
@@ -2852,10 +2678,7 @@ define float @v_maximumnum_f32_fabs_rhs(float %x, float %y) #1 {
; GFX1170-LABEL: v_maximumnum_f32_fabs_rhs:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: v_max_num_f32_e64 v0, v0, |v1|
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_f32_fabs_rhs:
@@ -2865,20 +2688,14 @@ define float @v_maximumnum_f32_fabs_rhs(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_max_num_f32_e64 v0, v0, |v1|
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_f32_fabs_rhs:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1251-NEXT: v_max_num_f32_e64 v0, v0, |v1|
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f32_fabs_rhs:
; GFX7-GISEL: ; %bb.0:
@@ -2995,10 +2812,7 @@ define float @v_maximumnum_f32_fneg_fabs_rhs(float %x, float %y) #1 {
; GFX1170-LABEL: v_maximumnum_f32_fneg_fabs_rhs:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: v_max_num_f32_e64 v0, v0, -|v1|
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_f32_fneg_fabs_rhs:
@@ -3008,20 +2822,14 @@ define float @v_maximumnum_f32_fneg_fabs_rhs(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_max_num_f32_e64 v0, v0, -|v1|
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_f32_fneg_fabs_rhs:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1251-NEXT: v_max_num_f32_e64 v0, v0, -|v1|
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f32_fneg_fabs_rhs:
; GFX7-GISEL: ; %bb.0:
@@ -3139,10 +2947,7 @@ define float @v_maximumnum_f32_fabs(float %x, float %y) #1 {
; GFX1170-LABEL: v_maximumnum_f32_fabs:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1170-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: v_max_num_f32_e64 v0, |v0|, |v1|
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_f32_fabs:
@@ -3152,20 +2957,14 @@ define float @v_maximumnum_f32_fabs(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX12-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_max_num_f32_e64 v0, |v0|, |v1|
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_f32_fabs:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1251-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1251-NEXT: v_max_num_f32_e64 v0, |v0|, |v1|
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f32_fabs:
; GFX7-GISEL: ; %bb.0:
@@ -3283,10 +3082,7 @@ define float @v_maximumnum_f32_fneg(float %x, float %y) #1 {
; GFX1170-LABEL: v_maximumnum_f32_fneg:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX1170-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: v_max_num_f32_e64 v0, -v0, -v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_f32_fneg:
@@ -3296,19 +3092,14 @@ define float @v_maximumnum_f32_fneg(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, -v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_f32_fneg:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v1, -v1, -v1 :: v_dual_max_num_f32 v0, -v0, -v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1251-NEXT: v_max_num_f32_e64 v0, -v0, -v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f32_fneg:
; GFX7-GISEL: ; %bb.0:
@@ -3435,19 +3226,13 @@ define half @v_maximumnum_f16_fabs_rhs(half %x, half %y) #1 {
; GFX1170-TRUE16-LABEL: v_maximumnum_f16_fabs_rhs:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, v0.l, |v1.l|
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_maximumnum_f16_fabs_rhs:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, v0, |v1|
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: v_maximumnum_f16_fabs_rhs:
@@ -3457,10 +3242,7 @@ define half @v_maximumnum_f16_fabs_rhs(half %x, half %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, v0.l, |v1.l|
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_f16_fabs_rhs:
@@ -3470,30 +3252,21 @@ define half @v_maximumnum_f16_fabs_rhs(half %x, half %y) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, v0, |v1|
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-TRUE16-LABEL: v_maximumnum_f16_fabs_rhs:
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.l, v0.l, |v1.l|
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_maximumnum_f16_fabs_rhs:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v0, v0, |v1|
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f16_fabs_rhs:
; GFX7-GISEL: ; %bb.0:
@@ -3658,19 +3431,13 @@ define half @v_maximumnum_f16_fneg_fabs_rhs(half %x, half %y) #1 {
; GFX1170-TRUE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, v0.l, -|v1.l|
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, v0, -|v1|
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
@@ -3680,10 +3447,7 @@ define half @v_maximumnum_f16_fneg_fabs_rhs(half %x, half %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, v0.l, -|v1.l|
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
@@ -3693,30 +3457,21 @@ define half @v_maximumnum_f16_fneg_fabs_rhs(half %x, half %y) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, v0, -|v1|
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-TRUE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.l, v0.l, -|v1.l|
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v0, v0, -|v1|
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
; GFX7-GISEL: ; %bb.0:
@@ -3882,19 +3637,13 @@ define half @v_maximumnum_f16_fabs(half %x, half %y) #1 {
; GFX1170-TRUE16-LABEL: v_maximumnum_f16_fabs:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v1.l|
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_maximumnum_f16_fabs:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, |v0|, |v1|
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: v_maximumnum_f16_fabs:
@@ -3904,10 +3653,7 @@ define half @v_maximumnum_f16_fabs(half %x, half %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v1.l|
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_f16_fabs:
@@ -3917,30 +3663,21 @@ define half @v_maximumnum_f16_fabs(half %x, half %y) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, |v0|, |v1|
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-TRUE16-LABEL: v_maximumnum_f16_fabs:
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v1.l|
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_maximumnum_f16_fabs:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v0, |v0|, |v1|
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f16_fabs:
; GFX7-GISEL: ; %bb.0:
@@ -4106,19 +3843,13 @@ define half @v_maximumnum_f16_fneg(half %x, half %y) #1 {
; GFX1170-TRUE16-LABEL: v_maximumnum_f16_fneg:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v1.l
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_maximumnum_f16_fneg:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, -v0, -v1
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: v_maximumnum_f16_fneg:
@@ -4128,10 +3859,7 @@ define half @v_maximumnum_f16_fneg(half %x, half %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_f16_fneg:
@@ -4141,30 +3869,21 @@ define half @v_maximumnum_f16_fneg(half %x, half %y) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, -v0, -v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-TRUE16-LABEL: v_maximumnum_f16_fneg:
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v1.l
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_maximumnum_f16_fneg:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v0, -v0, -v1
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f16_fneg:
; GFX7-GISEL: ; %bb.0:
@@ -4320,10 +4039,7 @@ define double @v_maximumnum_f64_fneg(double %x, double %y) #1 {
; GFX1170-LABEL: v_maximumnum_f64_fneg:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], -v[2:3], -v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], -v[0:1], -v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: v_max_num_f64 v[0:1], -v[0:1], -v[2:3]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_f64_fneg:
@@ -4333,20 +4049,14 @@ define double @v_maximumnum_f64_fneg(double %x, double %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e64 v[2:3], -v[2:3], -v[2:3]
-; GFX12-NEXT: v_max_num_f64_e64 v[0:1], -v[0:1], -v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e64 v[0:1], -v[0:1], -v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_f64_fneg:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e64 v[2:3], -v[2:3], -v[2:3]
-; GFX1251-NEXT: v_max_num_f64_e64 v[0:1], -v[0:1], -v[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX1251-NEXT: v_max_num_f64_e64 v[0:1], -v[0:1], -v[2:3]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f64_fneg:
; GFX7-GISEL: ; %bb.0:
@@ -4486,9 +4196,6 @@ define <2 x half> @v_maximumnum_v2f16(<2 x half> %x, <2 x half> %y) #1 {
; GFX1170-LABEL: v_maximumnum_v2f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -4499,9 +4206,6 @@ define <2 x half> @v_maximumnum_v2f16(<2 x half> %x, <2 x half> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -4509,9 +4213,6 @@ define <2 x half> @v_maximumnum_v2f16(<2 x half> %x, <2 x half> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_v2f16:
@@ -4771,11 +4472,6 @@ define <3 x half> @v_maximumnum_v3f16(<3 x half> %x, <3 x half> %y) #1 {
; GFX1170-LABEL: v_maximumnum_v3f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -4787,11 +4483,6 @@ define <3 x half> @v_maximumnum_v3f16(<3 x half> %x, <3 x half> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4800,11 +4491,6 @@ define <3 x half> @v_maximumnum_v3f16(<3 x half> %x, <3 x half> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -5139,11 +4825,6 @@ define <4 x half> @v_maximumnum_v4f16(<4 x half> %x, <4 x half> %y) #1 {
; GFX1170-LABEL: v_maximumnum_v4f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -5155,11 +4836,6 @@ define <4 x half> @v_maximumnum_v4f16(<4 x half> %x, <4 x half> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -5168,11 +4844,6 @@ define <4 x half> @v_maximumnum_v4f16(<4 x half> %x, <4 x half> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -5564,14 +5235,7 @@ define <6 x half> @v_maximumnum_v6f16(<6 x half> %x, <6 x half> %y) #1 {
; GFX1170-LABEL: v_maximumnum_v6f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v3
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v4
; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v5
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -5583,14 +5247,7 @@ define <6 x half> @v_maximumnum_v6f16(<6 x half> %x, <6 x half> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v4
; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -5599,14 +5256,7 @@ define <6 x half> @v_maximumnum_v6f16(<6 x half> %x, <6 x half> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v3
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v4
; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v5
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -5940,18 +5590,9 @@ define <8 x half> @v_maximumnum_v8f16(<8 x half> %x, <8 x half> %y) #1 {
; GFX1170-LABEL: v_maximumnum_v8f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v4
; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v5
; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v6
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v7
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -5962,18 +5603,9 @@ define <8 x half> @v_maximumnum_v8f16(<8 x half> %x, <8 x half> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v4
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v5
; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v6
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v7
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -5981,18 +5613,9 @@ define <8 x half> @v_maximumnum_v8f16(<8 x half> %x, <8 x half> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1251-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v4
; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v5
; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v6
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v7
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_v8f16:
@@ -6488,30 +6111,14 @@ define <16 x half> @v_maximumnum_v16f16(<16 x half> %x, <16 x half> %y) #1 {
; GFX1170-LABEL: v_maximumnum_v16f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v8
-; GFX1170-NEXT: v_pk_max_num_f16 v8, v11, v11
; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v9
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v10
-; GFX1170-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX1170-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX1170-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v8
-; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v9
-; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v10
-; GFX1170-NEXT: v_pk_max_num_f16 v6, v6, v11
-; GFX1170-NEXT: v_pk_max_num_f16 v7, v7, v12
+; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v11
+; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v12
+; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v13
+; GFX1170-NEXT: v_pk_max_num_f16 v6, v6, v14
+; GFX1170-NEXT: v_pk_max_num_f16 v7, v7, v15
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_v16f16:
@@ -6521,60 +6128,28 @@ define <16 x half> @v_maximumnum_v16f16(<16 x half> %x, <16 x half> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v8
-; GFX12-NEXT: v_pk_max_num_f16 v8, v11, v11
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v9
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v10
-; GFX12-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX12-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX12-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v8
-; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v9
-; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v10
-; GFX12-NEXT: v_pk_max_num_f16 v6, v6, v11
-; GFX12-NEXT: v_pk_max_num_f16 v7, v7, v12
+; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v11
+; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v12
+; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v13
+; GFX12-NEXT: v_pk_max_num_f16 v6, v6, v14
+; GFX12-NEXT: v_pk_max_num_f16 v7, v7, v15
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_v16f16:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v8
-; GFX1251-NEXT: v_pk_max_num_f16 v8, v11, v11
; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v9
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v10
-; GFX1251-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX1251-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1251-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX1251-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1251-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX1251-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1251-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX1251-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v8
-; GFX1251-NEXT: v_pk_max_num_f16 v4, v4, v9
-; GFX1251-NEXT: v_pk_max_num_f16 v5, v5, v10
-; GFX1251-NEXT: v_pk_max_num_f16 v6, v6, v11
-; GFX1251-NEXT: v_pk_max_num_f16 v7, v7, v12
+; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v11
+; GFX1251-NEXT: v_pk_max_num_f16 v4, v4, v12
+; GFX1251-NEXT: v_pk_max_num_f16 v5, v5, v13
+; GFX1251-NEXT: v_pk_max_num_f16 v6, v6, v14
+; GFX1251-NEXT: v_pk_max_num_f16 v7, v7, v15
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_v16f16:
; GFX7-GISEL: ; %bb.0:
@@ -7522,37 +7097,6 @@ define <32 x half> @v_maximumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX1170-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX1170-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX1170-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX1170-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX1170-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX1170-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX1170-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX1170-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX1170-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX1170-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX1170-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX1170-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX1170-NEXT: v_pk_max_num_f16 v15, v15, v15
; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v16
; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v17
; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v18
@@ -7569,9 +7113,7 @@ define <32 x half> @v_maximumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX1170-NEXT: v_pk_max_num_f16 v13, v13, v29
; GFX1170-NEXT: v_pk_max_num_f16 v14, v14, v30
; GFX1170-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_pk_max_num_f16 v15, v15, v16
+; GFX1170-NEXT: v_pk_max_num_f16 v15, v15, v31
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_v32f16:
@@ -7582,37 +7124,6 @@ define <32 x half> @v_maximumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX12-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX12-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX12-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX12-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX12-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX12-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX12-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX12-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX12-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX12-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX12-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX12-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX12-NEXT: v_pk_max_num_f16 v15, v15, v15
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v16
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v17
; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v18
@@ -7629,9 +7140,7 @@ define <32 x half> @v_maximumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX12-NEXT: v_pk_max_num_f16 v13, v13, v29
; GFX12-NEXT: v_pk_max_num_f16 v14, v14, v30
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v15, v15, v16
+; GFX12-NEXT: v_pk_max_num_f16 v15, v15, v31
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_v32f16:
@@ -7639,37 +7148,6 @@ define <32 x half> @v_maximumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
; GFX1251-NEXT: scratch_load_b32 v31, off, s32
-; GFX1251-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1251-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1251-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX1251-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1251-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX1251-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1251-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX1251-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1251-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX1251-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1251-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX1251-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1251-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX1251-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1251-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX1251-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1251-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX1251-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX1251-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX1251-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX1251-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX1251-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX1251-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX1251-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX1251-NEXT: v_pk_max_num_f16 v15, v15, v15
; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v16
; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v17
; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v18
@@ -7686,9 +7164,7 @@ define <32 x half> @v_maximumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX1251-NEXT: v_pk_max_num_f16 v13, v13, v29
; GFX1251-NEXT: v_pk_max_num_f16 v14, v14, v30
; GFX1251-NEXT: s_wait_loadcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_pk_max_num_f16 v15, v15, v16
+; GFX1251-NEXT: v_pk_max_num_f16 v15, v15, v31
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_v32f16:
; GFX7-GISEL: ; %bb.0:
@@ -8455,9 +7931,6 @@ define <2 x float> @v_maximumnum_v2f32(<2 x float> %x, <2 x float> %y) #1 {
; GFX1170-LABEL: v_maximumnum_v2f32:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v2 :: v_dual_max_num_f32 v1, v1, v3
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -8468,9 +7941,6 @@ define <2 x float> @v_maximumnum_v2f32(<2 x float> %x, <2 x float> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v2 :: v_dual_max_num_f32 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -8478,9 +7948,6 @@ define <2 x float> @v_maximumnum_v2f32(<2 x float> %x, <2 x float> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1251-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_dual_max_num_f32 v0, v0, v2 :: v_dual_max_num_f32 v1, v1, v3
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_v2f32:
@@ -8696,10 +8163,6 @@ define <3 x float> @v_maximumnum_v3f32(<3 x float> %x, <3 x float> %y) #1 {
; GFX1170-LABEL: v_maximumnum_v3f32:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
; GFX1170-NEXT: v_max_num_f32_e32 v2, v2, v5
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -8711,10 +8174,6 @@ define <3 x float> @v_maximumnum_v3f32(<3 x float> %x, <3 x float> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
; GFX12-NEXT: v_max_num_f32_e32 v2, v2, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -8723,10 +8182,6 @@ define <3 x float> @v_maximumnum_v3f32(<3 x float> %x, <3 x float> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1251-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1251-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1251-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
; GFX1251-NEXT: v_max_num_f32_e32 v2, v2, v5
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -8984,11 +8439,6 @@ define <4 x float> @v_maximumnum_v4f32(<4 x float> %x, <4 x float> %y) #1 {
; GFX1170-LABEL: v_maximumnum_v4f32:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX1170-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v4 :: v_dual_max_num_f32 v1, v1, v5
; GFX1170-NEXT: v_dual_max_num_f32 v2, v2, v6 :: v_dual_max_num_f32 v3, v3, v7
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -9000,11 +8450,6 @@ define <4 x float> @v_maximumnum_v4f32(<4 x float> %x, <4 x float> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX12-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v4 :: v_dual_max_num_f32 v1, v1, v5
; GFX12-NEXT: v_dual_max_num_f32 v2, v2, v6 :: v_dual_max_num_f32 v3, v3, v7
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -9013,11 +8458,6 @@ define <4 x float> @v_maximumnum_v4f32(<4 x float> %x, <4 x float> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1251-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1251-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX1251-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1251-NEXT: v_dual_max_num_f32 v0, v0, v4 :: v_dual_max_num_f32 v1, v1, v5
; GFX1251-NEXT: v_dual_max_num_f32 v2, v2, v6 :: v_dual_max_num_f32 v3, v3, v7
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -9282,11 +8722,6 @@ define <2 x double> @v_maximumnum_v2f64(<2 x double> %x, <2 x double> %y) #1 {
; GFX1170-LABEL: v_maximumnum_v2f64:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[6:7]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -9298,11 +8733,6 @@ define <2 x double> @v_maximumnum_v2f64(<2 x double> %x, <2 x double> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -9311,9 +8741,6 @@ define <2 x double> @v_maximumnum_v2f64(<2 x double> %x, <2 x double> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f64 v[4:7], v[4:7], v[4:7]
-; GFX1251-NEXT: v_pk_max_num_f64 v[0:3], v[0:3], v[0:3]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_pk_max_num_f64 v[0:3], v[0:3], v[4:7]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_v2f64:
@@ -9577,14 +9004,7 @@ define <3 x double> @v_maximumnum_v3f64(<3 x double> %x, <3 x double> %y) #1 {
; GFX1170-LABEL: v_maximumnum_v3f64:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[6:7]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[8:9]
; GFX1170-NEXT: v_max_num_f64 v[4:5], v[4:5], v[10:11]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -9596,14 +9016,7 @@ define <3 x double> @v_maximumnum_v3f64(<3 x double> %x, <3 x double> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[8:9]
; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[10:11]
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -9612,14 +9025,7 @@ define <3 x double> @v_maximumnum_v3f64(<3 x double> %x, <3 x double> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1251-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX1251-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1251-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX1251-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1251-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[8:9]
; GFX1251-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[10:11]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -9932,18 +9338,9 @@ define <4 x double> @v_maximumnum_v4f64(<4 x double> %x, <4 x double> %y) #1 {
; GFX1170-LABEL: v_maximumnum_v4f64:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[12:13], v[12:13], v[12:13]
-; GFX1170-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-NEXT: v_max_num_f64 v[14:15], v[14:15], v[14:15]
-; GFX1170-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[8:9]
; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[10:11]
; GFX1170-NEXT: v_max_num_f64 v[4:5], v[4:5], v[12:13]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1170-NEXT: v_max_num_f64 v[6:7], v[6:7], v[14:15]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -9954,18 +9351,9 @@ define <4 x double> @v_maximumnum_v4f64(<4 x double> %x, <4 x double> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[12:13], v[12:13], v[12:13]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-NEXT: v_max_num_f64_e32 v[14:15], v[14:15], v[14:15]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[8:9]
; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[10:11]
; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[12:13]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[14:15]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -9973,11 +9361,6 @@ define <4 x double> @v_maximumnum_v4f64(<4 x double> %x, <4 x double> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f64 v[8:11], v[8:11], v[8:11]
-; GFX1251-NEXT: v_pk_max_num_f64 v[0:3], v[0:3], v[0:3]
-; GFX1251-NEXT: v_pk_max_num_f64 v[12:15], v[12:15], v[12:15]
-; GFX1251-NEXT: v_pk_max_num_f64 v[4:7], v[4:7], v[4:7]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1251-NEXT: v_pk_max_num_f64 v[0:3], v[0:3], v[8:11]
; GFX1251-NEXT: v_pk_max_num_f64 v[4:7], v[4:7], v[12:15]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -10266,18 +9649,12 @@ define half @v_maximumnum_f16_no_ieee(half %x, half %y) #0 {
; GFX1170-TRUE16-LABEL: v_maximumnum_f16_no_ieee:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_maximumnum_f16_no_ieee:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -10288,10 +9665,7 @@ define half @v_maximumnum_f16_no_ieee(half %x, half %y) #0 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_f16_no_ieee:
@@ -10301,9 +9675,6 @@ define half @v_maximumnum_f16_no_ieee(half %x, half %y) #0 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -10311,19 +9682,13 @@ define half @v_maximumnum_f16_no_ieee(half %x, half %y) #0 {
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_maximumnum_f16_no_ieee:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_f16_no_ieee:
@@ -10527,8 +9892,6 @@ define float @v_maximumnum_f32_no_ieee(float %x, float %y) #0 {
; GFX1170-LABEL: v_maximumnum_f32_no_ieee:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -10539,8 +9902,6 @@ define float @v_maximumnum_f32_no_ieee(float %x, float %y) #0 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -10548,8 +9909,6 @@ define float @v_maximumnum_f32_no_ieee(float %x, float %y) #0 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX1170-GISEL-LABEL: v_maximumnum_f32_no_ieee:
@@ -10673,9 +10032,6 @@ define double @v_maximumnum_f64_no_ieee(double %x, double %y) #0 {
; GFX1170-LABEL: v_maximumnum_f64_no_ieee:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -10686,9 +10042,6 @@ define double @v_maximumnum_f64_no_ieee(double %x, double %y) #0 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -10696,9 +10049,6 @@ define double @v_maximumnum_f64_no_ieee(double %x, double %y) #0 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX1170-GISEL-LABEL: v_maximumnum_f64_no_ieee:
@@ -10838,9 +10188,6 @@ define <2 x half> @v_maximumnum_v2f16_no_ieee(<2 x half> %x, <2 x half> %y) #0 {
; GFX1170-LABEL: v_maximumnum_v2f16_no_ieee:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -10851,9 +10198,6 @@ define <2 x half> @v_maximumnum_v2f16_no_ieee(<2 x half> %x, <2 x half> %y) #0 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -10861,9 +10205,6 @@ define <2 x half> @v_maximumnum_v2f16_no_ieee(<2 x half> %x, <2 x half> %y) #0 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_maximumnum_v2f16_no_ieee:
@@ -11621,37 +10962,6 @@ define <32 x half> @v_maximumnum_v32f16_no_ieee(<32 x half> %x, <32 x half> %y)
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX1170-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX1170-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX1170-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX1170-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX1170-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX1170-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX1170-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX1170-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX1170-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX1170-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX1170-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX1170-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX1170-NEXT: v_pk_max_num_f16 v15, v15, v15
; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v16
; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v17
; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v18
@@ -11668,9 +10978,7 @@ define <32 x half> @v_maximumnum_v32f16_no_ieee(<32 x half> %x, <32 x half> %y)
; GFX1170-NEXT: v_pk_max_num_f16 v13, v13, v29
; GFX1170-NEXT: v_pk_max_num_f16 v14, v14, v30
; GFX1170-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_pk_max_num_f16 v15, v15, v16
+; GFX1170-NEXT: v_pk_max_num_f16 v15, v15, v31
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_v32f16_no_ieee:
@@ -11681,37 +10989,6 @@ define <32 x half> @v_maximumnum_v32f16_no_ieee(<32 x half> %x, <32 x half> %y)
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX12-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX12-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX12-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX12-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX12-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX12-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX12-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX12-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX12-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX12-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX12-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX12-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX12-NEXT: v_pk_max_num_f16 v15, v15, v15
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v16
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v17
; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v18
@@ -11728,9 +11005,7 @@ define <32 x half> @v_maximumnum_v32f16_no_ieee(<32 x half> %x, <32 x half> %y)
; GFX12-NEXT: v_pk_max_num_f16 v13, v13, v29
; GFX12-NEXT: v_pk_max_num_f16 v14, v14, v30
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v15, v15, v16
+; GFX12-NEXT: v_pk_max_num_f16 v15, v15, v31
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_maximumnum_v32f16_no_ieee:
@@ -11738,37 +11013,6 @@ define <32 x half> @v_maximumnum_v32f16_no_ieee(<32 x half> %x, <32 x half> %y)
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
; GFX1251-NEXT: scratch_load_b32 v31, off, s32
-; GFX1251-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1251-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1251-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX1251-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1251-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX1251-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1251-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX1251-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1251-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX1251-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1251-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX1251-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1251-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX1251-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1251-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX1251-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1251-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX1251-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX1251-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX1251-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX1251-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX1251-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX1251-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX1251-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX1251-NEXT: v_pk_max_num_f16 v15, v15, v15
; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v16
; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v17
; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v18
@@ -11785,9 +11029,7 @@ define <32 x half> @v_maximumnum_v32f16_no_ieee(<32 x half> %x, <32 x half> %y)
; GFX1251-NEXT: v_pk_max_num_f16 v13, v13, v29
; GFX1251-NEXT: v_pk_max_num_f16 v14, v14, v30
; GFX1251-NEXT: s_wait_loadcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_pk_max_num_f16 v15, v15, v16
+; GFX1251-NEXT: v_pk_max_num_f16 v15, v15, v31
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
%result = call <32 x half> @llvm.maximumnum.v32f16(<32 x half> %x, <32 x half> %y)
ret <32 x half> %result
diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.ll
index 82aaf92697c1d..058fa30d8a96b 100644
--- a/llvm/test/CodeGen/AMDGPU/minimumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimumnum.ll
@@ -93,18 +93,12 @@ define half @v_minimumnum_f16(half %x, half %y) #1 {
; GFX1170-TRUE16-LABEL: v_minimumnum_f16:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_minimumnum_f16:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -115,10 +109,7 @@ define half @v_minimumnum_f16(half %x, half %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_f16:
@@ -128,9 +119,6 @@ define half @v_minimumnum_f16(half %x, half %y) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -138,19 +126,13 @@ define half @v_minimumnum_f16(half %x, half %y) #1 {
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_minimumnum_f16:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f16:
@@ -406,16 +388,12 @@ define half @v_minimumnum_f16_1.0(half %x) #1 {
; GFX1170-TRUE16-LABEL: v_minimumnum_f16_1.0:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, 1.0, v0.l
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_minimumnum_f16_1.0:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, 1.0, v0
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -426,8 +404,6 @@ define half @v_minimumnum_f16_1.0(half %x) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, 1.0, v0.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -438,8 +414,6 @@ define half @v_minimumnum_f16_1.0(half %x) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, 1.0, v0
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -447,8 +421,6 @@ define half @v_minimumnum_f16_1.0(half %x) #1 {
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-TRUE16-NEXT: v_min_num_f16_e32 v0.l, 1.0, v0.l
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -456,8 +428,6 @@ define half @v_minimumnum_f16_1.0(half %x) #1 {
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-FAKE16-NEXT: v_min_num_f16_e32 v0, 1.0, v0
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
%result = call half @llvm.minimumnum.f16(half %x, half 1.0)
@@ -508,8 +478,6 @@ define float @v_minimumnum_f32(float %x, float %y) #1 {
; GFX1170-LABEL: v_minimumnum_f32:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -520,8 +488,6 @@ define float @v_minimumnum_f32(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -529,8 +495,6 @@ define float @v_minimumnum_f32(float %x, float %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f32:
@@ -700,9 +664,6 @@ define double @v_minimumnum_f64(double %x, double %y) #1 {
; GFX1170-LABEL: v_minimumnum_f64:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -713,9 +674,6 @@ define double @v_minimumnum_f64(double %x, double %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -723,9 +681,6 @@ define double @v_minimumnum_f64(double %x, double %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f64:
@@ -894,8 +849,6 @@ define float @v_minimumnum_f32_1.0(float %x) #1 {
; GFX1170-LABEL: v_minimumnum_f32_1.0:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f32_e32 v0, 1.0, v0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -906,8 +859,6 @@ define float @v_minimumnum_f32_1.0(float %x) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v0, 1.0, v0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -915,8 +866,6 @@ define float @v_minimumnum_f32_1.0(float %x) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_min_num_f32_e32 v0, 1.0, v0
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
%result = call float @llvm.minimumnum.f32(float %x, float 1.0)
@@ -967,7 +916,7 @@ define float @v_minimumnum_f32_rhs_not_snan(float %x, float %y) #1 {
; GFX1170-LABEL: v_minimumnum_f32_rhs_not_snan:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
+; GFX1170-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -979,7 +928,7 @@ define float @v_minimumnum_f32_rhs_not_snan(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
+; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -988,7 +937,7 @@ define float @v_minimumnum_f32_rhs_not_snan(float %x, float %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
+; GFX1251-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -1041,7 +990,7 @@ define float @v_minimumnum_f32_lhs_not_snan(float %x, float %y) #1 {
; GFX1170-LABEL: v_minimumnum_f32_lhs_not_snan:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -1053,7 +1002,7 @@ define float @v_minimumnum_f32_lhs_not_snan(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -1062,7 +1011,7 @@ define float @v_minimumnum_f32_lhs_not_snan(float %x, float %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v0
; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -1186,8 +1135,6 @@ define double @v_minimumnum_f64_1.0(double %x) #1 {
; GFX1170-LABEL: v_minimumnum_f64_1.0:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], 1.0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -1198,8 +1145,6 @@ define double @v_minimumnum_f64_1.0(double %x) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], 1.0, v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -1207,8 +1152,6 @@ define double @v_minimumnum_f64_1.0(double %x) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_min_num_f64_e32 v[0:1], 1.0, v[0:1]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
%result = call double @llvm.minimumnum.f64(double %x, double 1.0)
@@ -1278,19 +1221,13 @@ define half @v_minimumnum_f16_v_s(half %x, half inreg %y) #1 {
; GFX1170-TRUE16-LABEL: v_minimumnum_f16_v_s:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, s0, v0.l
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_minimumnum_f16_v_s:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, s0, v0
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: v_minimumnum_f16_v_s:
@@ -1300,10 +1237,7 @@ define half @v_minimumnum_f16_v_s(half %x, half inreg %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, s0, v0.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_f16_v_s:
@@ -1313,30 +1247,21 @@ define half @v_minimumnum_f16_v_s(half %x, half inreg %y) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, s0, v0
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-TRUE16-LABEL: v_minimumnum_f16_v_s:
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_min_num_f16_e32 v0.l, s0, v0.l
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_minimumnum_f16_v_s:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1251-FAKE16-NEXT: v_min_num_f16_e32 v0, s0, v0
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f16_v_s:
; GFX7-GISEL: ; %bb.0:
@@ -1512,69 +1437,35 @@ define half @v_minimumnum_f16_s_s(half inreg %x, half inreg %y) #1 {
; GFX11-FAKE16-NEXT: v_min_f16_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-LABEL: v_minimumnum_f16_s_s:
-; GFX1170-TRUE16: ; %bb.0:
-; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, s1, s1
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.h, v0.l
-; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-LABEL: v_minimumnum_f16_s_s:
-; GFX1170-FAKE16: ; %bb.0:
-; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, s1, s1
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, v1, v0
-; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-LABEL: v_minimumnum_f16_s_s:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, s1, s1
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-LABEL: v_minimumnum_f16_s_s:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, s1, s1
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v1, v0
-; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f16_s_s:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: s_min_f16 s0, s0, s1
+; GFX1170-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1170-NEXT: v_mov_b32_e32 v0, s0
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1251-TRUE16-LABEL: v_minimumnum_f16_s_s:
-; GFX1251-TRUE16: ; %bb.0:
-; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.l, s1, s1
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.h, v0.l
-; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+; GFX12-LABEL: v_minimumnum_f16_s_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_min_num_f16 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1251-FAKE16-LABEL: v_minimumnum_f16_s_s:
-; GFX1251-FAKE16: ; %bb.0:
-; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v0, s1, s1
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-FAKE16-NEXT: v_min_num_f16_e32 v0, v1, v0
-; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+; GFX1251-LABEL: v_minimumnum_f16_s_s:
+; GFX1251: ; %bb.0:
+; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1251-NEXT: s_wait_kmcnt 0x0
+; GFX1251-NEXT: s_min_num_f16 s0, s0, s1
+; GFX1251-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1251-NEXT: v_mov_b32_e32 v0, s0
+; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f16_s_s:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1760,10 +1651,7 @@ define float @v_minimumnum_f32_s_v(float inreg %x, float %y) #1 {
; GFX1170-LABEL: v_minimumnum_f32_s_v:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f32_e32 v0, v1, v0
+; GFX1170-NEXT: v_min_num_f32_e32 v0, s0, v0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_f32_s_v:
@@ -1773,20 +1661,14 @@ define float @v_minimumnum_f32_s_v(float inreg %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f32_e32 v0, v1, v0
+; GFX12-NEXT: v_min_num_f32_e32 v0, s0, v0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_f32_s_v:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1251-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_min_num_f32_e32 v0, v1, v0
+; GFX1251-NEXT: v_min_num_f32_e32 v0, s0, v0
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f32_s_v:
; GFX7-GISEL: ; %bb.0:
@@ -1917,10 +1799,7 @@ define float @v_minimumnum_f32_v_s(float %x, float inreg %y) #1 {
; GFX1170-LABEL: v_minimumnum_f32_v_s:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: v_min_num_f32_e32 v0, s0, v0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_f32_v_s:
@@ -1930,20 +1809,14 @@ define float @v_minimumnum_f32_v_s(float %x, float inreg %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_min_num_f32_e32 v0, s0, v0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_f32_v_s:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1251-NEXT: v_min_num_f32_e32 v0, s0, v0
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f32_v_s:
; GFX7-GISEL: ; %bb.0:
@@ -2074,10 +1947,9 @@ define float @v_minimumnum_f32_s_s(float inreg %x, float inreg %y) #1 {
; GFX1170-LABEL: v_minimumnum_f32_s_s:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e64 v0, s1, s1
-; GFX1170-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f32_e32 v0, v1, v0
+; GFX1170-NEXT: s_min_f32 s0, s0, s1
+; GFX1170-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1170-NEXT: v_mov_b32_e32 v0, s0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_f32_s_s:
@@ -2087,20 +1959,19 @@ define float @v_minimumnum_f32_s_s(float inreg %x, float inreg %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v0, s1, s1
-; GFX12-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f32_e32 v0, v1, v0
+; GFX12-NEXT: s_min_num_f32 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_f32_s_s:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e64 v0, s1, s1
-; GFX1251-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_min_num_f32_e32 v0, v1, v0
+; GFX1251-NEXT: s_min_num_f32 s0, s0, s1
+; GFX1251-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1251-NEXT: v_mov_b32_e32 v0, s0
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f32_s_s:
; GFX7-GISEL: ; %bb.0:
@@ -2240,10 +2111,7 @@ define double @v_minimumnum_f64_s_v(double inreg %x, double %y) #1 {
; GFX1170-LABEL: v_minimumnum_f64_s_v:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], s[0:1], s[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f64 v[0:1], v[2:3], v[0:1]
+; GFX1170-NEXT: v_min_num_f64 v[0:1], s[0:1], v[0:1]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_f64_s_v:
@@ -2253,20 +2121,14 @@ define double @v_minimumnum_f64_s_v(double inreg %x, double %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], s[0:1], v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_f64_s_v:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX1251-NEXT: v_min_num_f64_e32 v[0:1], s[0:1], v[0:1]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f64_s_v:
; GFX7-GISEL: ; %bb.0:
@@ -2353,10 +2215,7 @@ define double @v_minimumnum_f64_v_s(double %x, double inreg %y) #1 {
; GFX1170-LABEL: v_minimumnum_f64_v_s:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], s[0:1], s[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], s[0:1]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_f64_v_s:
@@ -2366,20 +2225,14 @@ define double @v_minimumnum_f64_v_s(double %x, double inreg %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], s[0:1], v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_f64_v_s:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX1251-NEXT: v_min_num_f64_e32 v[0:1], s[0:1], v[0:1]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f64_v_s:
; GFX7-GISEL: ; %bb.0:
@@ -2466,10 +2319,7 @@ define double @v_minimumnum_f64_s_s(double inreg %x, double inreg %y) #1 {
; GFX1170-LABEL: v_minimumnum_f64_s_s:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[0:1], s[2:3], s[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], s[0:1], s[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f64 v[0:1], v[2:3], v[0:1]
+; GFX1170-NEXT: v_min_num_f64 v[0:1], s[0:1], s[2:3]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_f64_s_s:
@@ -2479,20 +2329,14 @@ define double @v_minimumnum_f64_s_s(double inreg %x, double inreg %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
-; GFX12-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX12-NEXT: v_min_num_f64_e64 v[0:1], s[0:1], s[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_f64_s_s:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
-; GFX1251-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX1251-NEXT: v_min_num_f64_e64 v[0:1], s[0:1], s[2:3]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f64_s_s:
; GFX7-GISEL: ; %bb.0:
@@ -2615,10 +2459,7 @@ define float @v_minimumnum_f32_fabs_rhs(float %x, float %y) #1 {
; GFX1170-LABEL: v_minimumnum_f32_fabs_rhs:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: v_min_num_f32_e64 v0, v0, |v1|
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_f32_fabs_rhs:
@@ -2628,20 +2469,14 @@ define float @v_minimumnum_f32_fabs_rhs(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_min_num_f32_e64 v0, v0, |v1|
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_f32_fabs_rhs:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1251-NEXT: v_min_num_f32_e64 v0, v0, |v1|
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f32_fabs_rhs:
; GFX7-GISEL: ; %bb.0:
@@ -2758,10 +2593,7 @@ define float @v_minimumnum_f32_fneg_fabs_rhs(float %x, float %y) #1 {
; GFX1170-LABEL: v_minimumnum_f32_fneg_fabs_rhs:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: v_min_num_f32_e64 v0, v0, -|v1|
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_f32_fneg_fabs_rhs:
@@ -2771,20 +2603,14 @@ define float @v_minimumnum_f32_fneg_fabs_rhs(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_min_num_f32_e64 v0, v0, -|v1|
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_f32_fneg_fabs_rhs:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX1251-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1251-NEXT: v_min_num_f32_e64 v0, v0, -|v1|
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f32_fneg_fabs_rhs:
; GFX7-GISEL: ; %bb.0:
@@ -2902,10 +2728,7 @@ define float @v_minimumnum_f32_fabs(float %x, float %y) #1 {
; GFX1170-LABEL: v_minimumnum_f32_fabs:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1170-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: v_min_num_f32_e64 v0, |v0|, |v1|
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_f32_fabs:
@@ -2915,20 +2738,14 @@ define float @v_minimumnum_f32_fabs(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX12-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_min_num_f32_e64 v0, |v0|, |v1|
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_f32_fabs:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1251-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1251-NEXT: v_min_num_f32_e64 v0, |v0|, |v1|
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f32_fabs:
; GFX7-GISEL: ; %bb.0:
@@ -3046,10 +2863,7 @@ define float @v_minimumnum_f32_fneg(float %x, float %y) #1 {
; GFX1170-LABEL: v_minimumnum_f32_fneg:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX1170-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: v_min_num_f32_e64 v0, -v0, -v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_f32_fneg:
@@ -3059,19 +2873,14 @@ define float @v_minimumnum_f32_fneg(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_min_num_f32_e64 v0, -v0, -v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_f32_fneg:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v1, -v1, -v1 :: v_dual_max_num_f32 v0, -v0, -v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1251-NEXT: v_min_num_f32_e64 v0, -v0, -v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f32_fneg:
; GFX7-GISEL: ; %bb.0:
@@ -3198,19 +3007,13 @@ define half @v_minimumnum_f16_fabs_rhs(half %x, half %y) #1 {
; GFX1170-TRUE16-LABEL: v_minimumnum_f16_fabs_rhs:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e64 v0.l, v0.l, |v1.l|
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_minimumnum_f16_fabs_rhs:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: v_min_num_f16_e64 v0, v0, |v1|
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: v_minimumnum_f16_fabs_rhs:
@@ -3220,10 +3023,7 @@ define half @v_minimumnum_f16_fabs_rhs(half %x, half %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_min_num_f16_e64 v0.l, v0.l, |v1.l|
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_f16_fabs_rhs:
@@ -3233,30 +3033,21 @@ define half @v_minimumnum_f16_fabs_rhs(half %x, half %y) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_min_num_f16_e64 v0, v0, |v1|
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-TRUE16-LABEL: v_minimumnum_f16_fabs_rhs:
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_min_num_f16_e64 v0.l, v0.l, |v1.l|
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_minimumnum_f16_fabs_rhs:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1251-FAKE16-NEXT: v_min_num_f16_e64 v0, v0, |v1|
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f16_fabs_rhs:
; GFX7-GISEL: ; %bb.0:
@@ -3421,19 +3212,13 @@ define half @v_minimumnum_f16_fneg_fabs_rhs(half %x, half %y) #1 {
; GFX1170-TRUE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e64 v0.l, v0.l, -|v1.l|
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: v_min_num_f16_e64 v0, v0, -|v1|
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
@@ -3443,10 +3228,7 @@ define half @v_minimumnum_f16_fneg_fabs_rhs(half %x, half %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_min_num_f16_e64 v0.l, v0.l, -|v1.l|
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
@@ -3456,30 +3238,21 @@ define half @v_minimumnum_f16_fneg_fabs_rhs(half %x, half %y) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_min_num_f16_e64 v0, v0, -|v1|
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-TRUE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_min_num_f16_e64 v0.l, v0.l, -|v1.l|
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1251-FAKE16-NEXT: v_min_num_f16_e64 v0, v0, -|v1|
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
; GFX7-GISEL: ; %bb.0:
@@ -3645,19 +3418,13 @@ define half @v_minimumnum_f16_fabs(half %x, half %y) #1 {
; GFX1170-TRUE16-LABEL: v_minimumnum_f16_fabs:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e64 v0.l, |v0.l|, |v1.l|
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_minimumnum_f16_fabs:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: v_min_num_f16_e64 v0, |v0|, |v1|
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: v_minimumnum_f16_fabs:
@@ -3667,10 +3434,7 @@ define half @v_minimumnum_f16_fabs(half %x, half %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_min_num_f16_e64 v0.l, |v0.l|, |v1.l|
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_f16_fabs:
@@ -3680,30 +3444,21 @@ define half @v_minimumnum_f16_fabs(half %x, half %y) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_min_num_f16_e64 v0, |v0|, |v1|
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-TRUE16-LABEL: v_minimumnum_f16_fabs:
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_min_num_f16_e64 v0.l, |v0.l|, |v1.l|
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_minimumnum_f16_fabs:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1251-FAKE16-NEXT: v_min_num_f16_e64 v0, |v0|, |v1|
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f16_fabs:
; GFX7-GISEL: ; %bb.0:
@@ -3869,19 +3624,13 @@ define half @v_minimumnum_f16_fneg(half %x, half %y) #1 {
; GFX1170-TRUE16-LABEL: v_minimumnum_f16_fneg:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e64 v0.l, -v0.l, -v1.l
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_minimumnum_f16_fneg:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: v_min_num_f16_e64 v0, -v0, -v1
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: v_minimumnum_f16_fneg:
@@ -3891,10 +3640,7 @@ define half @v_minimumnum_f16_fneg(half %x, half %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_min_num_f16_e64 v0.l, -v0.l, -v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_f16_fneg:
@@ -3904,30 +3650,21 @@ define half @v_minimumnum_f16_fneg(half %x, half %y) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_min_num_f16_e64 v0, -v0, -v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-TRUE16-LABEL: v_minimumnum_f16_fneg:
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_min_num_f16_e64 v0.l, -v0.l, -v1.l
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_minimumnum_f16_fneg:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1251-FAKE16-NEXT: v_min_num_f16_e64 v0, -v0, -v1
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f16_fneg:
; GFX7-GISEL: ; %bb.0:
@@ -4083,10 +3820,7 @@ define double @v_minimumnum_f64_fneg(double %x, double %y) #1 {
; GFX1170-LABEL: v_minimumnum_f64_fneg:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], -v[2:3], -v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], -v[0:1], -v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: v_min_num_f64 v[0:1], -v[0:1], -v[2:3]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_f64_fneg:
@@ -4096,20 +3830,14 @@ define double @v_minimumnum_f64_fneg(double %x, double %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e64 v[2:3], -v[2:3], -v[2:3]
-; GFX12-NEXT: v_max_num_f64_e64 v[0:1], -v[0:1], -v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: v_min_num_f64_e64 v[0:1], -v[0:1], -v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_f64_fneg:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e64 v[2:3], -v[2:3], -v[2:3]
-; GFX1251-NEXT: v_max_num_f64_e64 v[0:1], -v[0:1], -v[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX1251-NEXT: v_min_num_f64_e64 v[0:1], -v[0:1], -v[2:3]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f64_fneg:
; GFX7-GISEL: ; %bb.0:
@@ -4249,9 +3977,6 @@ define <2 x half> @v_minimumnum_v2f16(<2 x half> %x, <2 x half> %y) #1 {
; GFX1170-LABEL: v_minimumnum_v2f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -4262,9 +3987,6 @@ define <2 x half> @v_minimumnum_v2f16(<2 x half> %x, <2 x half> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -4272,9 +3994,6 @@ define <2 x half> @v_minimumnum_v2f16(<2 x half> %x, <2 x half> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_v2f16:
@@ -4534,11 +4253,6 @@ define <3 x half> @v_minimumnum_v3f16(<3 x half> %x, <3 x half> %y) #1 {
; GFX1170-LABEL: v_minimumnum_v3f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX1170-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -4550,11 +4264,6 @@ define <3 x half> @v_minimumnum_v3f16(<3 x half> %x, <3 x half> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4563,11 +4272,6 @@ define <3 x half> @v_minimumnum_v3f16(<3 x half> %x, <3 x half> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1251-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX1251-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -4902,11 +4606,6 @@ define <4 x half> @v_minimumnum_v4f16(<4 x half> %x, <4 x half> %y) #1 {
; GFX1170-LABEL: v_minimumnum_v4f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX1170-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -4918,11 +4617,6 @@ define <4 x half> @v_minimumnum_v4f16(<4 x half> %x, <4 x half> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4931,11 +4625,6 @@ define <4 x half> @v_minimumnum_v4f16(<4 x half> %x, <4 x half> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1251-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX1251-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -5327,14 +5016,7 @@ define <6 x half> @v_minimumnum_v6f16(<6 x half> %x, <6 x half> %y) #1 {
; GFX1170-LABEL: v_minimumnum_v6f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v3
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-NEXT: v_pk_min_num_f16 v1, v1, v4
; GFX1170-NEXT: v_pk_min_num_f16 v2, v2, v5
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -5346,14 +5028,7 @@ define <6 x half> @v_minimumnum_v6f16(<6 x half> %x, <6 x half> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v4
; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -5362,14 +5037,7 @@ define <6 x half> @v_minimumnum_v6f16(<6 x half> %x, <6 x half> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX1251-NEXT: v_pk_min_num_f16 v0, v0, v3
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1251-NEXT: v_pk_min_num_f16 v1, v1, v4
; GFX1251-NEXT: v_pk_min_num_f16 v2, v2, v5
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -5703,18 +5371,9 @@ define <8 x half> @v_minimumnum_v8f16(<8 x half> %x, <8 x half> %y) #1 {
; GFX1170-LABEL: v_minimumnum_v8f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v4
; GFX1170-NEXT: v_pk_min_num_f16 v1, v1, v5
; GFX1170-NEXT: v_pk_min_num_f16 v2, v2, v6
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1170-NEXT: v_pk_min_num_f16 v3, v3, v7
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -5725,18 +5384,9 @@ define <8 x half> @v_minimumnum_v8f16(<8 x half> %x, <8 x half> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v4
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v5
; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v6
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v7
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -5744,18 +5394,9 @@ define <8 x half> @v_minimumnum_v8f16(<8 x half> %x, <8 x half> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1251-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
; GFX1251-NEXT: v_pk_min_num_f16 v0, v0, v4
; GFX1251-NEXT: v_pk_min_num_f16 v1, v1, v5
; GFX1251-NEXT: v_pk_min_num_f16 v2, v2, v6
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1251-NEXT: v_pk_min_num_f16 v3, v3, v7
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_v8f16:
@@ -6251,30 +5892,14 @@ define <16 x half> @v_minimumnum_v16f16(<16 x half> %x, <16 x half> %y) #1 {
; GFX1170-LABEL: v_minimumnum_v16f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v8
-; GFX1170-NEXT: v_pk_max_num_f16 v8, v11, v11
; GFX1170-NEXT: v_pk_min_num_f16 v1, v1, v9
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
; GFX1170-NEXT: v_pk_min_num_f16 v2, v2, v10
-; GFX1170-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX1170-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX1170-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-NEXT: v_pk_min_num_f16 v3, v3, v8
-; GFX1170-NEXT: v_pk_min_num_f16 v4, v4, v9
-; GFX1170-NEXT: v_pk_min_num_f16 v5, v5, v10
-; GFX1170-NEXT: v_pk_min_num_f16 v6, v6, v11
-; GFX1170-NEXT: v_pk_min_num_f16 v7, v7, v12
+; GFX1170-NEXT: v_pk_min_num_f16 v3, v3, v11
+; GFX1170-NEXT: v_pk_min_num_f16 v4, v4, v12
+; GFX1170-NEXT: v_pk_min_num_f16 v5, v5, v13
+; GFX1170-NEXT: v_pk_min_num_f16 v6, v6, v14
+; GFX1170-NEXT: v_pk_min_num_f16 v7, v7, v15
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_v16f16:
@@ -6284,60 +5909,28 @@ define <16 x half> @v_minimumnum_v16f16(<16 x half> %x, <16 x half> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v8
-; GFX12-NEXT: v_pk_max_num_f16 v8, v11, v11
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v9
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v10
-; GFX12-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX12-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX12-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v8
-; GFX12-NEXT: v_pk_min_num_f16 v4, v4, v9
-; GFX12-NEXT: v_pk_min_num_f16 v5, v5, v10
-; GFX12-NEXT: v_pk_min_num_f16 v6, v6, v11
-; GFX12-NEXT: v_pk_min_num_f16 v7, v7, v12
+; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v11
+; GFX12-NEXT: v_pk_min_num_f16 v4, v4, v12
+; GFX12-NEXT: v_pk_min_num_f16 v5, v5, v13
+; GFX12-NEXT: v_pk_min_num_f16 v6, v6, v14
+; GFX12-NEXT: v_pk_min_num_f16 v7, v7, v15
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_v16f16:
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX1251-NEXT: v_pk_min_num_f16 v0, v0, v8
-; GFX1251-NEXT: v_pk_max_num_f16 v8, v11, v11
; GFX1251-NEXT: v_pk_min_num_f16 v1, v1, v9
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
; GFX1251-NEXT: v_pk_min_num_f16 v2, v2, v10
-; GFX1251-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX1251-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1251-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX1251-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1251-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX1251-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1251-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX1251-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1251-NEXT: v_pk_min_num_f16 v3, v3, v8
-; GFX1251-NEXT: v_pk_min_num_f16 v4, v4, v9
-; GFX1251-NEXT: v_pk_min_num_f16 v5, v5, v10
-; GFX1251-NEXT: v_pk_min_num_f16 v6, v6, v11
-; GFX1251-NEXT: v_pk_min_num_f16 v7, v7, v12
+; GFX1251-NEXT: v_pk_min_num_f16 v3, v3, v11
+; GFX1251-NEXT: v_pk_min_num_f16 v4, v4, v12
+; GFX1251-NEXT: v_pk_min_num_f16 v5, v5, v13
+; GFX1251-NEXT: v_pk_min_num_f16 v6, v6, v14
+; GFX1251-NEXT: v_pk_min_num_f16 v7, v7, v15
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_v16f16:
; GFX7-GISEL: ; %bb.0:
@@ -7285,37 +6878,6 @@ define <32 x half> @v_minimumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX1170-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX1170-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX1170-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX1170-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX1170-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX1170-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX1170-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX1170-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX1170-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX1170-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX1170-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX1170-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX1170-NEXT: v_pk_max_num_f16 v15, v15, v15
; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v16
; GFX1170-NEXT: v_pk_min_num_f16 v1, v1, v17
; GFX1170-NEXT: v_pk_min_num_f16 v2, v2, v18
@@ -7332,9 +6894,7 @@ define <32 x half> @v_minimumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX1170-NEXT: v_pk_min_num_f16 v13, v13, v29
; GFX1170-NEXT: v_pk_min_num_f16 v14, v14, v30
; GFX1170-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_pk_min_num_f16 v15, v15, v16
+; GFX1170-NEXT: v_pk_min_num_f16 v15, v15, v31
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_v32f16:
@@ -7345,37 +6905,6 @@ define <32 x half> @v_minimumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX12-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX12-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX12-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX12-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX12-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX12-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX12-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX12-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX12-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX12-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX12-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX12-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX12-NEXT: v_pk_max_num_f16 v15, v15, v15
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v16
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v17
; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v18
@@ -7392,9 +6921,7 @@ define <32 x half> @v_minimumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX12-NEXT: v_pk_min_num_f16 v13, v13, v29
; GFX12-NEXT: v_pk_min_num_f16 v14, v14, v30
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v15, v15, v16
+; GFX12-NEXT: v_pk_min_num_f16 v15, v15, v31
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_v32f16:
@@ -7402,37 +6929,6 @@ define <32 x half> @v_minimumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
; GFX1251-NEXT: scratch_load_b32 v31, off, s32
-; GFX1251-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1251-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1251-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX1251-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1251-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX1251-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1251-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX1251-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1251-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX1251-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1251-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX1251-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1251-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX1251-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1251-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX1251-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1251-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX1251-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX1251-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX1251-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX1251-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX1251-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX1251-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX1251-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX1251-NEXT: v_pk_max_num_f16 v15, v15, v15
; GFX1251-NEXT: v_pk_min_num_f16 v0, v0, v16
; GFX1251-NEXT: v_pk_min_num_f16 v1, v1, v17
; GFX1251-NEXT: v_pk_min_num_f16 v2, v2, v18
@@ -7449,9 +6945,7 @@ define <32 x half> @v_minimumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX1251-NEXT: v_pk_min_num_f16 v13, v13, v29
; GFX1251-NEXT: v_pk_min_num_f16 v14, v14, v30
; GFX1251-NEXT: s_wait_loadcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_pk_min_num_f16 v15, v15, v16
+; GFX1251-NEXT: v_pk_min_num_f16 v15, v15, v31
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_v32f16:
; GFX7-GISEL: ; %bb.0:
@@ -8218,9 +7712,6 @@ define <2 x float> @v_minimumnum_v2f32(<2 x float> %x, <2 x float> %y) #1 {
; GFX1170-LABEL: v_minimumnum_v2f32:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -8231,9 +7722,6 @@ define <2 x float> @v_minimumnum_v2f32(<2 x float> %x, <2 x float> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -8241,9 +7729,6 @@ define <2 x float> @v_minimumnum_v2f32(<2 x float> %x, <2 x float> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1251-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_v2f32:
@@ -8459,10 +7944,6 @@ define <3 x float> @v_minimumnum_v3f32(<3 x float> %x, <3 x float> %y) #1 {
; GFX1170-LABEL: v_minimumnum_v3f32:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
; GFX1170-NEXT: v_min_num_f32_e32 v2, v2, v5
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -8474,10 +7955,6 @@ define <3 x float> @v_minimumnum_v3f32(<3 x float> %x, <3 x float> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
; GFX12-NEXT: v_min_num_f32_e32 v2, v2, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -8486,10 +7963,6 @@ define <3 x float> @v_minimumnum_v3f32(<3 x float> %x, <3 x float> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1251-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1251-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1251-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
; GFX1251-NEXT: v_min_num_f32_e32 v2, v2, v5
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -8747,11 +8220,6 @@ define <4 x float> @v_minimumnum_v4f32(<4 x float> %x, <4 x float> %y) #1 {
; GFX1170-LABEL: v_minimumnum_v4f32:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX1170-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT: v_dual_min_num_f32 v0, v0, v4 :: v_dual_min_num_f32 v1, v1, v5
; GFX1170-NEXT: v_dual_min_num_f32 v2, v2, v6 :: v_dual_min_num_f32 v3, v3, v7
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -8763,11 +8231,6 @@ define <4 x float> @v_minimumnum_v4f32(<4 x float> %x, <4 x float> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX12-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v4 :: v_dual_min_num_f32 v1, v1, v5
; GFX12-NEXT: v_dual_min_num_f32 v2, v2, v6 :: v_dual_min_num_f32 v3, v3, v7
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -8776,11 +8239,6 @@ define <4 x float> @v_minimumnum_v4f32(<4 x float> %x, <4 x float> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1251-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1251-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX1251-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1251-NEXT: v_dual_min_num_f32 v0, v0, v4 :: v_dual_min_num_f32 v1, v1, v5
; GFX1251-NEXT: v_dual_min_num_f32 v2, v2, v6 :: v_dual_min_num_f32 v3, v3, v7
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -9045,11 +8503,6 @@ define <2 x double> @v_minimumnum_v2f64(<2 x double> %x, <2 x double> %y) #1 {
; GFX1170-LABEL: v_minimumnum_v2f64:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
; GFX1170-NEXT: v_min_num_f64 v[2:3], v[2:3], v[6:7]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -9061,11 +8514,6 @@ define <2 x double> @v_minimumnum_v2f64(<2 x double> %x, <2 x double> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -9074,9 +8522,6 @@ define <2 x double> @v_minimumnum_v2f64(<2 x double> %x, <2 x double> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f64 v[4:7], v[4:7], v[4:7]
-; GFX1251-NEXT: v_pk_max_num_f64 v[0:3], v[0:3], v[0:3]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_pk_min_num_f64 v[0:3], v[0:3], v[4:7]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_v2f64:
@@ -9340,14 +8785,7 @@ define <3 x double> @v_minimumnum_v3f64(<3 x double> %x, <3 x double> %y) #1 {
; GFX1170-LABEL: v_minimumnum_v3f64:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[6:7]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-NEXT: v_min_num_f64 v[2:3], v[2:3], v[8:9]
; GFX1170-NEXT: v_min_num_f64 v[4:5], v[4:5], v[10:11]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -9359,14 +8797,7 @@ define <3 x double> @v_minimumnum_v3f64(<3 x double> %x, <3 x double> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[8:9]
; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[10:11]
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -9375,14 +8806,7 @@ define <3 x double> @v_minimumnum_v3f64(<3 x double> %x, <3 x double> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1251-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX1251-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1251-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX1251-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
; GFX1251-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1251-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[8:9]
; GFX1251-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[10:11]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -9695,18 +9119,9 @@ define <4 x double> @v_minimumnum_v4f64(<4 x double> %x, <4 x double> %y) #1 {
; GFX1170-LABEL: v_minimumnum_v4f64:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[12:13], v[12:13], v[12:13]
-; GFX1170-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-NEXT: v_max_num_f64 v[14:15], v[14:15], v[14:15]
-; GFX1170-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[8:9]
; GFX1170-NEXT: v_min_num_f64 v[2:3], v[2:3], v[10:11]
; GFX1170-NEXT: v_min_num_f64 v[4:5], v[4:5], v[12:13]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1170-NEXT: v_min_num_f64 v[6:7], v[6:7], v[14:15]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -9717,18 +9132,9 @@ define <4 x double> @v_minimumnum_v4f64(<4 x double> %x, <4 x double> %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[12:13], v[12:13], v[12:13]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-NEXT: v_max_num_f64_e32 v[14:15], v[14:15], v[14:15]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[8:9]
; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[10:11]
; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[12:13]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[6:7], v[14:15]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -9736,11 +9142,6 @@ define <4 x double> @v_minimumnum_v4f64(<4 x double> %x, <4 x double> %y) #1 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f64 v[8:11], v[8:11], v[8:11]
-; GFX1251-NEXT: v_pk_max_num_f64 v[0:3], v[0:3], v[0:3]
-; GFX1251-NEXT: v_pk_max_num_f64 v[12:15], v[12:15], v[12:15]
-; GFX1251-NEXT: v_pk_max_num_f64 v[4:7], v[4:7], v[4:7]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1251-NEXT: v_pk_min_num_f64 v[0:3], v[0:3], v[8:11]
; GFX1251-NEXT: v_pk_min_num_f64 v[4:7], v[4:7], v[12:15]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
@@ -10029,18 +9430,12 @@ define half @v_minimumnum_f16_no_ieee(half %x, half %y) #0 {
; GFX1170-TRUE16-LABEL: v_minimumnum_f16_no_ieee:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_minimumnum_f16_no_ieee:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -10051,10 +9446,7 @@ define half @v_minimumnum_f16_no_ieee(half %x, half %y) #0 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_f16_no_ieee:
@@ -10064,9 +9456,6 @@ define half @v_minimumnum_f16_no_ieee(half %x, half %y) #0 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -10074,19 +9463,13 @@ define half @v_minimumnum_f16_no_ieee(half %x, half %y) #0 {
; GFX1251-TRUE16: ; %bb.0:
; GFX1251-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1251-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1251-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1251-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
; GFX1251-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1251-FAKE16-LABEL: v_minimumnum_f16_no_ieee:
; GFX1251-FAKE16: ; %bb.0:
; GFX1251-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1251-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1251-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX1251-FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_f16_no_ieee:
@@ -10290,8 +9673,6 @@ define float @v_minimumnum_f32_no_ieee(float %x, float %y) #0 {
; GFX1170-LABEL: v_minimumnum_f32_no_ieee:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -10302,8 +9683,6 @@ define float @v_minimumnum_f32_no_ieee(float %x, float %y) #0 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -10311,8 +9690,6 @@ define float @v_minimumnum_f32_no_ieee(float %x, float %y) #0 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX1170-GISEL-LABEL: v_minimumnum_f32_no_ieee:
@@ -10436,9 +9813,6 @@ define double @v_minimumnum_f64_no_ieee(double %x, double %y) #0 {
; GFX1170-LABEL: v_minimumnum_f64_no_ieee:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -10449,9 +9823,6 @@ define double @v_minimumnum_f64_no_ieee(double %x, double %y) #0 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -10459,9 +9830,6 @@ define double @v_minimumnum_f64_no_ieee(double %x, double %y) #0 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1251-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX1170-GISEL-LABEL: v_minimumnum_f64_no_ieee:
@@ -10601,9 +9969,6 @@ define <2 x half> @v_minimumnum_v2f16_no_ieee(<2 x half> %x, <2 x half> %y) #0 {
; GFX1170-LABEL: v_minimumnum_v2f16_no_ieee:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -10614,9 +9979,6 @@ define <2 x half> @v_minimumnum_v2f16_no_ieee(<2 x half> %x, <2 x half> %y) #0 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -10624,9 +9986,6 @@ define <2 x half> @v_minimumnum_v2f16_no_ieee(<2 x half> %x, <2 x half> %y) #0 {
; GFX1251: ; %bb.0:
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
; GFX7-GISEL-LABEL: v_minimumnum_v2f16_no_ieee:
@@ -11384,37 +10743,6 @@ define <32 x half> @v_minimumnum_v32f16_no_ieee(<32 x half> %x, <32 x half> %y)
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX1170-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX1170-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX1170-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX1170-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX1170-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX1170-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX1170-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX1170-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX1170-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX1170-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX1170-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX1170-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX1170-NEXT: v_pk_max_num_f16 v15, v15, v15
; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v16
; GFX1170-NEXT: v_pk_min_num_f16 v1, v1, v17
; GFX1170-NEXT: v_pk_min_num_f16 v2, v2, v18
@@ -11431,9 +10759,7 @@ define <32 x half> @v_minimumnum_v32f16_no_ieee(<32 x half> %x, <32 x half> %y)
; GFX1170-NEXT: v_pk_min_num_f16 v13, v13, v29
; GFX1170-NEXT: v_pk_min_num_f16 v14, v14, v30
; GFX1170-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_pk_min_num_f16 v15, v15, v16
+; GFX1170-NEXT: v_pk_min_num_f16 v15, v15, v31
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_v32f16_no_ieee:
@@ -11444,37 +10770,6 @@ define <32 x half> @v_minimumnum_v32f16_no_ieee(<32 x half> %x, <32 x half> %y)
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX12-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX12-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX12-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX12-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX12-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX12-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX12-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX12-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX12-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX12-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX12-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX12-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX12-NEXT: v_pk_max_num_f16 v15, v15, v15
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v16
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v17
; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v18
@@ -11491,9 +10786,7 @@ define <32 x half> @v_minimumnum_v32f16_no_ieee(<32 x half> %x, <32 x half> %y)
; GFX12-NEXT: v_pk_min_num_f16 v13, v13, v29
; GFX12-NEXT: v_pk_min_num_f16 v14, v14, v30
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v15, v15, v16
+; GFX12-NEXT: v_pk_min_num_f16 v15, v15, v31
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1251-LABEL: v_minimumnum_v32f16_no_ieee:
@@ -11501,37 +10794,6 @@ define <32 x half> @v_minimumnum_v32f16_no_ieee(<32 x half> %x, <32 x half> %y)
; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-NEXT: s_wait_kmcnt 0x0
; GFX1251-NEXT: scratch_load_b32 v31, off, s32
-; GFX1251-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX1251-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1251-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX1251-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1251-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX1251-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1251-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX1251-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1251-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX1251-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1251-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX1251-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1251-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX1251-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1251-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX1251-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1251-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX1251-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1251-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX1251-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1251-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX1251-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1251-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX1251-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX1251-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX1251-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX1251-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX1251-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX1251-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX1251-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX1251-NEXT: v_pk_max_num_f16 v15, v15, v15
; GFX1251-NEXT: v_pk_min_num_f16 v0, v0, v16
; GFX1251-NEXT: v_pk_min_num_f16 v1, v1, v17
; GFX1251-NEXT: v_pk_min_num_f16 v2, v2, v18
@@ -11548,9 +10810,7 @@ define <32 x half> @v_minimumnum_v32f16_no_ieee(<32 x half> %x, <32 x half> %y)
; GFX1251-NEXT: v_pk_min_num_f16 v13, v13, v29
; GFX1251-NEXT: v_pk_min_num_f16 v14, v14, v30
; GFX1251-NEXT: s_wait_loadcnt 0x0
-; GFX1251-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1251-NEXT: v_pk_min_num_f16 v15, v15, v16
+; GFX1251-NEXT: v_pk_min_num_f16 v15, v15, v31
; GFX1251-NEXT: s_set_pc_i64 s[30:31]
%result = call <32 x half> @llvm.minimumnum.v32f16(<32 x half> %x, <32 x half> %y)
ret <32 x half> %result
diff --git a/llvm/test/CodeGen/AMDGPU/minmax.ll b/llvm/test/CodeGen/AMDGPU/minmax.ll
index 93c9e67bda589..c3bf35ae4ed53 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax.ll
@@ -578,8 +578,6 @@ define float @test_minmax_f32_ieee_true(float %a, float %b, float %c) {
; SDAG-GFX1170-LABEL: test_minmax_f32_ieee_true:
; SDAG-GFX1170: ; %bb.0:
; SDAG-GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1170-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; SDAG-GFX1170-NEXT: v_max_num_f32_e32 v2, v2, v2
; SDAG-GFX1170-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
; SDAG-GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -598,8 +596,6 @@ define float @test_minmax_f32_ieee_true(float %a, float %b, float %c) {
; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; SDAG-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
; SDAG-GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -619,8 +615,6 @@ define float @test_minmax_f32_ieee_true(float %a, float %b, float %c) {
; SDAG-GFX1250: ; %bb.0:
; SDAG-GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1250-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX1250-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; SDAG-GFX1250-NEXT: v_max_num_f32_e32 v2, v2, v2
; SDAG-GFX1250-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
; SDAG-GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
@@ -778,8 +772,6 @@ define float @test_maxmin_f32_ieee_true(float %a, float %b, float %c) {
; SDAG-GFX1170-LABEL: test_maxmin_f32_ieee_true:
; SDAG-GFX1170: ; %bb.0:
; SDAG-GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1170-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; SDAG-GFX1170-NEXT: v_max_num_f32_e32 v2, v2, v2
; SDAG-GFX1170-NEXT: v_minmax_num_f32 v0, v0, v1, v2
; SDAG-GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -798,8 +790,6 @@ define float @test_maxmin_f32_ieee_true(float %a, float %b, float %c) {
; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; SDAG-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
; SDAG-GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2
; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -819,8 +809,6 @@ define float @test_maxmin_f32_ieee_true(float %a, float %b, float %c) {
; SDAG-GFX1250: ; %bb.0:
; SDAG-GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1250-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX1250-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; SDAG-GFX1250-NEXT: v_max_num_f32_e32 v2, v2, v2
; SDAG-GFX1250-NEXT: v_minmax_num_f32 v0, v0, v1, v2
; SDAG-GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
@@ -1272,18 +1260,12 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX1170-TRUE16-LABEL: test_minmax_commuted_f16_ieee_true:
; SDAG-GFX1170-TRUE16: ; %bb.0:
; SDAG-GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; SDAG-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; SDAG-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; SDAG-GFX1170-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
+; SDAG-GFX1170-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1170-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
; SDAG-GFX1170-FAKE16: ; %bb.0:
; SDAG-GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; SDAG-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; SDAG-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; SDAG-GFX1170-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; SDAG-GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1312,10 +1294,7 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; SDAG-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
+; SDAG-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX12-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
@@ -1325,9 +1304,6 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; SDAG-GFX12-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; SDAG-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1361,19 +1337,13 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX1250-TRUE16: ; %bb.0:
; SDAG-GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; SDAG-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; SDAG-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; SDAG-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
+; SDAG-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; SDAG-GFX1250-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
; SDAG-GFX1250-FAKE16: ; %bb.0:
; SDAG-GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; SDAG-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; SDAG-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; SDAG-GFX1250-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; SDAG-GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -1542,18 +1512,12 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX1170-TRUE16-LABEL: test_maxmin_commuted_f16_ieee_true:
; SDAG-GFX1170-TRUE16: ; %bb.0:
; SDAG-GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; SDAG-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; SDAG-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; SDAG-GFX1170-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
+; SDAG-GFX1170-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1170-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
; SDAG-GFX1170-FAKE16: ; %bb.0:
; SDAG-GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; SDAG-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; SDAG-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; SDAG-GFX1170-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; SDAG-GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1582,10 +1546,7 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; SDAG-GFX12-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
+; SDAG-GFX12-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX12-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
@@ -1595,9 +1556,6 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; SDAG-GFX12-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; SDAG-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1631,19 +1589,13 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX1250-TRUE16: ; %bb.0:
; SDAG-GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; SDAG-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; SDAG-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; SDAG-GFX1250-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
+; SDAG-GFX1250-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; SDAG-GFX1250-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
; SDAG-GFX1250-FAKE16: ; %bb.0:
; SDAG-GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; SDAG-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; SDAG-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; SDAG-GFX1250-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; SDAG-GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll b/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
index 2658847d1ca1b..3915e7c040e7d 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
@@ -22,9 +22,8 @@ define float @v_max3_maxnum_tree4_f32(float %a, float %b, float %c, float %d) {
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_max3_num_f32 v0, v0, v1, v2
-; GFX1250-NEXT: v_max_num_f32_e32 v1, v3, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1250-NEXT: v_max_num_f32_e32 v0, v0, v3
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%max.ab = call float @llvm.maxnum.f32(float %a, float %b)
%max.cd = call float @llvm.maxnum.f32(float %c, float %d)
@@ -50,10 +49,9 @@ define float @v_max3_maxnum_tree8_f32(float %a, float %b, float %c, float %d,
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX1250-NEXT: v_max3_num_f32 v1, v4, v5, v6
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_max3_num_f32 v0, v0, v3, v1
-; GFX1250-NEXT: v_max_num_f32_e32 v1, v7, v7
-; GFX1250-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1250-NEXT: v_max_num_f32_e32 v0, v0, v7
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
float %e, float %f, float %g, float %h) {
%ab = call float @llvm.maxnum.f32(float %a, float %b)
@@ -193,9 +191,8 @@ define float @v_min3_minnum_tree4_f32(float %a, float %b, float %c, float %d) {
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_min3_num_f32 v0, v0, v1, v2
-; GFX1250-NEXT: v_max_num_f32_e32 v1, v3, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1250-NEXT: v_min_num_f32_e32 v0, v0, v3
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%min.ab = call float @llvm.minnum.f32(float %a, float %b)
%min.cd = call float @llvm.minnum.f32(float %c, float %d)
@@ -345,9 +342,8 @@ define float @v_max3_maxnum_tree4_multi_use(float %a, float %b, float %c, float
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v2, v2, v2
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_max_num_f32_e32 v2, v2, v3
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX1250-NEXT: global_store_b32 v[4:5], v2, off
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
@@ -431,9 +427,8 @@ define half @v_max3_maxnum_tree4_f16(half %a, half %b, half %c, half %d) {
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_max3_num_f16 v0, v0, v1, v2
-; GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v1, v3, v3
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v3
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-REAL16-LABEL: v_max3_maxnum_tree4_f16:
@@ -441,9 +436,8 @@ define half @v_max3_maxnum_tree4_f16(half %a, half %b, half %c, half %d) {
; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v2.l
-; GFX1250-REAL16-NEXT: v_max_num_f16_e32 v0.h, v3.l, v3.l
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-REAL16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1250-REAL16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v3.l
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%max.ab = call half @llvm.maxnum.f16(half %a, half %b)
%max.cd = call half @llvm.maxnum.f16(half %c, half %d)
@@ -469,11 +463,6 @@ define double @v_no_max3_maxnum_tree4_f64(double %a, double %b, double %c, doubl
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1250-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX1250-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[6:7]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -665,11 +654,9 @@ define <2 x float> @v_max3_maxnum_tree4_v2f32(<2 x float> %a, <2 x float> %b, <2
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_max3_num_f32 v0, v0, v2, v4
-; GFX1250-NEXT: v_max_num_f32_e32 v2, v6, v6
; GFX1250-NEXT: v_max3_num_f32 v1, v1, v3, v5
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_dual_max_num_f32 v3, v7, v7 :: v_dual_max_num_f32 v0, v0, v2
-; GFX1250-NEXT: v_max_num_f32_e32 v1, v1, v3
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_dual_max_num_f32 v0, v0, v6 :: v_dual_max_num_f32 v1, v1, v7
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%max.ab = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b)
%max.cd = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %c, <2 x float> %d)
@@ -739,9 +726,8 @@ define <2 x half> @v_max3_maxnum_tree4_v2f16(<2 x half> %a, <2 x half> %b, <2 x
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_pk_max3_num_f16 v0, v0, v1, v2
-; GFX1250-NEXT: v_pk_max_num_f16 v1, v3, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX1250-NEXT: v_pk_max_num_f16 v0, v0, v3
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%max.ab = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
%max.cd = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %c, <2 x half> %d)
diff --git a/llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll b/llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
index 158a45c3d5849..9ff0714564fc3 100644
--- a/llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
@@ -317,13 +317,8 @@ define <4 x half> @fminnum_v4f16_neg(<4 x half> %first, <4 x half> %second) {
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-LABEL: fminnum_v4f16_neg:
@@ -384,19 +379,10 @@ define <8 x half> @fminnum_v8f16_neg(<8 x half> %first, <8 x half> %second) {
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v4
-; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v5
-; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v2, v2, v6
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v3, v3, v7
+; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v4 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v5 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v2, v2, v6 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v3, v3, v7 neg_lo:[0,1] neg_hi:[0,1]
; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-LABEL: fminnum_v8f16_neg:
@@ -451,13 +437,8 @@ define <4 x half> @fmaxnum_v4f16_neg(<4 x half> %first, <4 x half> %second) {
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v3
+; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-LABEL: fmaxnum_v4f16_neg:
@@ -518,19 +499,10 @@ define <8 x half> @fmaxnum_v8f16_neg(<8 x half> %first, <8 x half> %second) {
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v4
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v5
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v6
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v7
+; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v4 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v5 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v6 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v7 neg_lo:[0,1] neg_hi:[0,1]
; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-LABEL: fmaxnum_v8f16_neg:
diff --git a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
index e3a43047014af..c2b7761d9eb8d 100644
--- a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
@@ -3128,8 +3128,6 @@ define float @v_test_fmin_legacy_ole_f32_const_rhs(float %a) {
; GFX1170-LABEL: v_test_fmin_legacy_ole_f32_const_rhs:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f32_e32 v0, 2.0, v0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -3140,8 +3138,6 @@ define float @v_test_fmin_legacy_ole_f32_const_rhs(float %a) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v0, 2.0, v0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ole float %a, 2.0
@@ -3241,8 +3237,6 @@ define float @v_test_fmax_legacy_ogt_f32_const_rhs(float %a) {
; GFX1170-LABEL: v_test_fmax_legacy_ogt_f32_const_rhs:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_max_num_f32_e32 v0, 2.0, v0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -3253,8 +3247,6 @@ define float @v_test_fmax_legacy_ogt_f32_const_rhs(float %a) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f32_e32 v0, 2.0, v0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ogt float %a, 2.0
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
index c19c285454a4c..9723357a39562 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
@@ -132,19 +132,15 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v2half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -175,10 +171,8 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v2half:
@@ -189,9 +183,7 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -353,8 +345,6 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0xfe00
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
@@ -365,10 +355,9 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_pack_b32_f16 v1, v1, 0xfe00
+; GFX1170-SDAG-FAKE16-NEXT: s_mov_b32 s0, 0xfe00
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
@@ -404,8 +393,6 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0xfe00
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
@@ -420,13 +407,13 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_pack_b32_f16 v1, v1, 0xfe00
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_mov_b32 s0, 0xfe00
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -622,24 +609,18 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v4half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -677,12 +658,9 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -693,12 +671,9 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1001,11 +976,6 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v8half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1018,11 +988,6 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1083,11 +1048,6 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1104,11 +1064,6 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1632,57 +1587,35 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v8.l, v8.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v8.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v2.l, v9.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v3.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v4.l, v2.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v5.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v6.l, v2.l
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v3, v3, v7
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v5
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v2, v2, v6
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v4
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v3
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v2
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v7.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v8
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v1, v9
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v2, v8
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v3, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v4, v2
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v5, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v6, v2
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v3, v3, v7
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v5
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v2, v2, v6
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v4
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v3
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v2
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v7, v1
+; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
@@ -1766,29 +1699,18 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v8.l, v8.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v8.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v2.l, v9.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v3.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v4.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v5.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v6.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v5
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v7.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
@@ -1798,29 +1720,18 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v8
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v1, v9
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v2, v8
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v3, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v4, v2
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v5, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v6, v2
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v7, v1
+; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
@@ -1993,8 +1904,6 @@ define float @test_vector_reduce_fmax_v2float(<2 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v2float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2013,8 +1922,6 @@ define float @test_vector_reduce_fmax_v2float(<2 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2255,9 +2162,8 @@ define float @test_vector_reduce_fmax_v4float(<4 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v4float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2278,9 +2184,8 @@ define float @test_vector_reduce_fmax_v4float(<4 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2450,12 +2355,11 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v8float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v4, v5
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v6, v7
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2482,12 +2386,11 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v4, v5
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v6, v7
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2747,18 +2650,17 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v16float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v4, v5
-; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v6, v7
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v6, v7
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v8, v9
-; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v10, v11
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v10, v11
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v12, v13
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v14, v15
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2795,18 +2697,17 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v4, v5
-; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v6, v7
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v6, v7
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v8, v9
-; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v10, v11
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v10, v11
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v12, v13
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v14, v15
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2931,9 +2832,6 @@ define double @test_vector_reduce_fmax_v2double(<2 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v2double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2953,9 +2851,6 @@ define double @test_vector_reduce_fmax_v2double(<2 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3082,11 +2977,8 @@ define double @test_vector_reduce_fmax_v3double(<3 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v3double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3108,11 +3000,8 @@ define double @test_vector_reduce_fmax_v3double(<3 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3263,15 +3152,10 @@ define double @test_vector_reduce_fmax_v4double(<4 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v4double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[6:7], v[6:7]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[6:7]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v4double:
@@ -3295,15 +3179,10 @@ define double @test_vector_reduce_fmax_v4double(<4 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[6:7], v[6:7]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v4double:
@@ -3538,25 +3417,16 @@ define double @test_vector_reduce_fmax_v8double(<8 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v8double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[8:9], v[8:9]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[10:11], v[10:11]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[12:13], v[12:13]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[14:15], v[14:15]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[6:7]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[10:11]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[12:13]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[14:15]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v8double:
@@ -3588,25 +3458,16 @@ define double @test_vector_reduce_fmax_v8double(<8 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[8:9], v[8:9]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[10:11], v[10:11]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[12:13], v[12:13]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[14:15], v[14:15]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[8:9]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[10:11]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[12:13]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[14:15]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v8double:
@@ -4033,46 +3894,30 @@ define double @test_vector_reduce_fmax_v16double(<16 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v16double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[8:9], v[8:9]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[10:11], v[10:11]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[12:13], v[12:13]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[14:15], v[14:15]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[16:17], v[16:17]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[18:19], v[18:19]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[20:21], v[20:21]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[22:23], v[22:23]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[24:25], v[24:25]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[26:27], v[26:27]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[28:29], v[28:29]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[6:7]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[10:11]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[12:13]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[14:15]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[16:17]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[18:19]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[20:21]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[22:23]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[24:25]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[26:27]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[28:29]
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[30:31], v[30:31]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[30:31]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v16double:
@@ -4123,46 +3968,30 @@ define double @test_vector_reduce_fmax_v16double(<16 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[8:9], v[8:9]
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[10:11], v[10:11]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[12:13], v[12:13]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[14:15], v[14:15]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[16:17], v[16:17]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[18:19], v[18:19]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[20:21], v[20:21]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[22:23], v[22:23]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[24:25], v[24:25]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[26:27], v[26:27]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[28:29], v[28:29]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[8:9]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[10:11]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[12:13]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[14:15]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[16:17]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[18:19]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[20:21]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[22:23]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[24:25]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[26:27]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[28:29]
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[30:31], v[30:31]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[30:31]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v16double:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
index b3c0ed6470fa5..61e0c52c62e3e 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
@@ -132,19 +132,15 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v2half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -175,10 +171,8 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v2half:
@@ -189,9 +183,7 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -353,8 +345,6 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7e00
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
@@ -365,10 +355,9 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_pack_b32_f16 v1, v1, 0x7e00
+; GFX1170-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x7e00
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
@@ -404,8 +393,6 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7e00
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
@@ -420,13 +407,13 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_pack_b32_f16 v1, v1, 0x7e00
-; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x7e00
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -622,24 +609,18 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v4half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -677,12 +658,9 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -693,12 +671,9 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1001,11 +976,6 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v8half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1018,11 +988,6 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1083,11 +1048,6 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1104,11 +1064,6 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1632,57 +1587,35 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v8.l, v8.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v8.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v2.l, v9.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v3.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v4.l, v2.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v5.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v6.l, v2.l
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v3, v3, v7
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v1, v1, v5
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v2, v2, v6
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v4
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v7.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
-; GFX1170-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v8
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v1, v9
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v2, v8
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v3, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v4, v2
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v5, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v6, v2
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v3, v3, v7
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v1, v1, v5
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v2, v2, v6
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v4
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v7, v1
+; GFX1170-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
@@ -1766,29 +1699,18 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v8.l, v8.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v8.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v2.l, v9.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v3.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v4.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v5.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v6.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v1, v1, v5
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v7.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
@@ -1798,29 +1720,18 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
-; GFX12-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v8
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v1, v9
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v2, v8
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v3, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v4, v2
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v5, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v6, v2
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v7, v1
+; GFX12-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
@@ -1993,8 +1904,6 @@ define float @test_vector_reduce_fmin_v2float(<2 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v2float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2013,8 +1922,6 @@ define float @test_vector_reduce_fmin_v2float(<2 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2255,9 +2162,8 @@ define float @test_vector_reduce_fmin_v4float(<4 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v4float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2278,9 +2184,8 @@ define float @test_vector_reduce_fmin_v4float(<4 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2450,12 +2355,11 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v8float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v4, v5
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v6, v7
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2482,12 +2386,11 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v4, v5
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v6, v7
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2747,18 +2650,17 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v16float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v4, v5
-; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v6, v7
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v6, v7
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v8, v9
-; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v10, v11
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v10, v11
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v12, v13
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v14, v15
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2795,18 +2697,17 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v4, v5
-; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v6, v7
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v6, v7
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v8, v9
-; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v10, v11
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v10, v11
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v12, v13
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v14, v15
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2930,9 +2831,6 @@ define double @test_vector_reduce_fmin_v2double(<2 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v2double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2952,9 +2850,6 @@ define double @test_vector_reduce_fmin_v2double(<2 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3081,11 +2976,8 @@ define double @test_vector_reduce_fmin_v3double(<3 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v3double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3107,11 +2999,8 @@ define double @test_vector_reduce_fmin_v3double(<3 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3262,15 +3151,10 @@ define double @test_vector_reduce_fmin_v4double(<4 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v4double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[6:7], v[6:7]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[6:7]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v4double:
@@ -3294,15 +3178,10 @@ define double @test_vector_reduce_fmin_v4double(<4 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[6:7], v[6:7]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v4double:
@@ -3537,25 +3416,16 @@ define double @test_vector_reduce_fmin_v8double(<8 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v8double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[8:9], v[8:9]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[10:11], v[10:11]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[12:13], v[12:13]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[14:15], v[14:15]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[6:7]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[10:11]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[12:13]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[14:15]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v8double:
@@ -3587,25 +3457,16 @@ define double @test_vector_reduce_fmin_v8double(<8 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[8:9], v[8:9]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[10:11], v[10:11]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[12:13], v[12:13]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[14:15], v[14:15]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[8:9]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[10:11]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[12:13]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[14:15]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v8double:
@@ -4032,46 +3893,30 @@ define double @test_vector_reduce_fmin_v16double(<16 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v16double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[8:9], v[8:9]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[10:11], v[10:11]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[12:13], v[12:13]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[14:15], v[14:15]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[16:17], v[16:17]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[18:19], v[18:19]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[20:21], v[20:21]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[22:23], v[22:23]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[24:25], v[24:25]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[26:27], v[26:27]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[28:29], v[28:29]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[6:7]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[10:11]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[12:13]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[14:15]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[16:17]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[18:19]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[20:21]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[22:23]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[24:25]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[26:27]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[28:29]
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[30:31], v[30:31]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[30:31]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v16double:
@@ -4122,46 +3967,30 @@ define double @test_vector_reduce_fmin_v16double(<16 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[8:9], v[8:9]
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[10:11], v[10:11]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[12:13], v[12:13]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[14:15], v[14:15]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[16:17], v[16:17]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[18:19], v[18:19]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[20:21], v[20:21]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[22:23], v[22:23]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[24:25], v[24:25]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[26:27], v[26:27]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[28:29], v[28:29]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[8:9]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[10:11]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[12:13]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[14:15]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[16:17]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[18:19]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[20:21]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[22:23]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[24:25]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[26:27]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[28:29]
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[30:31], v[30:31]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[30:31]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v16double:
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