[llvm] [AArch64] Allow SME peephole opts without +sme in streaming compat functions (PR #222728)
Benjamin Maxwell via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 11 03:06:41 PDT 2026
https://github.com/MacDue updated https://github.com/llvm/llvm-project/pull/222728
>From 59d62469b45d370b5a5e6f1c8218ca52749c7462 Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: Thu, 10 Sep 2026 17:50:34 +0000
Subject: [PATCH 1/4] Precommit test
---
.../AArch64/sme-peephole-opt-sm-compat.ll | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll
diff --git a/llvm/test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll b/llvm/test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll
new file mode 100644
index 0000000000000..227d5a869cdb9
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64-linux-gnu -aarch64-streaming-hazard-size=0 -mattr=+sve < %s | FileCheck %s
+
+declare void @callee()
+
+; streaming-compatible caller -> normal callees
+define void @test0() nounwind "aarch64_pstate_sm_compatible" {
+; CHECK-LABEL: test0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill
+; CHECK-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
+; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-NEXT: bl __arm_sme_state
+; CHECK-NEXT: mov x19, x0
+; CHECK-NEXT: tbz w19, #0, .LBB0_2
+; CHECK-NEXT: // %bb.1:
+; CHECK-NEXT: smstop sm
+; CHECK-NEXT: .LBB0_2:
+; CHECK-NEXT: bl callee
+; CHECK-NEXT: tbz w19, #0, .LBB0_4
+; CHECK-NEXT: // %bb.3:
+; CHECK-NEXT: smstart sm
+; CHECK-NEXT: .LBB0_4:
+; CHECK-NEXT: tbz w19, #0, .LBB0_6
+; CHECK-NEXT: // %bb.5:
+; CHECK-NEXT: smstop sm
+; CHECK-NEXT: .LBB0_6:
+; CHECK-NEXT: bl callee
+; CHECK-NEXT: tbz w19, #0, .LBB0_8
+; CHECK-NEXT: // %bb.7:
+; CHECK-NEXT: smstart sm
+; CHECK-NEXT: .LBB0_8:
+; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldp d15, d14, [sp], #80 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+ call void @callee()
+ call void @callee()
+ ret void
+}
>From 38c42af02fb47b214ec10121e4c7be504e6207e8 Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: Thu, 10 Sep 2026 17:51:54 +0000
Subject: [PATCH 2/4] [AArch64] Allow SME peephole opts without +sme in
streaming compat functions
---
llvm/lib/Target/AArch64/SMEPeepholeOpt.cpp | 7 +++++--
.../test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll | 10 +---------
2 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/AArch64/SMEPeepholeOpt.cpp b/llvm/lib/Target/AArch64/SMEPeepholeOpt.cpp
index 720e7c8b05d90..8e617e64ff230 100644
--- a/llvm/lib/Target/AArch64/SMEPeepholeOpt.cpp
+++ b/llvm/lib/Target/AArch64/SMEPeepholeOpt.cpp
@@ -293,7 +293,11 @@ bool SMEPeepholeOpt::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
- if (!MF.getSubtarget<AArch64Subtarget>().hasSME())
+ AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
+ SMEAttrs SMEFnAttrs = AFI->getSMEFnAttrs();
+
+ if (!MF.getSubtarget<AArch64Subtarget>().hasSME() &&
+ !SMEFnAttrs.hasStreamingCompatibleInterface())
return false;
assert(MF.getRegInfo().isSSA() && "Expected to be run on SSA form!");
@@ -316,7 +320,6 @@ bool SMEPeepholeOpt::runOnMachineFunction(MachineFunction &MF) {
}
}
- AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
if (FunctionHasAllSMChangesRemoved)
AFI->setHasStreamingModeChanges(false);
diff --git a/llvm/test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll b/llvm/test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll
index 227d5a869cdb9..5dfc232448a5e 100644
--- a/llvm/test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll
+++ b/llvm/test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll
@@ -19,19 +19,11 @@ define void @test0() nounwind "aarch64_pstate_sm_compatible" {
; CHECK-NEXT: smstop sm
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: bl callee
+; CHECK-NEXT: bl callee
; CHECK-NEXT: tbz w19, #0, .LBB0_4
; CHECK-NEXT: // %bb.3:
; CHECK-NEXT: smstart sm
; CHECK-NEXT: .LBB0_4:
-; CHECK-NEXT: tbz w19, #0, .LBB0_6
-; CHECK-NEXT: // %bb.5:
-; CHECK-NEXT: smstop sm
-; CHECK-NEXT: .LBB0_6:
-; CHECK-NEXT: bl callee
-; CHECK-NEXT: tbz w19, #0, .LBB0_8
-; CHECK-NEXT: // %bb.7:
-; CHECK-NEXT: smstart sm
-; CHECK-NEXT: .LBB0_8:
; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
>From 10b07c7815f33a0b0f2e5346ae0d3cfb4be58251 Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: Thu, 10 Sep 2026 19:26:34 +0000
Subject: [PATCH 3/4] Fixups
---
llvm/test/CodeGen/AArch64/stack-hazard.ll | 38 +++++------------------
1 file changed, 7 insertions(+), 31 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/stack-hazard.ll b/llvm/test/CodeGen/AArch64/stack-hazard.ll
index 8a43720faf2a5..604e51799595d 100644
--- a/llvm/test/CodeGen/AArch64/stack-hazard.ll
+++ b/llvm/test/CodeGen/AArch64/stack-hazard.ll
@@ -1737,21 +1737,13 @@ define i32 @f128_libcall(fp128 %v0, fp128 %v1, fp128 %v2, fp128 %v3, i32 %a, i32
; CHECK0-NEXT: .LBB27_2:
; CHECK0-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK0-NEXT: bl __lttf2
+; CHECK0-NEXT: ldp q0, q1, [sp, #32] // 32-byte Folded Reload
; CHECK0-NEXT: mov w22, w0
+; CHECK0-NEXT: bl __getf2
; CHECK0-NEXT: tbz w21, #0, .LBB27_4
; CHECK0-NEXT: // %bb.3:
; CHECK0-NEXT: smstart sm
; CHECK0-NEXT: .LBB27_4:
-; CHECK0-NEXT: tbz w21, #0, .LBB27_6
-; CHECK0-NEXT: // %bb.5:
-; CHECK0-NEXT: smstop sm
-; CHECK0-NEXT: .LBB27_6:
-; CHECK0-NEXT: ldp q0, q1, [sp, #32] // 32-byte Folded Reload
-; CHECK0-NEXT: bl __getf2
-; CHECK0-NEXT: tbz w21, #0, .LBB27_8
-; CHECK0-NEXT: // %bb.7:
-; CHECK0-NEXT: smstart sm
-; CHECK0-NEXT: .LBB27_8:
; CHECK0-NEXT: cmp w0, #0
; CHECK0-NEXT: ldp x29, x30, [sp, #128] // 16-byte Folded Reload
; CHECK0-NEXT: ccmp w22, #0, #0, pl
@@ -1822,21 +1814,13 @@ define i32 @f128_libcall(fp128 %v0, fp128 %v1, fp128 %v2, fp128 %v3, i32 %a, i32
; CHECK64-NEXT: .LBB27_2:
; CHECK64-NEXT: ldp q0, q1, [sp, #64] // 32-byte Folded Reload
; CHECK64-NEXT: bl __lttf2
+; CHECK64-NEXT: ldp q0, q1, [sp, #96] // 32-byte Folded Reload
; CHECK64-NEXT: mov w22, w0
+; CHECK64-NEXT: bl __getf2
; CHECK64-NEXT: tbz w21, #0, .LBB27_4
; CHECK64-NEXT: // %bb.3:
; CHECK64-NEXT: smstart sm
; CHECK64-NEXT: .LBB27_4:
-; CHECK64-NEXT: tbz w21, #0, .LBB27_6
-; CHECK64-NEXT: // %bb.5:
-; CHECK64-NEXT: smstop sm
-; CHECK64-NEXT: .LBB27_6:
-; CHECK64-NEXT: ldp q0, q1, [sp, #96] // 32-byte Folded Reload
-; CHECK64-NEXT: bl __getf2
-; CHECK64-NEXT: tbz w21, #0, .LBB27_8
-; CHECK64-NEXT: // %bb.7:
-; CHECK64-NEXT: smstart sm
-; CHECK64-NEXT: .LBB27_8:
; CHECK64-NEXT: cmp w0, #0
; CHECK64-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload
; CHECK64-NEXT: ccmp w22, #0, #0, pl
@@ -1918,22 +1902,14 @@ define i32 @f128_libcall(fp128 %v0, fp128 %v1, fp128 %v2, fp128 %v3, i32 %a, i32
; CHECK1024-NEXT: ldr q0, [sp, #1024] // 16-byte Reload
; CHECK1024-NEXT: ldr q1, [sp, #1040] // 16-byte Reload
; CHECK1024-NEXT: bl __lttf2
+; CHECK1024-NEXT: ldr q0, [sp, #1056] // 16-byte Reload
+; CHECK1024-NEXT: ldr q1, [sp, #1072] // 16-byte Reload
; CHECK1024-NEXT: mov w22, w0
+; CHECK1024-NEXT: bl __getf2
; CHECK1024-NEXT: tbz w21, #0, .LBB27_4
; CHECK1024-NEXT: // %bb.3:
; CHECK1024-NEXT: smstart sm
; CHECK1024-NEXT: .LBB27_4:
-; CHECK1024-NEXT: tbz w21, #0, .LBB27_6
-; CHECK1024-NEXT: // %bb.5:
-; CHECK1024-NEXT: smstop sm
-; CHECK1024-NEXT: .LBB27_6:
-; CHECK1024-NEXT: ldr q0, [sp, #1056] // 16-byte Reload
-; CHECK1024-NEXT: ldr q1, [sp, #1072] // 16-byte Reload
-; CHECK1024-NEXT: bl __getf2
-; CHECK1024-NEXT: tbz w21, #0, .LBB27_8
-; CHECK1024-NEXT: // %bb.7:
-; CHECK1024-NEXT: smstart sm
-; CHECK1024-NEXT: .LBB27_8:
; CHECK1024-NEXT: cmp w0, #0
; CHECK1024-NEXT: ccmp w22, #0, #0, pl
; CHECK1024-NEXT: csel w0, w20, w19, mi
>From 313e22b03bbe724d08e2ef3eadaf0de43a26afac Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: Fri, 11 Sep 2026 10:05:52 +0000
Subject: [PATCH 4/4] Fixups
---
llvm/test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll b/llvm/test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll
index 5dfc232448a5e..20fd021807a23 100644
--- a/llvm/test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll
+++ b/llvm/test/CodeGen/AArch64/sme-peephole-opt-sm-compat.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=aarch64-linux-gnu -aarch64-streaming-hazard-size=0 -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s
declare void @callee()
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