[llvm] [AMDGPU][NFC] Refactor integer to float lowering (PR #222898)

[Harrison Hao via llvm-commits]

https://github.com/harrisonGPU created https://github.com/llvm/llvm-project/pull/222898

Factor common code out of LowerUINT_TO_FP and LowerSINT_TO_FP.

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>From 2f7ddd10ad0b7460736b8fc95d4e8828fcff8291 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Fri, 11 Sep 2026 16:32:38 +0800
Subject: [PATCH] [AMDGPU][NFC] Refactor integer to float lowering

Factor common code out of LowerUINT_TO_FP and LowerSINT_TO_FP.
---
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 52 ++++++-------------
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h   |  1 +
 2 files changed, 16 insertions(+), 37 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index b01799a8194e0..cefbf02095521 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -3657,21 +3657,21 @@ SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
   return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
 }
 
-SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
-                                               SelectionDAG &DAG) const {
-  // TODO: Factor out code common with LowerSINT_TO_FP.
+SDValue AMDGPUTargetLowering::lowerINT_TO_FPImpl(SDValue Op, SelectionDAG &DAG,
+                                             bool Signed) const {
   EVT DestVT = Op.getValueType();
   SDValue Src = Op.getOperand(0);
   EVT SrcVT = Src.getValueType();
+  unsigned ExtOpc = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
+  unsigned CvtOpc = Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
 
   if (SrcVT == MVT::i16) {
     if (DestVT == MVT::f16)
       return Op;
-    SDLoc DL(Op);
 
-    // Promote src to i32
-    SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Src);
-    return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext);
+    SDLoc DL(Op);
+    SDValue Ext = DAG.getNode(ExtOpc, DL, MVT::i32, Src);
+    return DAG.getNode(CvtOpc, DL, DestVT, Ext);
   }
 
   if (DestVT == MVT::bf16 || DestVT == MVT::f16)
@@ -3681,42 +3681,20 @@ SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
     return Op;
 
   if (DestVT == MVT::f32)
-    return LowerINT_TO_FP32(Op, DAG, false);
+    return LowerINT_TO_FP32(Op, DAG, Signed);
 
   assert(DestVT == MVT::f64);
-  return LowerINT_TO_FP64(Op, DAG, false);
+  return LowerINT_TO_FP64(Op, DAG, Signed);
 }
 
-SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
+SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
                                               SelectionDAG &DAG) const {
-  EVT DestVT = Op.getValueType();
-
-  SDValue Src = Op.getOperand(0);
-  EVT SrcVT = Src.getValueType();
-
-  if (SrcVT == MVT::i16) {
-    if (DestVT == MVT::f16)
-      return Op;
-
-    SDLoc DL(Op);
-    // Promote src to i32
-    SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, Src);
-    return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext);
-  }
-
-  if (DestVT == MVT::bf16 || DestVT == MVT::f16)
-    return LowerINT_TO_FP16(Op, DAG, DestVT);
-
-  if (SrcVT != MVT::i64)
-    return Op;
-
-  // TODO: Factor out code common with LowerUINT_TO_FP.
-
-  if (DestVT == MVT::f32)
-    return LowerINT_TO_FP32(Op, DAG, true);
+  return lowerINT_TO_FPImpl(Op, DAG, false);
+}
 
-  assert(DestVT == MVT::f64);
-  return LowerINT_TO_FP64(Op, DAG, true);
+SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
+                                              SelectionDAG &DAG) const {
+  return lowerINT_TO_FPImpl(Op, DAG, true);
 }
 
 SDValue AMDGPUTargetLowering::LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 9316f83fac06e..a7696d89515c4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -96,6 +96,7 @@ class AMDGPUTargetLowering : public TargetLowering {
   SDValue LowerINT_TO_FP16(SDValue Op, SelectionDAG &DAG, EVT FP16Ty) const;
   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
+  SDValue lowerINT_TO_FPImpl(SDValue Op, SelectionDAG &DAG, bool Signed) const;
   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;