[llvm] [LV] Trim VFs that cause vector splitting when tail-folding with EVL (PR #222836)

[Luke Lau via llvm-commits]

lukel97 wrote:

> IIUC enabling max-bandwidth make LV calculate the `MaxVF` by the smallest type in the loop (w/o max-bandwidth is calculated by WidestType).
> 
> For the mix-width loops without cast instruction will not catch by #221913.

Ah right, so when we have two separate chains of types there might not be cast. In that case would it be sufficient then to also apply the same invalid cost for loads + stores if they need split?

My main concern with the VPlan pass approach is that this a detail of the RISC-V VL optimizer leaking upwards. For example we're hard-coding the maximum number of registers as 8 before it needs split.

I don't think returning an invalid cost is perfect either since that will also affect vectorcombine/slp costs. Maybe a better approach is to adjust the logic in `VFSelectionContext::getMaximizedVFForTarget` and use a new TTI hook to limit the maximum number of registers allowed for the widest type. 

https://github.com/llvm/llvm-project/pull/222836