[llvm] 75ca063 - [AMDGPU][GIsel][NPM] Port AMDGPUPostLegalizerCombiner to NPM (#216274)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 10 23:20:43 PDT 2026
Author: Keshav Vinayak Jha
Date: 2026-09-11T11:50:37+05:30
New Revision: 75ca063b3b303e499a798ef84d04d32fb96d44c8
URL: https://github.com/llvm/llvm-project/commit/75ca063b3b303e499a798ef84d04d32fb96d44c8
DIFF: https://github.com/llvm/llvm-project/commit/75ca063b3b303e499a798ef84d04d32fb96d44c8.diff
LOG: [AMDGPU][GIsel][NPM] Port AMDGPUPostLegalizerCombiner to NPM (#216274)
Porting `AMDGPUPostLegalizerCombiner` to work with the New PassManager
to support GISel.
Assisted-by: Codex
---------
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPU.h
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fdiv-sqrt-to-rsq.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 86afda9e4bf49..199231e7eea89 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -34,8 +34,17 @@ class AMDGPUPreLegalizerCombinerPass
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
};
-void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
-FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
+
+void initializeAMDGPUPostLegalizerCombinerLegacyPass(PassRegistry &);
+FunctionPass *createAMDGPUPostLegalizeCombinerLegacy(bool IsOptNone);
+
+class AMDGPUPostLegalizerCombinerPass
+ : public RequiredPassInfoMixin<AMDGPUPostLegalizerCombinerPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
FunctionPass *createAMDGPURegBankCombinerLegacy(bool IsOptLevelNone);
void initializeAMDGPURegBankCombinerLegacyPass(PassRegistry &);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 546a864863991..29e9046e4f8ca 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -122,6 +122,8 @@ MACHINE_FUNCTION_PASS("amdgpu-insert-delay-alu", AMDGPUInsertDelayAluPass())
MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this))
MACHINE_FUNCTION_PASS("amdgpu-lower-vgpr-encoding", AMDGPULowerVGPREncodingPass())
MACHINE_FUNCTION_PASS("amdgpu-mark-last-scratch-load", AMDGPUMarkLastScratchLoadPass())
+MACHINE_FUNCTION_PASS("amdgpu-postlegalizer-combiner",
+ AMDGPUPostLegalizerCombinerPass())
MACHINE_FUNCTION_PASS("amdgpu-pre-ra-long-branch-reg", GCNPreRALongBranchRegPass())
MACHINE_FUNCTION_PASS("amdgpu-reserve-wwm-regs", AMDGPUReserveWWMRegsPass())
MACHINE_FUNCTION_PASS("amdgpu-rewrite-agpr-copy-mfma", AMDGPURewriteAGPRCopyMFMAPass())
@@ -164,9 +166,3 @@ MACHINE_FUNCTION_PASS("si-pre-emit-peephole", SIPreEmitPeepholePass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
MACHINE_FUNCTION_PASS("si-wqm", SIWholeQuadModePass())
#undef MACHINE_FUNCTION_PASS
-
-#define DUMMY_MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
-// Global ISel passes
-DUMMY_MACHINE_FUNCTION_PASS("amdgpu-postlegalizer-combiner",
- AMDGPUPostLegalizerCombinerPass())
-#undef DUMMY_MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
index 32c0fce7c0146..4373cfee6587f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
@@ -15,6 +15,7 @@
#include "AMDGPUCombinerHelper.h"
#include "AMDGPULegalizerInfo.h"
#include "GCNSubtarget.h"
+#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
#include "llvm/CodeGen/GlobalISel/Combiner.h"
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
@@ -23,6 +24,9 @@
#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
+#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Target/TargetMachine.h"
@@ -392,11 +396,33 @@ bool AMDGPUPostLegalizerCombinerImpl::matchCombine_s_mul_u64(
// Pass boilerplate
// ================
-class AMDGPUPostLegalizerCombiner : public MachineFunctionPass {
+static bool
+runCombiner(MachineFunction &MF, GISelValueTracking *VT, GISelCSEInfo *CSEInfo,
+ MachineDominatorTree *MDT,
+ const AMDGPUPostLegalizerCombinerImplRuleConfig &RuleConfig,
+ bool EnableOpt) {
+ const Function &F = MF.getFunction();
+ const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+ const LegalizerInfo *LI = ST.getLegalizerInfo();
+
+ CombinerInfo CInfo(/*AllowIllegalOps=*/false,
+ /*ShouldLegalizeIllegal=*/true, LI, EnableOpt,
+ F.hasOptSize(), F.hasMinSize());
+ // Disable fixed-point iteration to reduce compile-time
+ CInfo.MaxIterations = 1;
+ CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
+ // Legalizer performs DCE, so a full DCE pass is unnecessary.
+ CInfo.EnableFullDCE = false;
+ AMDGPUPostLegalizerCombinerImpl Impl(MF, CInfo, *VT, CSEInfo, RuleConfig, ST,
+ MDT, LI);
+ return Impl.combineMachineInstrs();
+}
+
+class AMDGPUPostLegalizerCombinerLegacy : public MachineFunctionPass {
public:
static char ID;
- AMDGPUPostLegalizerCombiner(bool IsOptNone = false);
+ AMDGPUPostLegalizerCombinerLegacy(bool IsOptNone = false);
StringRef getPassName() const override {
return "AMDGPUPostLegalizerCombiner";
@@ -412,7 +438,8 @@ class AMDGPUPostLegalizerCombiner : public MachineFunctionPass {
};
} // end anonymous namespace
-void AMDGPUPostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
+void AMDGPUPostLegalizerCombinerLegacy::getAnalysisUsage(
+ AnalysisUsage &AU) const {
AU.setPreservesCFG();
getSelectionDAGFallbackAnalysisUsage(AU);
AU.addRequired<GISelValueTrackingAnalysisLegacy>();
@@ -425,56 +452,72 @@ void AMDGPUPostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-AMDGPUPostLegalizerCombiner::AMDGPUPostLegalizerCombiner(bool IsOptNone)
+AMDGPUPostLegalizerCombinerLegacy::AMDGPUPostLegalizerCombinerLegacy(
+ bool IsOptNone)
: MachineFunctionPass(ID), IsOptNone(IsOptNone) {
if (!RuleConfig.parseCommandLineOption())
report_fatal_error("Invalid rule identifier");
}
-bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
+bool AMDGPUPostLegalizerCombinerLegacy::runOnMachineFunction(
+ MachineFunction &MF) {
if (MF.getProperties().hasFailedISel())
return false;
const Function &F = MF.getFunction();
bool EnableOpt =
MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
- const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
- const AMDGPULegalizerInfo *LI =
- static_cast<const AMDGPULegalizerInfo *>(ST.getLegalizerInfo());
-
GISelValueTracking *VT =
&getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
- MachineDominatorTree *MDT =
- IsOptNone ? nullptr
- : &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
-
GISelCSEAnalysisWrapper &Wrapper =
getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
GISelCSEInfo *CSEInfo =
&Wrapper.get(getStandardCSEConfigForOpt(MF.getTarget().getOptLevel()));
+ MachineDominatorTree *MDT =
+ IsOptNone ? nullptr
+ : &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- CombinerInfo CInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
- LI, EnableOpt, F.hasOptSize(), F.hasMinSize());
- // Disable fixed-point iteration to reduce compile-time
- CInfo.MaxIterations = 1;
- CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
- // Legalizer performs DCE, so a full DCE pass is unnecessary.
- CInfo.EnableFullDCE = false;
- AMDGPUPostLegalizerCombinerImpl Impl(MF, CInfo, *VT, CSEInfo, RuleConfig, ST,
- MDT, LI);
- return Impl.combineMachineInstrs();
+ return runCombiner(MF, VT, CSEInfo, MDT, RuleConfig, EnableOpt);
}
-char AMDGPUPostLegalizerCombiner::ID = 0;
-INITIALIZE_PASS_BEGIN(AMDGPUPostLegalizerCombiner, DEBUG_TYPE,
+char AMDGPUPostLegalizerCombinerLegacy::ID = 0;
+INITIALIZE_PASS_BEGIN(AMDGPUPostLegalizerCombinerLegacy, DEBUG_TYPE,
"Combine AMDGPU machine instrs after legalization", false,
false)
INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy)
INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
-INITIALIZE_PASS_END(AMDGPUPostLegalizerCombiner, DEBUG_TYPE,
+INITIALIZE_PASS_END(AMDGPUPostLegalizerCombinerLegacy, DEBUG_TYPE,
"Combine AMDGPU machine instrs after legalization", false,
false)
-FunctionPass *llvm::createAMDGPUPostLegalizeCombiner(bool IsOptNone) {
- return new AMDGPUPostLegalizerCombiner(IsOptNone);
+FunctionPass *llvm::createAMDGPUPostLegalizeCombinerLegacy(bool IsOptNone) {
+ return new AMDGPUPostLegalizerCombinerLegacy(IsOptNone);
+}
+
+PreservedAnalyses
+AMDGPUPostLegalizerCombinerPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ if (MF.getProperties().hasFailedISel())
+ return PreservedAnalyses::all();
+
+ AMDGPUPostLegalizerCombinerImplRuleConfig RuleConfig;
+ if (!RuleConfig.parseCommandLineOption())
+ report_fatal_error("Invalid rule identifier");
+
+ bool IsOptNone = MF.getTarget().getOptLevel() == CodeGenOptLevel::None;
+
+ GISelValueTracking &VT = MFAM.getResult<GISelValueTrackingAnalysis>(MF);
+ GISelCSEInfo *CSEInfo = MFAM.getResult<GISelCSEAnalysis>(MF).get();
+ MachineDominatorTree *MDT =
+ IsOptNone ? nullptr : &MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+
+ if (!runCombiner(MF, &VT, CSEInfo, MDT, RuleConfig,
+ /*EnableOpt=*/!IsOptNone))
+ return PreservedAnalyses::all();
+
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<GISelValueTrackingAnalysis>();
+ PA.preserve<GISelCSEAnalysis>();
+ return PA;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index f25fab4b24721..b8a1e4a656fd8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -716,7 +716,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeAMDGPUPromoteKernelArgumentsPass(*PR);
initializeAMDGPULowerKernelAttributesPass(*PR);
initializeAMDGPUExportKernelRuntimeHandlesLegacyPass(*PR);
- initializeAMDGPUPostLegalizerCombinerPass(*PR);
+ initializeAMDGPUPostLegalizerCombinerLegacyPass(*PR);
initializeAMDGPUPreLegalizerCombinerLegacyPass(*PR);
initializeAMDGPURegBankCombinerLegacyPass(*PR);
initializeAMDGPUPromoteAllocaPass(*PR);
@@ -1802,7 +1802,7 @@ bool GCNPassConfig::addLegalizeMachineIR() {
void GCNPassConfig::addPreRegBankSelect() {
bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;
- addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
+ addPass(createAMDGPUPostLegalizeCombinerLegacy(IsOptNone));
addPass(createAMDGPUGlobalISelDivergenceLoweringPass());
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir
index 4a114a7553cb9..e34313ede7a17 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgpu8.03-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03-amd-amdhsa -passes=amdgpu-postlegalizer-combiner -verify-each %s -o - | FileCheck %s
---
name: cvt_f32_ubyte0_lshr_0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
index 9729a23c816c3..8346c29770296 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -passes=amdgpu-postlegalizer-combiner -verify-each %s -o - | FileCheck %s
---
name: test_fcanonicalize
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fdiv-sqrt-to-rsq.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fdiv-sqrt-to-rsq.mir
index 489995dc23b4d..631047d37d20d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fdiv-sqrt-to-rsq.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fdiv-sqrt-to-rsq.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgpu10.10 -passes=amdgpu-postlegalizer-combiner -verify-each %s -o - | FileCheck -check-prefix=GCN %s
---
name: rsq_f16
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
index 5d513504f71ce..3bb3dd30d3ca9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -passes=amdgpu-postlegalizer-combiner -verify-each %s -o - | FileCheck %s
---
name: uitofp_char_to_f32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
index 40029be13d5db..895789aa37528 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgpu10.10 -passes=amdgpu-postlegalizer-combiner -verify-each %s -o - | FileCheck -check-prefix=GCN %s
---
name: rcp_sqrt_test_f32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
index bea877ea72fb2..221e9b730f603 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=amdgpu12.00 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00 -passes=amdgpu-postlegalizer-combiner -verify-each -o - %s | FileCheck %s
---
name: mul_s64
More information about the llvm-commits
mailing list