[llvm] [Hexagon] Exclude debug instructions from load/store widening size limit (PR #221649)

[Yongqiang Tian via llvm-commits]

yqtian-se wrote:

> For the regression test, could we check the relevant transformation directly, specifically the presence of DBG_VALUE followed by the widened L4_loadrd_rr, rather than matching the entire MIR block with CHECK-NEXT? This would verify the bug while avoiding brittleness from unrelated instruction ordering or MIR formatting changes.

Hi @quic-asaravan Thanks for the suggestion. 

Do you mean simplifying the checks to something like this?

    ; WIDEN-LABEL: name: qhl_scalar_dsp_fft_f32
    ; WIDEN: DBG_VALUE
    ; WIDEN-NEXT: {{%[0-9]+}}:doubleregs = L4_loadrd_rr
    ;
    ; NO-WIDEN-LABEL: name: qhl_scalar_dsp_fft_f32
    ; NO-WIDEN: DBG_VALUE
    ; NO-WIDEN-NOT: L4_loadrd_rr
    ; NO-WIDEN-COUNT-2: L2_loadri_io

I tested both RUN lines with these checks. They pass with the patched llc, while the WIDEN check fails with the unpatched llc.

I would also remove the autogenerated NOTE because these would now be intentionally hand-written checks. Is this what you had in mind?


https://github.com/llvm/llvm-project/pull/221649