[llvm] 2a01771 - [LoongArch][NFC] Add tests for memory barrier optimization (#218596)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 10 20:50:34 PDT 2026
Author: hev
Date: 2026-09-11T11:50:26+08:00
New Revision: 2a0177189f4be62eb51ddca3fd4b8836c538dc12
URL: https://github.com/llvm/llvm-project/commit/2a0177189f4be62eb51ddca3fd4b8836c538dc12
DIFF: https://github.com/llvm/llvm-project/commit/2a0177189f4be62eb51ddca3fd4b8836c538dc12.diff
LOG: [LoongArch][NFC] Add tests for memory barrier optimization (#218596)
Added:
llvm/test/CodeGen/LoongArch/memory-barrier-opt.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/LoongArch/memory-barrier-opt.ll b/llvm/test/CodeGen/LoongArch/memory-barrier-opt.ll
new file mode 100644
index 0000000000000..fa37dda01c7b1
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/memory-barrier-opt.ll
@@ -0,0 +1,711 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 -mattr=+d < %s | FileCheck %s
+
+;; Positive
+
+define void @dbar_acquire_acquire() nounwind {
+; CHECK-LABEL: dbar_acquire_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ fence acquire
+ ret void
+}
+
+define void @dbar_acquire_release() nounwind {
+; CHECK-LABEL: dbar_acquire_release:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ fence release
+ ret void
+}
+
+define i32 @dbar_acquire_add_acquire(i32 %a) nounwind {
+; CHECK-LABEL: dbar_acquire_add_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: addi.w $a0, $a0, 1
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ %0 = add i32 %a, 1
+ fence acquire
+ ret i32 %0
+}
+
+define void @dbar_release_acquire() nounwind {
+; CHECK-LABEL: dbar_release_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence release
+ fence acquire
+ ret void
+}
+
+define void @dbar_seq_cst_acq_rel_seq_cst() nounwind {
+; CHECK-LABEL: dbar_seq_cst_acq_rel_seq_cst:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 16
+; CHECK-NEXT: dbar 16
+; CHECK-NEXT: dbar 16
+; CHECK-NEXT: ret
+entry:
+ fence seq_cst
+ fence acq_rel
+ fence seq_cst
+ ret void
+}
+
+define void @dbar_acquire_asm_dbar_acquire() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_dbar_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: dbar 22
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void asm "dbar 22", ""()
+ fence acquire
+ ret void
+}
+
+define void @dbar_acquire_asm_space_dbar_acquire() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_space_dbar_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: dbar 22
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void asm " dbar 22", ""()
+ fence acquire
+ ret void
+}
+
+define void @dbar_acquire_asm_comment_dbar_acquire() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_comment_dbar_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: dbar 22 # barrier
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void asm "dbar 22 # barrier", ""()
+ fence acquire
+ ret void
+}
+
+define void @dbar_acquire_asm_arg0_dbar_acquire() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_arg0_dbar_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: dbar 16
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void asm sideeffect "dbar $0", "I,I,~{memory}"(i32 16, i32 22)
+ fence acquire
+ ret void
+}
+
+define void @dbar_acquire_asm_arg1_dbar_acquire() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_arg1_dbar_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: dbar 16
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void asm sideeffect "dbar $1", "I,I,~{memory}"(i32 22, i32 16)
+ fence acquire
+ ret void
+}
+
+define void @dbar_completion_acquire() nounwind {
+; CHECK-LABEL: dbar_completion_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 0
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.loongarch.dbar(i32 0)
+ fence acquire
+ ret void
+}
+
+define void @dbar_release_completion() nounwind {
+; CHECK-LABEL: dbar_release_completion:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: dbar 0
+; CHECK-NEXT: ret
+entry:
+ fence release
+ call void @llvm.loongarch.dbar(i32 0)
+ ret void
+}
+
+define void @dbar_release_amswap_i8_acquire() nounwind {
+; CHECK-LABEL: dbar_release_amswap_i8_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: addi.w $a0, $zero, -256
+; CHECK-NEXT: amand_db.w $a1, $a0, $zero
+; CHECK-NEXT: ret
+entry:
+ fence release
+ atomicrmw xchg ptr null, i8 0 acquire
+ ret void
+}
+
+define void @dbar_release_amswap_i32_acquire() nounwind {
+; CHECK-LABEL: dbar_release_amswap_i32_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: amswap_db.w $a0, $zero, $zero
+; CHECK-NEXT: ret
+entry:
+ fence release
+ atomicrmw xchg ptr null, i32 0 acquire
+ ret void
+}
+
+define void @dbar_release_amswap_i32_monotonic() nounwind {
+; CHECK-LABEL: dbar_release_amswap_i32_monotonic:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: amswap.w $a0, $zero, $zero
+; CHECK-NEXT: ret
+entry:
+ fence release
+ atomicrmw xchg ptr null, i32 0 monotonic
+ ret void
+}
+
+define void @dbar_completion_amswap_i32_monotonic() nounwind {
+; CHECK-LABEL: dbar_completion_amswap_i32_monotonic:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 0
+; CHECK-NEXT: amswap.w $a0, $zero, $zero
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.loongarch.dbar(i32 0)
+ atomicrmw xchg ptr null, i32 0 monotonic
+ ret void
+}
+
+define void @amswap_i8_release_dbar_acquire() nounwind {
+; CHECK-LABEL: amswap_i8_release_dbar_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi.w $a0, $zero, -256
+; CHECK-NEXT: amand_db.w $a1, $a0, $zero
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ atomicrmw xchg ptr null, i8 0 release
+ fence acquire
+ ret void
+}
+
+define void @amswap_i32_release_dbar_acquire() nounwind {
+; CHECK-LABEL: amswap_i32_release_dbar_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: amswap_db.w $a0, $zero, $zero
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ atomicrmw xchg ptr null, i32 0 release
+ fence acquire
+ ret void
+}
+
+define void @amswap_i32_release_dbar_completion() nounwind {
+; CHECK-LABEL: amswap_i32_release_dbar_completion:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: amswap_db.w $a0, $zero, $zero
+; CHECK-NEXT: dbar 0
+; CHECK-NEXT: ret
+entry:
+ atomicrmw xchg ptr null, i32 0 release
+ call void @llvm.loongarch.dbar(i32 0)
+ ret void
+}
+
+define void @dbar_release_amswap_i8_release_dbar_acquire() nounwind {
+; CHECK-LABEL: dbar_release_amswap_i8_release_dbar_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: addi.w $a0, $zero, -256
+; CHECK-NEXT: amand_db.w $a1, $a0, $zero
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence release
+ atomicrmw xchg ptr null, i8 0 release
+ fence acquire
+ ret void
+}
+
+define void @dbar_acquire_amswap_i32_release_dbar_acquire() nounwind {
+; CHECK-LABEL: dbar_acquire_amswap_i32_release_dbar_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: amswap_db.w $a0, $zero, $zero
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ atomicrmw xchg ptr null, i32 0 release
+ fence acquire
+ ret void
+}
+
+define void @dbar_completion_amswap_i32_release_dbar_completion() nounwind {
+; CHECK-LABEL: dbar_completion_amswap_i32_release_dbar_completion:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 0
+; CHECK-NEXT: amswap_db.w $a0, $zero, $zero
+; CHECK-NEXT: dbar 0
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.loongarch.dbar(i32 0)
+ atomicrmw xchg ptr null, i32 0 release
+ call void @llvm.loongarch.dbar(i32 0)
+ ret void
+}
+
+define void @dbar_acquire_asm_amswap_i32_release() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_amswap_i32_release:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: amswap_db.w $a0, $a1, $a2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void asm "amswap_db.w $$r4, $$r5, $$r6", ""()
+ ret void
+}
+
+define void @dbar_acquire_asm_amswap_i32_monotonic() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_amswap_i32_monotonic:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: amswap.w $a0, $a1, $a2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void asm sideeffect "amswap.w $$r4, $$r5, $$r6", ""()
+ ret void
+}
+
+define void @dbar_acquire_asm_space_amswap_i32_monotonic() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_space_amswap_i32_monotonic:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: amswap.w $a0, $a1, $a2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void asm sideeffect " amswap.w $$r4, $$r5, $$r6", ""()
+ ret void
+}
+
+define void @dbar_acquire_asm_comment_amswap_i32_monotonic() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_comment_amswap_i32_monotonic:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: amswap.w $a0, $a1, $a2 # atomic
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void asm sideeffect "amswap.w $$r4, $$r5, $$r6 # atomic", ""()
+ ret void
+}
+
+define void @dbar_acquire_asm_args_amswap_i32_monotonic() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_args_amswap_i32_monotonic:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: amswap.w $a0, $zero, $zero
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call i32 asm sideeffect "amswap.w $0, $1, $2", "=r,r,r,~{memory}"(i32 0, i32 0)
+ ret void
+}
+
+define void @dbar_acquire_asm_reg_args_amswap_i32_monotonic() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_reg_args_amswap_i32_monotonic:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: amswap_db.w $ra, $zero, $zero
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void asm sideeffect "amswap_db.w $$r1, $0, $1", "r,r,~{memory}"(i32 0, i32 0)
+ ret void
+}
+
+define void @dbar_acquire_cmpxchg_i32_dbar_release() nounwind {
+; CHECK-LABEL: dbar_acquire_cmpxchg_i32_dbar_release:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ori $a0, $zero, 1
+; CHECK-NEXT: .LBB28_1: # %entry
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ll.w $a1, $zero, 0
+; CHECK-NEXT: bne $a1, $zero, .LBB28_3
+; CHECK-NEXT: # %bb.2: # %entry
+; CHECK-NEXT: # in Loop: Header=BB28_1 Depth=1
+; CHECK-NEXT: move $a2, $a0
+; CHECK-NEXT: sc.w $a2, $zero, 0
+; CHECK-NEXT: beq $a2, $zero, .LBB28_1
+; CHECK-NEXT: b .LBB28_4
+; CHECK-NEXT: .LBB28_3: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: .LBB28_4: # %entry
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ cmpxchg ptr null, i32 0, i32 1 acquire acquire
+ fence release
+ ret void
+}
+
+define void @cfg_dominate(i1 %a) {
+; CHECK-LABEL: cfg_dominate:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi $a0, $a0, 1
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: beqz $a0, .LBB29_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB29_2:
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ br i1 %a, label %2, label %3
+2:
+ fence acquire
+ ret void
+3:
+ fence release
+ ret void
+}
+
+define void @cfg_postdominate(i1 %a, i1 %b, i1 %c) {
+; CHECK-LABEL: cfg_postdominate:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi $a0, $a0, 1
+; CHECK-NEXT: beqz $a0, .LBB30_2
+; CHECK-NEXT: .LBB30_1:
+; CHECK-NEXT: andi $a0, $a1, 1
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: beqz $a0, .LBB30_3
+; CHECK-NEXT: .LBB30_2:
+; CHECK-NEXT: andi $a0, $a2, 1
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: bnez $a0, .LBB30_1
+; CHECK-NEXT: .LBB30_3:
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: ret
+entry:
+ br i1 %a, label %2, label %3
+2:
+ fence acquire
+ br i1 %b, label %3, label %4
+3:
+ fence release
+ br i1 %c, label %2, label %4
+4:
+ fence release
+ ret void
+}
+
+;; Negative
+
+define void @dbar_sa_acquire() nounwind {
+; CHECK-LABEL: dbar_sa_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 1792
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.loongarch.dbar(i32 1792)
+ fence acquire
+ ret void
+}
+
+define void @dbar_release_sa() nounwind {
+; CHECK-LABEL: dbar_release_sa:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: dbar 1792
+; CHECK-NEXT: ret
+entry:
+ fence release
+ call void @llvm.loongarch.dbar(i32 1792)
+ ret void
+}
+define void @asm_dbar_sa_acquire() nounwind {
+; CHECK-LABEL: asm_dbar_sa_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: dbar 1792
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ call void asm "dbar 1792", ""()
+ fence acquire
+ ret void
+}
+
+define void @asm_arg_dbar_release_sa() nounwind {
+; CHECK-LABEL: asm_arg_dbar_release_sa:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: #APP
+; CHECK-NEXT: dbar 1792
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: ret
+entry:
+ fence release
+ call void asm "dbar $0", "I,~{memory}"(i32 1792)
+ ret void
+}
+
+define void @dbar_acquire_asm_dbar_acquire_nop() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_dbar_acquire_nop:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: dbar 22
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void asm "dbar 22; nop", ""()
+ fence acquire
+ ret void
+}
+
+define void @dbar_acquire_asm_dbar_acquire_idle() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_dbar_acquire_idle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: dbar 22
+; CHECK-NEXT: idle 0
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void asm "dbar 22\0Aidle 0", ""()
+ fence acquire
+ ret void
+}
+
+define i32 @dbar_acquire_load_acquire() nounwind {
+; CHECK-LABEL: dbar_acquire_load_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ld.w $a0, $zero, 0
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ %0 = load i32, ptr null
+ fence acquire
+ ret i32 %0
+}
+
+define void @dbar_acquire_store_acquire() nounwind {
+; CHECK-LABEL: dbar_acquire_store_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: st.w $zero, $zero, 0
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ store i32 0, ptr null
+ fence acquire
+ ret void
+}
+
+declare void @callee();
+define void @dbar_acquire_call_acquire() nounwind {
+; CHECK-LABEL: dbar_acquire_call_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi.d $sp, $sp, -16
+; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee)
+; CHECK-NEXT: jirl $ra, $ra, 0
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
+; CHECK-NEXT: addi.d $sp, $sp, 16
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void @callee();
+ fence acquire
+ ret void
+}
+
+define void @dbar_acquire_asm_acquire() nounwind {
+; CHECK-LABEL: dbar_acquire_asm_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: #APP
+; CHECK-NEXT: idle 0
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call void asm "idle 0", ""()
+ fence acquire
+ ret void
+}
+
+define void @dbar_acquire_sideeffect_acquire() nounwind {
+; CHECK-LABEL: dbar_acquire_sideeffect_acquire:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: move $a0, $zero
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: csrwr $a0, 1
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ call i32 @llvm.loongarch.csrwr.w(i32 0, i32 1)
+ fence acquire
+ ret void
+}
+
+define void @cfg_dominate_store(i1 %a) {
+; CHECK-LABEL: cfg_dominate_store:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi $a0, $a0, 1
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: st.w $zero, $zero, 0
+; CHECK-NEXT: beqz $a0, .LBB42_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB42_2:
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: ret
+entry:
+ fence acquire
+ store i32 0, ptr null
+ br i1 %a, label %2, label %3
+2:
+ fence acquire
+ ret void
+3:
+ fence release
+ ret void
+}
+
+define void @cfg_postdominate_store(i1 %a, i1 %b, i1 %c) {
+; CHECK-LABEL: cfg_postdominate_store:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi $a0, $a0, 1
+; CHECK-NEXT: beqz $a0, .LBB43_2
+; CHECK-NEXT: .LBB43_1:
+; CHECK-NEXT: andi $a0, $a1, 1
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: beqz $a0, .LBB43_3
+; CHECK-NEXT: .LBB43_2:
+; CHECK-NEXT: andi $a0, $a2, 1
+; CHECK-NEXT: st.w $zero, $zero, 0
+; CHECK-NEXT: bnez $a0, .LBB43_1
+; CHECK-NEXT: .LBB43_3:
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: ret
+entry:
+ br i1 %a, label %2, label %3
+2:
+ fence acquire
+ br i1 %b, label %3, label %4
+3:
+ store i32 0, ptr null
+ br i1 %c, label %2, label %4
+4:
+ fence release
+ ret void
+}
+
+define void @cfg_no_dom_no_postdom(i1 %a, i1 %b, i1 %c) {
+; CHECK-LABEL: cfg_no_dom_no_postdom:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi $a0, $a0, 1
+; CHECK-NEXT: beqz $a0, .LBB44_2
+; CHECK-NEXT: .LBB44_1:
+; CHECK-NEXT: andi $a0, $a1, 1
+; CHECK-NEXT: dbar 20
+; CHECK-NEXT: beqz $a0, .LBB44_3
+; CHECK-NEXT: .LBB44_2:
+; CHECK-NEXT: andi $a0, $a2, 1
+; CHECK-NEXT: dbar 18
+; CHECK-NEXT: bnez $a0, .LBB44_1
+; CHECK-NEXT: .LBB44_3:
+; CHECK-NEXT: ret
+entry:
+ br i1 %a, label %2, label %3
+2:
+ fence acquire
+ br i1 %b, label %3, label %4
+3:
+ fence release
+ br i1 %c, label %2, label %4
+4:
+ ret void
+}
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