[llvm] [RISCV] Lower f16 to i64 fp_to_[su]int via i32 on RV32 with Zfh (PR #222829)
Kane Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 10 19:31:12 PDT 2026
https://github.com/ReVe1uv created https://github.com/llvm/llvm-project/pull/222829
f16 is the only FP type whose finite values always fit in an i32 after truncation towards zero, so the conversion can be done in i32 and extended instead of a __fix(un)hfdi libcall.
The expandFPToI ( ExpandIRInsts.cpp ) only expands conversions wider than the target limit (64 on RV32), so f16-to-i64 on RV32 is untouched by it and this change is fully complementary.
>From d5a44c948984de98dc33dc69fa6fcd8e5b58aa52 Mon Sep 17 00:00:00 2001
From: Kane Wang <wangqiang1 at kylinos.cn>
Date: Thu, 10 Sep 2026 17:35:04 +0800
Subject: [PATCH] [RISCV] Lower f16 to i64 fp_to_[su]int via i32 on RV32 with
Zfh
f16 is the only FP type whose finite values always fit in an i32 after
truncation towards zero, so the conversion can be done in i32 and
extended instead of a __fix(un)hfdi libcall. Out of range values and
NaN are poison, so the fcvt clamping is acceptable.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 34 +-
.../test/CodeGen/RISCV/half-convert-strict.ll | 28 +-
llvm/test/CodeGen/RISCV/half-convert.ll | 56 +--
llvm/test/CodeGen/RISCV/half-round-conv.ll | 320 ++----------------
4 files changed, 91 insertions(+), 347 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 5f8ad5da42da1..d61edda2a0489 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -907,6 +907,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT},
MVT::i32, Custom);
setOperationAction(ISD::LROUND, MVT::i32, Custom);
+ } else if (Subtarget.hasStdExtZfhOrZhinx()) {
+ // f16 is the only FP type whose finite values always fit in an i32 after
+ // truncation towards zero, so an f16 to i64 conversion can be done by
+ // converting to i32 and extending, rather than using a libcall.
+ setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT,
+ ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT},
+ MVT::i64, Custom);
}
if (Subtarget.hasStdExtFOrZfinx()) {
@@ -16363,12 +16370,35 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: {
- assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
- "Unexpected custom legalisation");
bool IsStrict = N->isStrictFPOpcode();
bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
N->getOpcode() == ISD::STRICT_FP_TO_SINT;
SDValue Op0 = IsStrict ? N->getOperand(1) : N->getOperand(0);
+
+ // On RV32, only f16 operands are handled here; other operand types fall
+ // back to the default expansion, which uses a libcall.
+ if (!Subtarget.is64Bit()) {
+ assert(N->getValueType(0) == MVT::i64 &&
+ "Unexpected custom legalisation");
+ if (Op0.getValueType() != MVT::f16)
+ return;
+ SDValue Cvt;
+ if (IsStrict) {
+ Cvt = DAG.getNode(
+ IsSigned ? ISD::STRICT_FP_TO_SINT : ISD::STRICT_FP_TO_UINT, DL,
+ DAG.getVTList(MVT::i32, MVT::Other), N->getOperand(0), Op0);
+ } else {
+ Cvt = DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, DL,
+ MVT::i32, Op0);
+ }
+ Results.push_back(DAG.getNode(
+ IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL, MVT::i64, Cvt));
+ if (IsStrict)
+ Results.push_back(Cvt.getValue(1));
+ return;
+ }
+
+ assert(N->getValueType(0) == MVT::i32 && "Unexpected custom legalisation");
if (getTypeAction(*DAG.getContext(), Op0.getValueType()) !=
TargetLowering::TypeSoftenFloat) {
if (!isTypeLegal(Op0.getValueType()))
diff --git a/llvm/test/CodeGen/RISCV/half-convert-strict.ll b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
index 4a6f8a0d9a6d3..73aca398827c6 100644
--- a/llvm/test/CodeGen/RISCV/half-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
@@ -399,11 +399,8 @@ define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) strictfp {
define i64 @fcvt_l_h(half %a) nounwind strictfp {
; CHECK32-IZFH-LABEL: fcvt_l_h:
; CHECK32-IZFH: # %bb.0:
-; CHECK32-IZFH-NEXT: addi sp, sp, -16
-; CHECK32-IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZFH-NEXT: call __fixhfdi
-; CHECK32-IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZFH-NEXT: addi sp, sp, 16
+; CHECK32-IZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; CHECK32-IZFH-NEXT: srai a1, a0, 31
; CHECK32-IZFH-NEXT: ret
;
; CHECK64-IZFH-LABEL: fcvt_l_h:
@@ -413,11 +410,8 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp {
;
; CHECK32-IZHINX-LABEL: fcvt_l_h:
; CHECK32-IZHINX: # %bb.0:
-; CHECK32-IZHINX-NEXT: addi sp, sp, -16
-; CHECK32-IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZHINX-NEXT: call __fixhfdi
-; CHECK32-IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZHINX-NEXT: addi sp, sp, 16
+; CHECK32-IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; CHECK32-IZHINX-NEXT: srai a1, a0, 31
; CHECK32-IZHINX-NEXT: ret
;
; CHECK64-IZHINX-LABEL: fcvt_l_h:
@@ -475,11 +469,8 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp {
define i64 @fcvt_lu_h(half %a) nounwind strictfp {
; CHECK32-IZFH-LABEL: fcvt_lu_h:
; CHECK32-IZFH: # %bb.0:
-; CHECK32-IZFH-NEXT: addi sp, sp, -16
-; CHECK32-IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZFH-NEXT: call __fixunshfdi
-; CHECK32-IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZFH-NEXT: addi sp, sp, 16
+; CHECK32-IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; CHECK32-IZFH-NEXT: li a1, 0
; CHECK32-IZFH-NEXT: ret
;
; CHECK64-IZFH-LABEL: fcvt_lu_h:
@@ -489,11 +480,8 @@ define i64 @fcvt_lu_h(half %a) nounwind strictfp {
;
; CHECK32-IZHINX-LABEL: fcvt_lu_h:
; CHECK32-IZHINX: # %bb.0:
-; CHECK32-IZHINX-NEXT: addi sp, sp, -16
-; CHECK32-IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZHINX-NEXT: call __fixunshfdi
-; CHECK32-IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZHINX-NEXT: addi sp, sp, 16
+; CHECK32-IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; CHECK32-IZHINX-NEXT: li a1, 0
; CHECK32-IZHINX-NEXT: ret
;
; CHECK64-IZHINX-LABEL: fcvt_lu_h:
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index 646b13c825195..fe2de98417df8 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -1991,11 +1991,8 @@ start:
define i64 @fcvt_l_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_l_h:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: call __fixhfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: addi sp, sp, 16
+; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; RV32IZFH-NEXT: srai a1, a0, 31
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_l_h:
@@ -2005,11 +2002,8 @@ define i64 @fcvt_l_h(half %a) nounwind {
;
; RV32IDZFH-LABEL: fcvt_l_h:
; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: call __fixhfdi
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
+; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; RV32IDZFH-NEXT: srai a1, a0, 31
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_l_h:
@@ -2019,11 +2013,8 @@ define i64 @fcvt_l_h(half %a) nounwind {
;
; RV32IZHINX-LABEL: fcvt_l_h:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: call __fixhfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: addi sp, sp, 16
+; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT: srai a1, a0, 31
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: fcvt_l_h:
@@ -2033,11 +2024,8 @@ define i64 @fcvt_l_h(half %a) nounwind {
;
; RV32IZDINXZHINX-LABEL: fcvt_l_h:
; RV32IZDINXZHINX: # %bb.0:
-; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
-; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZDINXZHINX-NEXT: call __fixhfdi
-; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT: srai a1, a0, 31
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: fcvt_l_h:
@@ -2753,11 +2741,8 @@ start:
define i64 @fcvt_lu_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_lu_h:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: call __fixunshfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: addi sp, sp, 16
+; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IZFH-NEXT: li a1, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_lu_h:
@@ -2767,11 +2752,8 @@ define i64 @fcvt_lu_h(half %a) nounwind {
;
; RV32IDZFH-LABEL: fcvt_lu_h:
; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: call __fixunshfdi
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
+; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IDZFH-NEXT: li a1, 0
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_lu_h:
@@ -2781,11 +2763,8 @@ define i64 @fcvt_lu_h(half %a) nounwind {
;
; RV32IZHINX-LABEL: fcvt_lu_h:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: call __fixunshfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: addi sp, sp, 16
+; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT: li a1, 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: fcvt_lu_h:
@@ -2795,11 +2774,8 @@ define i64 @fcvt_lu_h(half %a) nounwind {
;
; RV32IZDINXZHINX-LABEL: fcvt_lu_h:
; RV32IZDINXZHINX: # %bb.0:
-; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
-; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZDINXZHINX-NEXT: call __fixunshfdi
-; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT: li a1, 0
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: fcvt_lu_h:
diff --git a/llvm/test/CodeGen/RISCV/half-round-conv.ll b/llvm/test/CodeGen/RISCV/half-round-conv.ll
index 7c3ef17d952a8..4a08868723da5 100644
--- a/llvm/test/CodeGen/RISCV/half-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/half-round-conv.ll
@@ -309,26 +309,8 @@ define signext i32 @test_floor_si32(half %x) {
define i64 @test_floor_si64(half %x) {
; RV32IZFH-LABEL: test_floor_si64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB3_2
-; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB3_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixhfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: srai a1, a0, 31
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_floor_si64:
@@ -348,15 +330,8 @@ define i64 @test_floor_si64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB3_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixhfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT: srai a1, a0, 31
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_floor_si64:
@@ -755,26 +730,8 @@ define signext i32 @test_floor_ui32(half %x) {
define i64 @test_floor_ui64(half %x) {
; RV32IZFH-LABEL: test_floor_ui64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB7_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB7_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixunshfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rdn
+; RV32IZFH-NEXT: li a1, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_floor_ui64:
@@ -794,15 +751,8 @@ define i64 @test_floor_ui64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB7_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixunshfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT: li a1, 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_floor_ui64:
@@ -1201,26 +1151,8 @@ define signext i32 @test_ceil_si32(half %x) {
define i64 @test_ceil_si64(half %x) {
; RV32IZFH-LABEL: test_ceil_si64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB11_2
-; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB11_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixhfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: srai a1, a0, 31
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_ceil_si64:
@@ -1240,15 +1172,8 @@ define i64 @test_ceil_si64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB11_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixhfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT: srai a1, a0, 31
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_ceil_si64:
@@ -1647,26 +1572,8 @@ define signext i32 @test_ceil_ui32(half %x) {
define i64 @test_ceil_ui64(half %x) {
; RV32IZFH-LABEL: test_ceil_ui64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB15_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB15_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixunshfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rup
+; RV32IZFH-NEXT: li a1, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_ceil_ui64:
@@ -1686,15 +1593,8 @@ define i64 @test_ceil_ui64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB15_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixunshfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT: li a1, 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_ceil_ui64:
@@ -2093,26 +1993,8 @@ define signext i32 @test_trunc_si32(half %x) {
define i64 @test_trunc_si64(half %x) {
; RV32IZFH-LABEL: test_trunc_si64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB19_2
-; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB19_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixhfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: srai a1, a0, 31
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_trunc_si64:
@@ -2132,15 +2014,8 @@ define i64 @test_trunc_si64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB19_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixhfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT: srai a1, a0, 31
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_trunc_si64:
@@ -2539,26 +2414,8 @@ define signext i32 @test_trunc_ui32(half %x) {
define i64 @test_trunc_ui64(half %x) {
; RV32IZFH-LABEL: test_trunc_ui64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB23_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB23_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixunshfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IZFH-NEXT: li a1, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_trunc_ui64:
@@ -2578,15 +2435,8 @@ define i64 @test_trunc_ui64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB23_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixunshfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT: li a1, 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_trunc_ui64:
@@ -2985,26 +2835,8 @@ define signext i32 @test_round_si32(half %x) {
define i64 @test_round_si64(half %x) {
; RV32IZFH-LABEL: test_round_si64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB27_2
-; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB27_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixhfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: srai a1, a0, 31
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_round_si64:
@@ -3024,15 +2856,8 @@ define i64 @test_round_si64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB27_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixhfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT: srai a1, a0, 31
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_round_si64:
@@ -3431,26 +3256,8 @@ define signext i32 @test_round_ui32(half %x) {
define i64 @test_round_ui64(half %x) {
; RV32IZFH-LABEL: test_round_ui64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB31_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB31_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixunshfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rmm
+; RV32IZFH-NEXT: li a1, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_round_ui64:
@@ -3470,15 +3277,8 @@ define i64 @test_round_ui64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB31_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixunshfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT: li a1, 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_round_ui64:
@@ -3877,26 +3677,8 @@ define signext i32 @test_roundeven_si32(half %x) {
define i64 @test_roundeven_si64(half %x) {
; RV32IZFH-LABEL: test_roundeven_si64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB35_2
-; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB35_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixhfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: srai a1, a0, 31
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_roundeven_si64:
@@ -3916,15 +3698,8 @@ define i64 @test_roundeven_si64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB35_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixhfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT: srai a1, a0, 31
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_roundeven_si64:
@@ -4323,26 +4098,8 @@ define signext i32 @test_roundeven_ui32(half %x) {
define i64 @test_roundeven_ui64(half %x) {
; RV32IZFH-LABEL: test_roundeven_ui64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB39_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB39_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixunshfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rne
+; RV32IZFH-NEXT: li a1, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_roundeven_ui64:
@@ -4362,15 +4119,8 @@ define i64 @test_roundeven_ui64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB39_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixunshfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT: li a1, 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_roundeven_ui64:
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