[llvm] [AMDGPU] Migrate isVALU(..., false) call sites to isComputeVALU (PR #222772)
Akash Dutta via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 10 14:07:52 PDT 2026
https://github.com/akadutta updated https://github.com/llvm/llvm-project/pull/222772
>From ca22f1ad66c4526d186d8d3d02570452f3147b06 Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Thu, 10 Sep 2026 11:52:03 -0500
Subject: [PATCH 1/4] AMDGPU: Add isComputeVALU and isCoexecutableVALU helpers
to drop AllowLDSDMA
---
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 31 ++++++++++++++++++++++++----
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index ea91f128f9392..1210c4f7c3f87 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -493,17 +493,40 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return SIInstrFlags::isSALU(get(Opcode));
}
- static bool isVALU(const MachineInstr &MI, bool AllowLDSDMA) {
- if (!AllowLDSDMA && isLDSDMA(MI))
- return false;
-
+ /// Return true if MI uses the VALU encoding/pipeline, including LDSDMA.
+ static bool isVALU(const MachineInstr &MI) {
return SIInstrFlags::isVALU(MI);
}
+ /// Return true if Opcode uses the VALU encoding/pipeline, including LDSDMA.
+ bool isVALU(uint32_t Opcode) const {
+ return SIInstrFlags::isVALU(get(Opcode));
+ }
+
+ /// Return true if MI is an ordinary compute VALU instruction. Excludes
+ /// LDSDMA, which is VALU-encoded but not compute/lane/exec semantics.
+ static bool isComputeVALU(const MachineInstr &MI) {
+ return isVALU(MI) && !isLDSDMA(MI);
+ }
+
+ bool isComputeVALU(uint32_t Opcode) const {
+ return isVALU(Opcode) && !isLDSDMA(Opcode);
+ }
+
+ /// Return true if MI may be a WMMA co-execution hazard victim.
+ static bool isCoexecutableVALU(const MachineInstr &MI) {
+ return isComputeVALU(MI) && !isWMMA(MI) && !isSWMMAC(MI);
+ }
+
+ bool isCoexecutableVALU(uint32_t Opcode) const {
+ return isComputeVALU(Opcode) && !isWMMA(Opcode) && !isSWMMAC(Opcode);
+ }
+
/// LDSDMA instructions act as both VALU and memory instructions, thus
/// we also tag them as VALU. However, in many places, we do not actually want
/// to include LDSDMA instructions in this query. By setting \p AllowLDSDMA to
/// false, this will return false for LDSDMA instructions.
+ /// This will be removed once call sites are migrated to the new API.
bool isVALU(uint32_t Opcode, bool AllowLDSDMA) const {
if (!AllowLDSDMA && isLDSDMA(Opcode))
return false;
>From 71688c9134a929b5009273eecb0ac5b2beec02b7 Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Thu, 10 Sep 2026 13:39:41 -0500
Subject: [PATCH 2/4] fix broken func def
---
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 1210c4f7c3f87..ed6a4403fab78 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -527,11 +527,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
/// to include LDSDMA instructions in this query. By setting \p AllowLDSDMA to
/// false, this will return false for LDSDMA instructions.
/// This will be removed once call sites are migrated to the new API.
- bool isVALU(uint32_t Opcode, bool AllowLDSDMA) const {
- if (!AllowLDSDMA && isLDSDMA(Opcode))
- return false;
+ static bool isVALU(const MachineInstr &MI, bool AllowLDSDMA) {
+ return AllowLDSDMA ? isVALU(MI) : isComputeVALU(MI);
+ }
- return SIInstrFlags::isVALU(get(Opcode));
+ bool isVALU(uint32_t Opcode, bool AllowLDSDMA) const {
+ return AllowLDSDMA ? isVALU(Opcode) : isComputeVALU(Opcode);
}
static bool isImage(const MachineInstr &MI) {
>From 99ecca4932f31a94de45546feb595e79c8ec759a Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Thu, 10 Sep 2026 15:55:45 -0500
Subject: [PATCH 3/4] Migrate isVALU(..., false) calls to isCompareVALU
---
llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp | 4 ++--
llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp | 4 ++--
llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp | 4 ++--
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 11 +++--------
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 4 ++--
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 10 +++++-----
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 2 +-
11 files changed, 22 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
index 1f3905a0465e4..87e8d7bbd777c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
@@ -398,7 +398,7 @@ InstructionFlavor llvm::AMDGPU::classifyFlavor(const MachineInstr &MI,
if (SII.isTRANS(MI))
return InstructionFlavor::TRANS;
- if (SII.isVALU(MI, /*AllowLDSDMA=*/false))
+ if (SII.isComputeVALU(MI))
return InstructionFlavor::SingleCycleVALU;
if (SII.isSMRD(MI))
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
index 7d39057300388..7b115389a207b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
@@ -22,7 +22,7 @@ LLVM_DUMP_METHOD void HWEvents::dump() const { dbgs() << *this << "\n"; }
static HWEvents getExpertSchedulingEventType(const MachineInstr &Inst,
const SIInstrInfo &TII) {
- if (TII.isVALU(Inst, /*AllowLDSDMA=*/false)) {
+ if (TII.isComputeVALU(Inst)) {
// Core/Side-, DP-, XDL- and TRANS-MACC VALU instructions complete
// out-of-order with respect to each other, so each of these classes
// has its own event.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp
index 38ee16fd37e28..e0a6170c0a223 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp
@@ -47,7 +47,7 @@ void HazardLatency::apply(ScheduleDAGInstrs *DAG) {
for (SUnit &SU : DAG->SUnits) {
const MachineInstr *MI = SU.getInstr();
- if (!SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/false))
+ if (!SIInstrInfo::isComputeVALU(*MI))
continue;
if (MI->getOpcode() == AMDGPU::V_READLANE_B32 ||
MI->getOpcode() == AMDGPU::V_READFIRSTLANE_B32)
@@ -58,7 +58,7 @@ void HazardLatency::apply(ScheduleDAGInstrs *DAG) {
// Boost latency on VALU writes to SGPRs used by VALUs.
// Reduce risk of premature VALU pipeline stall on associated reads.
MachineInstr *DestMI = SuccDep.getSUnit()->getInstr();
- if (!SIInstrInfo::isVALU(*DestMI, /*AllowLDSDMA=*/false))
+ if (!SIInstrInfo::isComputeVALU(*DestMI))
continue;
Register Reg = SuccDep.getReg();
if (!TRI.isSGPRReg(MRI, Reg))
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index 9ce0e4d8c7664..7fa0925c214e9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -2589,7 +2589,7 @@ bool SchedGroup::canAddMI(const MachineInstr &MI) const {
Result = !MI.mayLoadOrStore();
else if (((SGMask & SchedGroupMask::VALU) != SchedGroupMask::NONE) &&
- TII->isVALU(MI, /*AllowLDSDMA=*/false) && !TII->isMFMAorWMMA(MI) &&
+ TII->isComputeVALU(MI) && !TII->isMFMAorWMMA(MI) &&
!TII->isTRANS(MI)) {
// Some memory instructions may be marked as VALU (e.g. BUFFER_LOAD_*_LDS).
// For our purposes, these shall not be classified as VALU as this results
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
index 779d9b019971f..c9dc4d2e7dfc3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
@@ -155,7 +155,7 @@ bool AMDGPUSetWavePriority::run(MachineFunction &MF) {
MaxNumVALUInstsInMiddle =
std::max(MaxNumVALUInstsInMiddle, NumVALUInstsAtEnd);
NumVALUInstsAtEnd = 0;
- } else if (SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/false)) {
+ } else if (SIInstrInfo::isComputeVALU(MI)) {
if (AtStart)
++MBBInfos[MBB].NumVALUInstsAtStart;
++NumVALUInstsAtEnd;
@@ -188,7 +188,7 @@ bool AMDGPUSetWavePriority::run(MachineFunction &MF) {
// Raise the priority at the beginning of the shader.
MachineBasicBlock::iterator I = Entry.begin(), E = Entry.end();
- while (I != E && !SIInstrInfo::isVALU(*I, /*AllowLDSDMA=*/false) &&
+ while (I != E && !SIInstrInfo::isComputeVALU(*I) &&
!I->isTerminator())
++I;
BuildSetprioMI(Entry, I, HighPriority);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp b/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
index d4bdaa245ff16..7aaae3a29e3aa 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
@@ -273,7 +273,7 @@ class AMDGPUWaitSGPRHazards {
}
// Process only VALUs and SALUs
- bool IsVALU = SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/false);
+ bool IsVALU = SIInstrInfo::isComputeVALU(*MI);
bool IsSALU = SIInstrInfo::isSALU(*MI);
if (!IsVALU && !IsSALU)
continue;
@@ -510,7 +510,7 @@ class AMDGPUWaitSGPRHazards {
if (MI.isMetaInstruction())
continue;
- const bool IsVALU = SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/false);
+ const bool IsVALU = SIInstrInfo::isComputeVALU(MI);
const bool IsSALU = SIInstrInfo::isSALU(MI);
if (!IsVALU && !IsSALU)
continue;
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 11e7e2f1edc97..17808f2bc243c 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1460,7 +1460,7 @@ int GCNHazardRecognizer::checkVALUHazardsHelper(
/// none exists.
static const MachineOperand *
getDstSelForwardingOperand(const MachineInstr &MI, const GCNSubtarget &ST) {
- if (!SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/false))
+ if (!SIInstrInfo::isComputeVALU(MI))
return nullptr;
const SIInstrInfo *TII = ST.getInstrInfo();
@@ -2532,11 +2532,6 @@ bool GCNHazardRecognizer::fixWMMAHazards(MachineInstr *MI) {
return true;
}
-static bool isCoexecutableVALUInst(const MachineInstr &MI) {
- return SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/false) &&
- !SIInstrInfo::isWMMA(MI) && !SIInstrInfo::isSWMMAC(MI);
-}
-
// Classify XDL WMMA instructions into co-execution hazard categories
// (Refer to SPG 4.6.12.1), mainly based on instruction latency.
//
@@ -2614,7 +2609,7 @@ int GCNHazardRecognizer::checkWMMACoexecutionHazards(MachineInstr *MI) const {
return 0;
const SIInstrInfo *TII = ST.getInstrInfo();
- if (!TII->isXDLWMMA(*MI) && !isCoexecutableVALUInst(*MI))
+ if (!TII->isXDLWMMA(*MI) && !SIInstrInfo::isCoexecutableVALU(*MI))
return 0;
// WaitStates here is the number of V_NOPs or unrelated VALU instructions must
@@ -2724,7 +2719,7 @@ bool GCNHazardRecognizer::isCoexecutionHazardFor(const MachineInstr &I,
// Dispatch based on MI type
if (TII.isXDLWMMA(MI))
return hasWMMAToWMMARegOverlap(I, MI);
- if (isCoexecutableVALUInst(MI))
+ if (SIInstrInfo::isCoexecutableVALU(MI))
return hasWMMAToVALURegOverlap(I, MI);
return false;
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 33fb3c7ca37a0..d2873aadb2902 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -1466,7 +1466,7 @@ MCPhysReg WaitcntBrackets::determineVGPR16Dependency(const MachineInstr &MI,
if (!Wait.hasWait())
return Reg;
- if (Context->TII.isVALU(MI, /*AllowLDSDMA=*/false))
+ if (Context->TII.isComputeVALU(MI))
return Reg32;
// If hi/lo16 mixed events
@@ -2592,7 +2592,7 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(
// waits on VA_VDST if the instruction it would precede is not a VALU
// instruction, since hardware handles VALU->VGPR->VALU hazards in
// expert scheduling mode.
- if (TII.isVALU(MI, /*AllowLDSDMA=*/false)) {
+ if (TII.isComputeVALU(MI)) {
Wait.set(AMDGPU::VA_VDST_RD, ~0u);
Wait.set(AMDGPU::VA_VDST_WR, ~0u);
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index d69be52d9241b..d496d3e88345b 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2953,7 +2953,7 @@ bool SIInstrInfo::isLegalToSwap(const MachineInstr &MI, unsigned OpIdx0,
// It may move literal to position other than src0, this is not allowed
// pre-gfx10 However, most test cases need literals in Src0 for VOP
// FIXME: After gfx9, literal can be in place other than Src0
- if (isVALU(MI, /*AllowLDSDMA=*/false)) {
+ if (isComputeVALU(MI)) {
if ((int)OpIdx0 == Src0Idx && !MO0.isReg() &&
!isInlineConstant(MO0, OpInfo1))
return false;
@@ -5729,7 +5729,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
}
// Verify VOP*. Ignore multiple sgpr operands on writelane.
- if (isVALU(MI, /*AllowLDSDMA=*/false) &&
+ if (isComputeVALU(MI) &&
Desc.getOpcode() != AMDGPU::V_WRITELANE_B32) {
unsigned ConstantBusCount = 0;
bool UsesLiteral = false;
@@ -6738,7 +6738,7 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
const bool IsInlineConst = !MO->isReg() && isInlineConstant(*MO, OpInfo);
- if (isVALU(MI, /*AllowLDSDMA=*/false) && !IsInlineConst &&
+ if (isComputeVALU(MI) && !IsInlineConst &&
usesConstantBus(MRI, *MO, OpInfo)) {
const MachineOperand *UsedLiteral = nullptr;
@@ -6854,7 +6854,7 @@ bool SIInstrInfo::isNeverCoissue(MachineInstr &MI) const {
if (!IsGFX950Only && !IsGFX940Only)
return false;
- if (!isVALU(MI, /*AllowLDSDMA=*/false))
+ if (!isComputeVALU(MI))
return false;
// V_COS, V_EXP, V_RCP, etc.
@@ -10274,7 +10274,7 @@ unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
// Instructions may have a 32-bit literal encoded after them. Check
// operands that could ever be literals.
- if (isVALU(MI, /*AllowLDSDMA=*/false) || isSALU(MI)) {
+ if (isComputeVALU(MI) || isSALU(MI)) {
if (isDPP(MI))
return DescSize;
bool HasLiteral = false;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index ed6a4403fab78..a6e836d3e58e6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -909,13 +909,13 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
static bool isVGPRSpill(const MachineInstr &MI) {
return MI.getOpcode() != AMDGPU::SI_SPILL_S32_TO_VGPR &&
MI.getOpcode() != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
- (isSpill(MI) && isVALU(MI, /*AllowLDSDMA=*/false));
+ (isSpill(MI) && isComputeVALU(MI));
}
bool isVGPRSpill(uint32_t Opcode) const {
return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR &&
Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
- (isSpill(Opcode) && isVALU(Opcode, /*AllowLDSDMA=*/false));
+ (isSpill(Opcode) && isComputeVALU(Opcode));
}
static bool isSGPRSpill(const MachineInstr &MI) {
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
index aab3e63f3e9d0..31a531aab203b 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -379,7 +379,7 @@ void SILowerControlFlow::emitIfBreak(MachineInstr &MI) {
if (MI.getOperand(1).isReg()) {
if (MachineInstr *Def = MRI->getUniqueVRegDef(MI.getOperand(1).getReg())) {
SkipAnding = Def->getParent() == MI.getParent() &&
- SIInstrInfo::isVALU(*Def, /*AllowLDSDMA=*/false);
+ SIInstrInfo::isComputeVALU(*Def);
}
}
>From 5b982e1cff33bb3b23cf7b90d57d891351275936 Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Thu, 10 Sep 2026 16:07:34 -0500
Subject: [PATCH 4/4] code format
---
llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp | 3 +--
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
index c9dc4d2e7dfc3..f39dacfa01483 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
@@ -188,8 +188,7 @@ bool AMDGPUSetWavePriority::run(MachineFunction &MF) {
// Raise the priority at the beginning of the shader.
MachineBasicBlock::iterator I = Entry.begin(), E = Entry.end();
- while (I != E && !SIInstrInfo::isComputeVALU(*I) &&
- !I->isTerminator())
+ while (I != E && !SIInstrInfo::isComputeVALU(*I) && !I->isTerminator())
++I;
BuildSetprioMI(Entry, I, HighPriority);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index d496d3e88345b..2ffa73b622ca8 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5729,8 +5729,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
}
// Verify VOP*. Ignore multiple sgpr operands on writelane.
- if (isComputeVALU(MI) &&
- Desc.getOpcode() != AMDGPU::V_WRITELANE_B32) {
+ if (isComputeVALU(MI) && Desc.getOpcode() != AMDGPU::V_WRITELANE_B32) {
unsigned ConstantBusCount = 0;
bool UsesLiteral = false;
const MachineOperand *LiteralVal = nullptr;
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