[llvm] [AMDGPU] DAG Mutation to solve load bunching in outer product matrix multiplications (PR #203095)

[Lukas Sommer via llvm-commits]

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sommerlukas wrote:

So it's currently sorted by the smallest `MinPos` of each fragment's subloads, right? What is the secondary sorting criteria/tie breaker? Would it make sense to use the `MaxPos` or the number of registers in this fragment as tie-breaker, e.g., to expand the window for two smaller fragments instead of a single one?

https://github.com/llvm/llvm-project/pull/203095