[llvm] [AArch64] Reassociate adds/subs of extends for [SU](ADD|SUB)L. (PR #222561)

Paul Walker via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 10 05:52:58 PDT 2026


================
@@ -0,0 +1,237 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
+
+; (a - X) + b  ->  UADDL(a, b) - X
+define <8 x i16> @add_sub_u(<8 x i16> %x, <8 x i8> %a, <8 x i8> %b) {
+; CHECK-LABEL: add_sub_u:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uaddl v1.8h, v1.8b, v2.8b
+; CHECK-NEXT:    sub v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    ret
+  %a.ext = zext <8 x i8> %a to <8 x i16>
+  %b.ext = zext <8 x i8> %b to <8 x i16>
+  %t = sub <8 x i16> %a.ext, %x
+  %r = add <8 x i16> %t, %b.ext
+  ret <8 x i16> %r
+}
+
+; (a - X) + b  ->  SADDL(a, b) - X
+define <8 x i16> @add_sub_s(<8 x i16> %x, <8 x i8> %a, <8 x i8> %b) {
+; CHECK-LABEL: add_sub_s:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    saddl v1.8h, v1.8b, v2.8b
+; CHECK-NEXT:    sub v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    ret
+  %a.ext = sext <8 x i8> %a to <8 x i16>
+  %b.ext = sext <8 x i8> %b to <8 x i16>
+  %t = sub <8 x i16> %a.ext, %x
+  %r = add <8 x i16> %t, %b.ext
+  ret <8 x i16> %r
+}
+
+; (a - X) - b  ->  USUBL(a, b) - X
+define <8 x i16> @sub_sub_u(<8 x i16> %x, <8 x i8> %a, <8 x i8> %b) {
+; CHECK-LABEL: sub_sub_u:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    usubl v1.8h, v1.8b, v2.8b
+; CHECK-NEXT:    sub v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    ret
+  %a.ext = zext <8 x i8> %a to <8 x i16>
+  %b.ext = zext <8 x i8> %b to <8 x i16>
+  %t = sub <8 x i16> %a.ext, %x
+  %r = sub <8 x i16> %t, %b.ext
+  ret <8 x i16> %r
+}
+
+; b - (X + a)  ->  USUBL(b, a) - X
+define <8 x i16> @sub_add_u(<8 x i16> %x, <8 x i8> %a, <8 x i8> %b) {
+; CHECK-LABEL: sub_add_u:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    usubl v1.8h, v2.8b, v1.8b
+; CHECK-NEXT:    sub v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    ret
+  %a.ext = zext <8 x i8> %a to <8 x i16>
+  %b.ext = zext <8 x i8> %b to <8 x i16>
+  %t = add <8 x i16> %x, %a.ext
+  %r = sub <8 x i16> %b.ext, %t
+  ret <8 x i16> %r
+}
+
+define <4 x i32> @sub_sub_u_s(<4 x i32> %x, <4 x i16> %a, <4 x i16> %b) {
----------------
paulwalker-arm wrote:

```suggestion
define <4 x i32> @sub_sub_u_i32(<4 x i32> %x, <4 x i16> %a, <4 x i16> %b) {
```
only because I thought this was testing mixed unsigned/signed extension until I read the implementation.

It's also worth replicating the relevant `(a - X) - b  ->  USUBL(a, b) - X` comment.

https://github.com/llvm/llvm-project/pull/222561


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