[llvm] RegisterPressure: Remove dead defs correctly (PR #222627)
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llvm-commits at lists.llvm.org
Thu Sep 10 05:38:10 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-regalloc
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
When an instruction has overlapping register defs where only some carry the
dead flag (for example a dead super-register def alongside a live sub-register
def), the collector left the shared register units in both the live and dead def
sets. That produced a PressureDiff decrement with no matching increment and tripped
the "PSet overflow/underflow" assertion in getUpwardPressureDelta.
A register unit is dead if any def covering it is dead, regardless of operand
order. Reconcile by subtracting the dead defs from the live defs instead of the
reverse: removeRegLanes only clears the overlapping units, so a def keeps any
units a dead def does not cover.
Fixes #<!-- -->155807.
Fixes #<!-- -->149144.
Fixes #<!-- -->76416.
Fixes #<!-- -->205272.
Co-authored-by: XChy <xxs_chy@<!-- -->outlook.com>
Co-authored-by: Claude claude-opus-4.8 <noreply@<!-- -->anthropic.com>
---
Patch is 62.27 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/222627.diff
15 Files Affected:
- (modified) llvm/lib/CodeGen/RegisterPressure.cpp (+13-6)
- (added) llvm/test/CodeGen/X86/dead-register-pr76416.mir (+35)
- (added) llvm/test/CodeGen/X86/inline-asm-pr149144.ll (+26)
- (added) llvm/test/CodeGen/X86/inline-asm-pr155807.ll (+21)
- (added) llvm/test/CodeGen/X86/inline-asm-pr76416.ll (+75)
- (modified) llvm/test/CodeGen/X86/masked-udiv.ll (+225-208)
- (modified) llvm/test/CodeGen/X86/min-legal-vector-width.ll (+32-32)
- (added) llvm/test/CodeGen/X86/pr205272.ll (+23)
- (modified) llvm/test/CodeGen/X86/ssub_sat_plus.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/udiv_fix.ll (+18-16)
- (modified) llvm/test/CodeGen/X86/udiv_fix_sat.ll (+42-40)
- (modified) llvm/test/CodeGen/X86/usub_sat_plus.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/vector-idiv-strictfp.ll (+104-87)
- (modified) llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll (+72-60)
- (modified) llvm/test/CodeGen/X86/xmulo.ll (+6-6)
``````````diff
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index c42dced2a5bea..5956f52764c90 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -472,18 +472,25 @@ class RegisterOperandsCollector {
for (ConstMIBundleOperands OperI(MI); OperI.isValid(); ++OperI)
collectOperand(*OperI);
- // Remove redundant physreg dead defs.
- for (const VRegMaskOrUnit &P : RegOpers.Defs)
- removeRegLanes(RegOpers.DeadDefs, P);
+ // An instruction can have overlapping defs where only some carry the dead
+ // flag, for example a dead super-register def alongside a live
+ // sub-register def. A register unit is dead if any def covering it is dead,
+ // so subtract the dead defs from the live defs. removeRegLanes only clears
+ // the overlapping units, leaving each def with the units no dead def
+ // covers.
+ for (const VRegMaskOrUnit &P : RegOpers.DeadDefs)
+ removeRegLanes(RegOpers.Defs, P);
}
void collectInstrLanes(const MachineInstr &MI) const {
for (ConstMIBundleOperands OperI(MI); OperI.isValid(); ++OperI)
collectOperandLanes(*OperI);
- // Remove redundant physreg dead defs.
- for (const VRegMaskOrUnit &P : RegOpers.Defs)
- removeRegLanes(RegOpers.DeadDefs, P);
+ // A register unit is dead if any def covering it is dead; subtract the
+ // dead defs from the live defs so overlapping defs do not leave a unit
+ // counted as live. See collectInstr.
+ for (const VRegMaskOrUnit &P : RegOpers.DeadDefs)
+ removeRegLanes(RegOpers.Defs, P);
}
/// Push this operand's register onto the correct vectors.
diff --git a/llvm/test/CodeGen/X86/dead-register-pr76416.mir b/llvm/test/CodeGen/X86/dead-register-pr76416.mir
new file mode 100644
index 0000000000000..718b0545df436
--- /dev/null
+++ b/llvm/test/CodeGen/X86/dead-register-pr76416.mir
@@ -0,0 +1,35 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-unknown-unknown -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
+
+# An overlapping dead super-register def (implicit-def $rax) and dead
+# sub-register def ($eax) must not leave a phantom live register unit, which
+# previously unbalanced the register pressure tracker.
+
+---
+name: vga_load_state
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $rdi
+
+ ; CHECK-LABEL: name: vga_load_state
+ ; CHECK: liveins: $rdi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: dead undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_nosp = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: INLINEASM &"", sideeffect attdialect
+ ; CHECK-NEXT: INLINEASM &"", sideeffect attdialect
+ ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax
+ ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax
+ %0:gr64 = COPY $rdi
+ undef %1.sub_32bit:gr64_nosp = MOV32r0 implicit-def dead $eflags
+ dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax
+ INLINEASM &"", 1 /* sideeffect attdialect */
+ dead $eax = MOV32r0 implicit-def dead $eflags
+ INLINEASM &"", 1 /* sideeffect attdialect */
+ dead $eax = MOV32r0 implicit-def dead $eflags
+ dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax
+
+...
diff --git a/llvm/test/CodeGen/X86/inline-asm-pr149144.ll b/llvm/test/CodeGen/X86/inline-asm-pr149144.ll
new file mode 100644
index 0000000000000..422412246c1f2
--- /dev/null
+++ b/llvm/test/CodeGen/X86/inline-asm-pr149144.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=x86_64 < %s | FileCheck %s
+
+; An inline asm with an "=a" output tied to an input leaves the scheduler with
+; overlapping dead and live physreg defs. The register pressure tracker must
+; not count the shared units as live, or it hits a "PSet overflow/underflow"
+; assertion.
+define i32 @pr149144(i8 %how, ptr %set, ptr %oset) {
+; CHECK-LABEL: pr149144:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset %rbx, -16
+; CHECK-NEXT: movq %rsi, %rcx
+; CHECK-NEXT: movl $14, %ebx
+; CHECK-NEXT: movb %dil, %bl
+; CHECK-NEXT: movl $8, %esi
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
+entry:
+ %0 = tail call i32 asm sideeffect "", "={ax},0{bx}0,{bx},{cx},{dx},{si},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(i32 14, i8 %how, ptr %set, ptr %oset, i32 8)
+ ret i32 %0
+}
diff --git a/llvm/test/CodeGen/X86/inline-asm-pr155807.ll b/llvm/test/CodeGen/X86/inline-asm-pr155807.ll
new file mode 100644
index 0000000000000..3c10773dbb66c
--- /dev/null
+++ b/llvm/test/CodeGen/X86/inline-asm-pr155807.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=x86_64 < %s | FileCheck %s
+
+; LiveVariable Analysis transforms (inlineasm rax, eax) to (inlineasm dead rax, eax)
+; instead of (inlineasm dead rax, dead eax). RegisterPressure fails at considering
+; eax as dead register.
+define i64 @pr155807(i64 %vecext) {
+; CHECK-LABEL: pr155807:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movabsq $705425148255374, %rax # imm = 0x2819497609C8E
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: idivq %rdi
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: retq
+entry:
+ tail call void asm sideeffect "", "~{rax},~{eax},~{dirflag},~{fpsr},~{flags}"()
+ %rem = srem i64 705425148255374, %vecext
+ ret i64 %rem
+}
diff --git a/llvm/test/CodeGen/X86/inline-asm-pr76416.ll b/llvm/test/CodeGen/X86/inline-asm-pr76416.ll
new file mode 100644
index 0000000000000..b14a6eda7a6a6
--- /dev/null
+++ b/llvm/test/CodeGen/X86/inline-asm-pr76416.ll
@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -O2 -mtriple=x86_64 < %s | FileCheck %s
+%struct.anon.5.28.78.99.149.119 = type { [4 x i8] }
+
+ at vga_load_state_p = external dso_local global ptr, align 8
+ at vga_load_state_data = external dso_local global i8, align 1
+
+define dso_local void @vga_load_state() #0 {
+; CHECK-LABEL: vga_load_state:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: cmpl $3, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: jg .LBB0_3
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB0_2: # %for.body
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: incl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: cmpl $3, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: jle .LBB0_2
+; CHECK-NEXT: .LBB0_3: # %for.end
+; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB0_4: # %for.cond1
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: # implicit-def: $edx
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movq vga_load_state_p(%rip), %rax
+; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: movzbl (%rax,%rcx), %eax
+; CHECK-NEXT: movb %al, vga_load_state_data(%rip)
+; CHECK-NEXT: leal 1(%rcx), %eax
+; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: jmp .LBB0_4
+entry:
+ %i = alloca i32, align 4
+ store i32 0, ptr %i, align 4
+ br label %for.cond
+
+for.cond: ; preds = %for.body, %entry
+ %0 = load i32, ptr %i, align 4
+ %cmp = icmp slt i32 %0, 4
+ br i1 %cmp, label %for.body, label %for.end
+
+for.body: ; preds = %for.cond
+ call void asm sideeffect "", "{ax},~{dirflag},~{fpsr},~{flags}"(i8 0) #2
+ %1 = load i32, ptr %i, align 4
+ %inc = add nsw i32 %1, 1
+ store i32 %inc, ptr %i, align 4
+ br label %for.cond
+
+for.end: ; preds = %for.cond
+ store i32 0, ptr %i, align 4
+ br label %for.cond1
+
+for.cond1: ; preds = %for.cond1, %for.end
+ call void asm sideeffect "", "N{dx},~{dirflag},~{fpsr},~{flags}"(i32 poison) #2
+ %2 = load ptr, ptr @vga_load_state_p, align 8
+ %regs = getelementptr inbounds %struct.anon.5.28.78.99.149.119, ptr %2, i32 0, i32 0
+ %3 = load i32, ptr %i, align 4
+ %idxprom = sext i32 %3 to i64
+ %arrayidx = getelementptr inbounds [4 x i8], ptr %regs, i64 0, i64 %idxprom
+ %4 = load i8, ptr %arrayidx, align 1
+ store i8 %4, ptr @vga_load_state_data, align 1
+ %5 = load i32, ptr %i, align 4
+ %inc5 = add nsw i32 %5, 1
+ store i32 %inc5, ptr %i, align 4
+ br label %for.cond1, !llvm.loop !1
+}
+
+!1 = distinct !{!1, !2}
+!2 = !{!"llvm.loop.mustprogress"}
diff --git a/llvm/test/CodeGen/X86/masked-udiv.ll b/llvm/test/CodeGen/X86/masked-udiv.ll
index 2903265589a0b..28c16a1447ec5 100644
--- a/llvm/test/CodeGen/X86/masked-udiv.ll
+++ b/llvm/test/CodeGen/X86/masked-udiv.ll
@@ -204,39 +204,40 @@ define <2 x i64> @udiv_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m) {
define <4 x i64> @udiv_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; SSE2-LABEL: udiv_v4i64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa %xmm0, %xmm5
-; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[2,2,3,3]
+; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,1,1]
; SSE2-NEXT: pslld $31, %xmm6
; SSE2-NEXT: psrad $31, %xmm6
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,1,1]
-; SSE2-NEXT: pslld $31, %xmm4
-; SSE2-NEXT: psrad $31, %xmm4
-; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [1,1]
-; SSE2-NEXT: pand %xmm4, %xmm2
-; SSE2-NEXT: pandn %xmm7, %xmm4
-; SSE2-NEXT: por %xmm2, %xmm4
-; SSE2-NEXT: movq %xmm4, %rcx
+; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1,1]
+; SSE2-NEXT: pand %xmm6, %xmm2
+; SSE2-NEXT: pandn %xmm5, %xmm6
+; SSE2-NEXT: por %xmm2, %xmm6
+; SSE2-NEXT: movq %xmm6, %rcx
; SSE2-NEXT: movq %xmm0, %rax
; SSE2-NEXT: xorl %edx, %edx
; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %xmm0
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[2,3,2,3]
-; SSE2-NEXT: movq %xmm2, %rcx
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm5[2,3,2,3]
-; SSE2-NEXT: movq %xmm2, %rax
+; SSE2-NEXT: movq %rax, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm6[2,3,2,3]
+; SSE2-NEXT: movq %xmm2, %rsi
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; SSE2-NEXT: movq %xmm0, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %xmm2
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; SSE2-NEXT: pand %xmm6, %xmm3
-; SSE2-NEXT: pandn %xmm7, %xmm6
-; SSE2-NEXT: por %xmm3, %xmm6
-; SSE2-NEXT: movq %xmm6, %rcx
+; SSE2-NEXT: divq %rsi
+; SSE2-NEXT: movq %rax, %rsi
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[2,2,3,3]
+; SSE2-NEXT: pslld $31, %xmm4
+; SSE2-NEXT: psrad $31, %xmm4
+; SSE2-NEXT: pand %xmm4, %xmm3
+; SSE2-NEXT: pandn %xmm5, %xmm4
+; SSE2-NEXT: por %xmm3, %xmm4
+; SSE2-NEXT: movq %xmm4, %rdi
; SSE2-NEXT: movq %xmm1, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: divq %rdi
+; SSE2-NEXT: movq %rcx, %xmm0
+; SSE2-NEXT: movq %rsi, %xmm2
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE2-NEXT: movq %rax, %xmm2
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm6[2,3,2,3]
+; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[2,3,2,3]
; SSE2-NEXT: movq %xmm3, %rcx
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; SSE2-NEXT: movq %xmm1, %rax
@@ -250,38 +251,39 @@ define <4 x i64> @udiv_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; SSE42-LABEL: udiv_v4i64:
; SSE42: # %bb.0:
; SSE42-NEXT: movdqa %xmm0, %xmm5
-; SSE42-NEXT: pshufd {{.*#+}} xmm6 = xmm4[2,2,3,3]
; SSE42-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm4[0],zero,xmm4[1],zero
; SSE42-NEXT: psllq $63, %xmm0
-; SSE42-NEXT: movapd {{.*#+}} xmm4 = [1,1]
-; SSE42-NEXT: movapd %xmm4, %xmm7
+; SSE42-NEXT: movapd {{.*#+}} xmm6 = [1,1]
+; SSE42-NEXT: movapd %xmm6, %xmm7
; SSE42-NEXT: blendvpd %xmm0, %xmm2, %xmm7
; SSE42-NEXT: pextrq $1, %xmm7, %rcx
; SSE42-NEXT: pextrq $1, %xmm5, %rax
-; SSE42-NEXT: psllq $63, %xmm6
; SSE42-NEXT: xorl %edx, %edx
; SSE42-NEXT: divq %rcx
-; SSE42-NEXT: movq %rax, %xmm8
-; SSE42-NEXT: movq %xmm7, %rcx
+; SSE42-NEXT: movq %rax, %rcx
+; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm4[2,2,3,3]
+; SSE42-NEXT: psllq $63, %xmm0
+; SSE42-NEXT: movq %xmm7, %rdi
+; SSE42-NEXT: blendvpd %xmm0, %xmm3, %xmm6
+; SSE42-NEXT: pextrq $1, %xmm6, %r8
+; SSE42-NEXT: pextrq $1, %xmm1, %rsi
; SSE42-NEXT: movq %xmm5, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %rcx
-; SSE42-NEXT: movq %rax, %xmm2
-; SSE42-NEXT: movdqa %xmm6, %xmm0
-; SSE42-NEXT: blendvpd %xmm0, %xmm3, %xmm4
-; SSE42-NEXT: pextrq $1, %xmm4, %rcx
-; SSE42-NEXT: pextrq $1, %xmm1, %rax
-; SSE42-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm8[0]
+; SSE42-NEXT: divq %rdi
+; SSE42-NEXT: movq %rax, %rdi
+; SSE42-NEXT: movq %rsi, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %rcx
-; SSE42-NEXT: movq %rax, %xmm0
-; SSE42-NEXT: movq %xmm4, %rcx
+; SSE42-NEXT: divq %r8
+; SSE42-NEXT: movq %rcx, %xmm2
+; SSE42-NEXT: movq %rdi, %xmm0
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE42-NEXT: movq %rax, %xmm2
+; SSE42-NEXT: movq %xmm6, %rcx
; SSE42-NEXT: movq %xmm1, %rax
; SSE42-NEXT: xorl %edx, %edx
; SSE42-NEXT: divq %rcx
; SSE42-NEXT: movq %rax, %xmm1
-; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; SSE42-NEXT: movdqa %xmm2, %xmm0
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE42-NEXT: retq
;
; AVX2-LABEL: udiv_v4i64:
@@ -301,19 +303,20 @@ define <4 x i64> @udiv_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; AVX2-NEXT: vmovq %xmm3, %rax
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: divq %rsi
-; AVX2-NEXT: vmovq %rcx, %xmm2
-; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX2-NEXT: vmovq %rax, %xmm3
+; AVX2-NEXT: movq %rax, %rsi
+; AVX2-NEXT: vpextrq $1, %xmm1, %rdi
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: divq %rcx
-; AVX2-NEXT: movq %rax, %rcx
+; AVX2-NEXT: divq %rdi
+; AVX2-NEXT: movq %rax, %rdi
+; AVX2-NEXT: vmovq %rcx, %xmm2
+; AVX2-NEXT: vmovq %rsi, %xmm3
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
-; AVX2-NEXT: vmovq %xmm1, %rsi
+; AVX2-NEXT: vmovq %xmm1, %rcx
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: divq %rsi
-; AVX2-NEXT: vmovq %rcx, %xmm0
+; AVX2-NEXT: divq %rcx
+; AVX2-NEXT: vmovq %rdi, %xmm0
; AVX2-NEXT: vmovq %rax, %xmm1
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
@@ -816,169 +819,181 @@ define <3 x i10> @udiv_v3i10(<3 x i10> %x, <3 x i10> %y, <3 x i1> %m) {
define <8 x i64> @udiv_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i1> %m) {
; SSE2-LABEL: udiv_v8i64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa %xmm0, %xmm8
-; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0
-; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm0[3,3,3,3]
+; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
+; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm8[0,0,0,0]
; SSE2-NEXT: pshufhw {{.*#+}} xmm9 = xmm9[0,1,2,3,5,5,5,5]
-; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm9[0,0,2,2]
-; SSE2-NEXT: pslld $31, %xmm9
-; SSE2-NEXT: psrad $31, %xmm9
-; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm0[2,2,2,2]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm10 = xmm10[0,1,2,3,5,5,5,5]
-; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm10[0,0,2,2]
+; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
; SSE2-NEXT: pslld $31, %xmm10
; SSE2-NEXT: psrad $31, %xmm10
-; SSE2-NEXT: pshufd {{.*#+}} xmm11 = xmm0[1,1,1,1]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm11 = xmm11[0,1,2,3,5,5,5,5]
-; SSE2-NEXT: pshufd {{.*#+}} xmm12 = xmm11[0,0,2,2]
-; SSE2-NEXT: pslld $31, %xmm12
-; SSE2-NEXT: psrad $31, %xmm12
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
-; SSE2-NEXT: pshufd {{.*#+}} xmm13 = xmm0[0,0,2,2]
-; SSE2-NEXT: pslld $31, %xmm13
-; SSE2-NEXT: psrad $31, %xmm13
-; SSE2-NEXT: movdqa {{.*#+}} xmm11 = [1,1]
-; SSE2-NEXT: pand %xmm13, %xmm4
-; SSE2-NEXT: pandn %xmm11, %xmm13
-; SSE2-NEXT: por %xmm4, %xmm13
-; SSE2-NEXT: movq %xmm13, %rcx
-; SSE2-NEXT: movq %xmm8, %rax
+; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [1,1]
+; SSE2-NEXT: pand %xmm10, %xmm4
+; SSE2-NEXT: pandn %xmm9, %xmm10
+; SSE2-NEXT: por %xmm4, %xmm10
+; SSE2-NEXT: movq %xmm10, %rcx
+; SSE2-NEXT: movq %xmm0, %rax
; SSE2-NEXT: xorl %edx, %edx
; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %xmm0
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm13[2,3,2,3]
-; SSE2-NEXT: movq %xmm4, %rcx
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm8[2,3,2,3]
-; SSE2-NEXT: movq %xmm4, %rax
+; SSE2-NEXT: movq %rax, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm10[2,3,2,3]
+; SSE2-NEXT: movq %xmm4, %rsi
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; SSE2-NEXT: movq %xmm0, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %xmm4
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
-; SSE2-NEXT: pand %xmm12, %xmm5
-; SSE2-NEXT: pandn %xmm11, %xmm12
-; SSE2-NEXT: por %xmm5, %xmm12
-; SSE2-NEXT: movq %xmm12, %rcx
+; SSE2-NEXT: divq %rsi
+; SSE2-NEXT: movq %rax, %rsi
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm8[1,1,1,1]
+; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
+; SSE2-NEXT: pslld $31, %xmm0
+; SSE2-NEXT: psrad $31, %xmm0
+; SSE2-NEXT: pand %xmm0, %xmm5
+; SSE2-NEXT: pandn %xmm9, %xmm0
+; SSE2-NEXT: por %xmm5, %xmm0
+; SSE2-NEXT: movq %xmm0, %rdi
; SSE2-NEXT: movq %xmm1, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %xmm4
-; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm12[2,3,2,3]
-; SSE2-NEXT: movq %xmm5, %rcx
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
-; SSE2-NEXT: movq %xmm1, %rax
+; SSE2-NEXT: divq %rdi
+; SSE2-NEXT: movq %rax, %rdi
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; SSE2-NEXT: movq %xmm0, %r8
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; SSE2-NEXT: movq %xmm0, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %xmm1
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm1[0]
-; SSE2-NEXT: pand %xmm10, %xmm6
-; SSE2-NEXT: pandn %xmm11, %xmm10
-; SSE2-NEXT: por %xmm6, %xmm10
-; SSE2-NEXT: movq %xmm10, %rcx
+; SSE2-NEXT: divq %r8
+; SSE2-NEXT: movq %rax, %r8
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm8[2,2,2,2]
+; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
+; SSE2-NEXT: pslld $31, %xmm0
+; SSE2-NEXT: psrad $31, %xmm0
+; SSE2-NEXT: pand %xmm0, %xmm6
+; SSE2-NEXT: pandn %xmm9, %xmm0
+; SSE2-NEXT: por %xmm6, %xmm0
+; SSE2-NEXT: movq %xmm0, %r9
; SSE2-NEXT: movq %xmm2, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %xmm5
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm10[2,3,2,3]
-; SSE2-NEXT: movq %xmm1, %rcx
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,2,3]
-; SSE2-NEXT: movq %xmm1, %rax
+; SSE2-NEXT: divq %r9
+; SSE2-NEXT: movq %rax, %r9
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; SSE2-NEXT: movq %xmm0, %r10
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]
+; SSE2-NEXT: movq %xmm0, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %xmm1
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm1[0]
-; SSE2-NEXT: pand %xmm9, %xmm7
-; SSE2-NEXT: pandn %xmm11, %xmm9
-; SSE2-NEXT: por %xmm7, %xmm9
-; SSE2-NEXT: movq %xmm9, %rcx...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/222627
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