[llvm] [AMDGPU] Don't merge M0 initializations across calls that clobber M0 (PR #221963)

[Matt Arsenault via llvm-commits]

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@@ -637,12 +643,18 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
 
   // Instructions to re-legalize after changing register classes
   SmallVector<MachineInstr *, 8> Relegalize;
+  SmallVector<MachineInstr *, 4> Calls;
 
   for (MachineBasicBlock &MBB : MF) {
     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
          ++I) {
       MachineInstr &MI = *I;
 
+      // Record calls while walking the function so that hoistAndMergeSGPRInits
+      // can find the registers they clobber through their regmask operand.
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arsenm wrote:

This really shouldn't need to special case calls. Any instruction could also have a regmask 

https://github.com/llvm/llvm-project/pull/221963