[llvm] 5da4b50 - [AMDGPU][GISel] Notify GISel observers when splitting trap blocks (#219128)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 10 03:59:18 PDT 2026
Author: Keshav Vinayak Jha
Date: 2026-09-10T16:29:12+05:30
New Revision: 5da4b50d7a4f12c283b1253a8e4d2c1e1c68a360
URL: https://github.com/llvm/llvm-project/commit/5da4b50d7a4f12c283b1253a8e4d2c1e1c68a360
DIFF: https://github.com/llvm/llvm-project/commit/5da4b50d7a4f12c283b1253a8e4d2c1e1c68a360.diff
LOG: [AMDGPU][GISel] Notify GISel observers when splitting trap blocks (#219128)
`legalizeTrapEndpgm` can split a MBB and move the instructions following
a trap. Since an instruction's parent block is part of its GISel CSE
profile, notify active observers around the moved instructions so they
are re-profiled with the new parent block.
CSE consistency gap exposed by #217258.
Assisted-by: Codex
---------
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Co-authored-by: GPT-5 Codex <noreply at openai.com>
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap.mir
llvm/test/CodeGen/AMDGPU/trap.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index d0091a8295d04..5eab175858e01 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2406,7 +2406,7 @@ bool AMDGPULegalizerInfo::legalizeCustom(
case TargetOpcode::G_SET_FPENV:
return legalizeSetFPEnv(MI, MRI, B);
case TargetOpcode::G_TRAP:
- return legalizeTrap(MI, MRI, B);
+ return legalizeTrap(Helper, MI);
case TargetOpcode::G_DEBUGTRAP:
return legalizeDebugTrap(MI, MRI, B);
default:
@@ -7813,19 +7813,22 @@ bool AMDGPULegalizerInfo::legalizeSBufferPrefetch(LegalizerHelper &Helper,
}
// TODO: Move to selection
-bool AMDGPULegalizerInfo::legalizeTrap(MachineInstr &MI,
- MachineRegisterInfo &MRI,
- MachineIRBuilder &B) const {
+bool AMDGPULegalizerInfo::legalizeTrap(LegalizerHelper &Helper,
+ MachineInstr &MI) const {
+ MachineIRBuilder &B = Helper.MIRBuilder;
+ MachineRegisterInfo &MRI = *B.getMRI();
if (!ST.hasTrapHandler() ||
ST.getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA)
- return legalizeTrapEndpgm(MI, MRI, B);
+ return legalizeTrapEndpgm(Helper, MI);
return ST.supportsGetDoorbellID() ?
legalizeTrapHsa(MI, MRI, B) : legalizeTrapHsaQueuePtr(MI, MRI, B);
}
-bool AMDGPULegalizerInfo::legalizeTrapEndpgm(
- MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const {
+bool AMDGPULegalizerInfo::legalizeTrapEndpgm(LegalizerHelper &Helper,
+ MachineInstr &MI) const {
+ MachineIRBuilder &B = Helper.MIRBuilder;
+ GISelChangeObserver &Observer = Helper.Observer;
const DebugLoc &DL = MI.getDebugLoc();
MachineBasicBlock &BB = B.getMBB();
MachineFunction *MF = BB.getParent();
@@ -7840,7 +7843,18 @@ bool AMDGPULegalizerInfo::legalizeTrapEndpgm(
// We need a block split to make the real endpgm a terminator. We also don't
// want to break phis in successor blocks, so we can't just delete to the
// end of the block.
+ // An instruction's parent block is part of its CSE profile, so notify
+ // observers about the instructions moved by the split.
+ SmallVector<MachineInstr *, 8> MovedInstrs;
+ MachineBasicBlock::iterator SplitPoint(&MI);
+ ++SplitPoint;
+ for (auto I = SplitPoint, E = BB.end(); I != E; ++I) {
+ Observer.changingInstr(*I);
+ MovedInstrs.push_back(&*I);
+ }
BB.splitAt(MI, false /*UpdateLiveIns*/);
+ for (MachineInstr *MovedMI : MovedInstrs)
+ Observer.changedInstr(*MovedMI);
MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
MF->push_back(TrapBB);
BuildMI(*TrapBB, TrapBB->end(), DL, B.getTII().get(AMDGPU::S_ENDPGM))
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
index b2f1df909f06e..0305c789da6f7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -251,10 +251,8 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
bool legalizeSBufferPrefetch(LegalizerHelper &Helper, MachineInstr &MI) const;
- bool legalizeTrap(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &B) const;
- bool legalizeTrapEndpgm(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &B) const;
+ bool legalizeTrap(LegalizerHelper &Helper, MachineInstr &MI) const;
+ bool legalizeTrapEndpgm(LegalizerHelper &Helper, MachineInstr &MI) const;
bool legalizeTrapHsaQueuePtr(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI,
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap.mir
index 80e88e9ed56f0..ca5e011aab29d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap.mir
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=legalizer -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: %if asserts %{ llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=legalizer -enable-cse-in-legalizer=1 -debug-only=cseinfo -filetype=null %s 2>&1 | FileCheck -check-prefix=CSE %s %}
+# RUN: %if asserts %{ llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=legalizer,amdgpu-prelegalizer-combiner -enable-cse-in-legalizer=1 -filetype=null %s %}
# Check edge cases for trap legalization
@@ -34,6 +36,13 @@ body: |
---
name: test_def_fallthrough_after_trap
body: |
+ ; CSE: CSEInfo::Add MI: %2:_(p1) = G_CONSTANT i64 4
+ ; CSE: CSEInfo::Recording new MI %1:_(p1) = G_CONSTANT i64 0
+ ; CSE-NEXT: CSEInfo::Recording new MI %2:_(p1) = G_CONSTANT i64 4
+ ; CSE-NEXT: CSEInfo::Recording new MI %1:_(p1) = G_CONSTANT i64 0
+ ; CSE-NEXT: CSEInfo::Recording new MI %2:_(p1) = G_CONSTANT i64 4
+ ; CSE: CSEInfo::Handling recorded MI %2:_(p1) = G_CONSTANT i64 4
+ ; CSE-NEXT: CSEInfo::Handling recorded MI %1:_(p1) = G_CONSTANT i64 0
; GCN-LABEL: name: test_def_fallthrough_after_trap
; GCN: bb.0:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
@@ -45,11 +54,13 @@ body: |
; GCN-NEXT: successors: %bb.1(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[C1:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(p1) = G_CONSTANT i64 4
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: successors:
; GCN-NEXT: {{ $}}
; GCN-NEXT: G_STORE [[C]](s32), [[C1]](p1) :: (store (s8), addrspace 1)
+ ; GCN-NEXT: G_STORE [[C]](s32), [[C2]](p1) :: (store (s8), addrspace 1)
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.3:
; GCN-NEXT: S_ENDPGM 0
@@ -57,8 +68,10 @@ body: |
%0:_(s8) = G_CONSTANT i8 0
G_TRAP
%1:_(p1) = G_CONSTANT i64 0
+ %2:_(p1) = G_CONSTANT i64 4
bb.1:
G_STORE %0, %1 :: (store 1, addrspace 1)
+ G_STORE %0, %2 :: (store 1, addrspace 1)
...
diff --git a/llvm/test/CodeGen/AMDGPU/trap.ll b/llvm/test/CodeGen/AMDGPU/trap.ll
index c377ce2bceb3d..e1332b8e12791 100644
--- a/llvm/test/CodeGen/AMDGPU/trap.ll
+++ b/llvm/test/CodeGen/AMDGPU/trap.ll
@@ -1,5 +1,6 @@
; RUN: llc -global-isel=0 -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
; RUN: llc -global-isel=1 -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00-unknown-mesa3d -mattr=-trap-handler < %s | FileCheck -check-prefix=GISEL-TRAP %s
; RUN: llc -global-isel=0 -mtriple=amdgpu7.00--amdhsa -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
; RUN: llc -global-isel=1 -mtriple=amdgpu7.00--amdhsa -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
@@ -123,6 +124,12 @@ ret:
; TRAP-BIT: enable_trap_handler = 1
; NO-TRAP-BIT: enable_trap_handler = 0
+; GISEL-TRAP-LABEL: {{^}}non_entry_trap_no_unreachable:
+; GISEL-TRAP: [[ENDPGM:.LBB[0-9]+_[0-9]+]]:{{$}}
+; GISEL-TRAP-NEXT: s_endpgm
+; GISEL-TRAP: s_cbranch_execnz [[ENDPGM]]
+; GISEL-TRAP: ds_write_b32
+
; HSA-TRAP: BB{{[0-9]_[0-9]+}}: ; %trap
; HSA-TRAP: s_mov_b64 s[0:1], s[6:7]
; HSA-TRAP-NEXT: s_trap 2
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