[llvm] [DAG][X86] Bitfield insertion can combine into SHL + SHRD (PR #220182)

[Pratyay Pande via llvm-commits]

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@@ -53859,6 +53859,61 @@ static SDValue combineOrXorWithSETCC(unsigned Opc, const SDLoc &DL, EVT VT,
   return SDValue();
 }
 
+// Fold an OR with a masked destination and a left-shifted
+// source into a shift + double-precision shift (SHRD):
+static SDValue combineOrOnSHLToSHRD(SDNode *N, SDLoc &DL, SelectionDAG &DAG,
+                                    const X86Subtarget &Subtarget) {
+  using namespace SDPatternMatch;
+  assert(N->getOpcode() == ISD::OR && "Invalid Node. Expected OR.");
+
+  // If optimizing for code size, run irrespective of slow SHLD.
+  // If not optimizing for code size and SHLD is slow, then bail.
+  bool IsOptSize = DAG.getMachineFunction().getFunction().hasOptSize();
+  if (!IsOptSize && Subtarget.isSHLDSlow())
+      return SDValue();
+
+  EVT VT = N->getValueType(0);
+
+  // SHRD does not suppport 8-bit operands
+  if (VT == MVT::i8)
+    return SDValue();
+
+  APInt Mask;
+  uint64_t ShiftAmount;
+  SDValue X, Y;
+
+  // Check for the following pattern:
+  //   (or (and X, HighBitsMask(C)), (srl Y, C))
+  // Do not combine if there are multi-use AND and OR.
+  // It does not result in more performant code.
+  bool Match =
+      sd_match(N, m_Or(m_OneUse(m_And(m_Value(X), m_ConstInt(Mask))),
+                       m_OneUse(m_Shl(m_Value(Y), m_ConstInt(ShiftAmount)))));
+
+  if (!Match)
+    return SDValue();
+
+  // Max bit-width of operands
+  uint64_t MaxMaskBitWidth = VT.getSizeInBits();
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pratyaypande wrote:

Currently using `getScalarSizeInBits()` in the DAGCombiner implementation. Marking as resolved.

https://github.com/llvm/llvm-project/pull/220182