[llvm] [AMDGPU] Scale the frame register in place when lowering scalar frame indices (PR #221972)

[Matt Arsenault via llvm-commits]

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@@ -3419,11 +3419,40 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
       bool IsCopy = MI->getOpcode() == AMDGPU::V_MOV_B32_e32 ||
                     MI->getOpcode() == AMDGPU::V_MOV_B32_e64 ||
                     MI->getOpcode() == AMDGPU::S_MOV_B32;
-      Register ResultReg =
-          IsCopy ? MI->getOperand(0).getReg()
-                 : RS->scavengeRegisterBackwards(*RC, MI, false, 0);
 
       int64_t Offset = FrameInfo.getObjectOffset(Index);
+      int64_t ScaledOffset = -Offset * ST.getWavefrontSize();
+
+      // Scaling FrameReg in place is the last resort when there is nothing to
+      // scavenge. It has to be undone after MI, which is only possible while MI
+      // does not use FrameReg for anything besides the frame index, and while
+      // the offset can be folded back in wave space. A second frame index on MI
+      // would be lowered while FrameReg is still scaled, so keep away from it.
+      bool HasOneFrameIndex =
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arsenm wrote:

I think we just generally don't handle multiple frame indexes. Does the verifier check if there's only one?

https://github.com/llvm/llvm-project/pull/221972