[llvm] [RISCV] Remove TuneHasSingleElementVecFP64 has a configurable tune feature for sifive-180. (PR #222496)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

X180 is a DLEN=64 CPU with 1 vector ALU. By definition it is always single element FP64.

---
Full diff: https://github.com/llvm/llvm-project/pull/222496.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+1-3) 
- (modified) llvm/unittests/TargetParser/RISCVTargetParserTest.cpp (-6) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 38c3c884bf3ee..1ee553e552e6a 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -448,9 +448,7 @@ def SIFIVE_X180 : RISCVProcessorModel<"sifive-x180",
                                        FeatureStdExtZicfilp,
                                        FeatureStdExtZvdot4a8i,
                                        FeatureStdExtZvfbfa],
-                                       SiFiveIntelligenceTuneFeatures> {
-  let ConfigurableTuneFeatures = [TuneHasSingleElementVecFP64];
-}
+                                       SiFiveIntelligenceTuneFeatures>;
 
 defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
                                  TuneConditionalCompressedMoveFusion,
diff --git a/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp b/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
index df3bcc09f2b6a..3dd457dcc509a 100644
--- a/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
@@ -237,12 +237,6 @@ TEST(RISCVTuneFeature, AllProcConfigurableFeatures) {
   EXPECT_TRUE(is_contained(Result, "full-vec-fp64"));
   EXPECT_EQ(Result.size(), 2U);
 
-  Result.clear();
-  RISCV::getCPUConfigurableTuneFeatures("sifive-x180", Result);
-  EXPECT_TRUE(is_contained(Result, "single-element-vec-fp64"));
-  EXPECT_TRUE(is_contained(Result, "full-vec-fp64"));
-  EXPECT_EQ(Result.size(), 2U);
-
   Result.clear();
   RISCV::getCPUConfigurableTuneFeatures("rocket", Result);
   EXPECT_TRUE(Result.empty());

``````````

</details>


https://github.com/llvm/llvm-project/pull/222496