[llvm] 92c1693 - [NFC][AMDGPU] Remove unused MC insts in isPackedSingleSGPR64BitInst (#222463)

[via llvm-commits]

Author: Changpeng Fang
Date: 2026-09-09T19:10:42-07:00
New Revision: 92c1693b574850644535dcb8e18a70fdd115dc94

URL: https://github.com/llvm/llvm-project/commit/92c1693b574850644535dcb8e18a70fdd115dc94
DIFF: https://github.com/llvm/llvm-project/commit/92c1693b574850644535dcb8e18a70fdd115dc94.diff

LOG: [NFC][AMDGPU] Remove unused MC insts in isPackedSingleSGPR64BitInst (#222463)

There is no opsel support for these instructions, and thus we do not have
to manipulate opsel at MC layer. As a result, isPackedSingleSGPR64BitIns
is currently only used before pseudo-expansion. So we remove MC instruction
check inside.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 3a7916b80c37f..88e2d2f485262 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -3688,24 +3688,17 @@ bool isPackedSingleSGPRFP32Inst(unsigned Opc) {
   }
 }
 
+// NOTE: This function is currently only used before pseudo-expansion.
 bool isPackedSingleSGPR64BitInst(unsigned Opc) {
   switch (Opc) {
   case AMDGPU::V_PK_ADD_F64:
-  case AMDGPU::V_PK_ADD_F64_gfx1250:
   case AMDGPU::V_PK_MUL_F64:
-  case AMDGPU::V_PK_MUL_F64_gfx1250:
   case AMDGPU::V_PK_FMA_F64:
-  case AMDGPU::V_PK_FMA_F64_gfx1250:
   case AMDGPU::V_PK_MAX_NUM_F64:
-  case AMDGPU::V_PK_MAX_NUM_F64_gfx1250:
   case AMDGPU::V_PK_MIN_NUM_F64:
-  case AMDGPU::V_PK_MIN_NUM_F64_gfx1250:
   case AMDGPU::V_PK_ADD_NC_U64:
-  case AMDGPU::V_PK_ADD_NC_U64_gfx1250:
   case AMDGPU::V_PK_SUB_NC_U64:
-  case AMDGPU::V_PK_SUB_NC_U64_gfx1250:
   case AMDGPU::V_PK_LSHL_ADD_U64:
-  case AMDGPU::V_PK_LSHL_ADD_U64_gfx1250:
     return true;
   default:
     return false;