[llvm] [AMDGPU][True16][GlobalISel] Update True16 handling for FMA_MIX instructions in GlobalISel (PR #205431)
Domenic Nutile via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 9 12:50:45 PDT 2026
https://github.com/saxlungs updated https://github.com/llvm/llvm-project/pull/205431
>From efc40ac4bb8ec5a4776c2ea7b939cb5fc7a424e5 Mon Sep 17 00:00:00 2001
From: Domenic Nutile <domenic.nutile at gmail.com>
Date: Tue, 23 Jun 2026 16:55:52 -0400
Subject: [PATCH 1/4] [AMDGPU][True16][GlobalISel] Update True16 handling for
FMA_MIX instructions in GlobalISel
The FMA_MIX instructions can extend 16-bit input values, but must have
32-bit registers as operands. This patch handles cases in True16 mode
where the 16-bit input value lives in a VGPR-16 and must be widened.
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 56 +++
llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll | 79 ++--
llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll | 432 ++++++++++++------
llvm/test/CodeGen/AMDGPU/mad-mix.ll | 365 +++++++++++----
4 files changed, 669 insertions(+), 263 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index e4111ba265a7c..d3e2224e47470 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -2895,6 +2895,31 @@ static bool isExtractHiElt(MachineRegisterInfo &MRI, Register In,
return false;
}
+static bool isExtractLoElt(MachineRegisterInfo &MRI, Register In,
+ Register &Out) {
+ // There could be a bitcast between the extraction and its use.
+ In = stripBitCast(In, MRI);
+
+ // The first def of a 2 x 16-bit unmerge is the low half of its source.
+ if (auto *Unmerge = dyn_cast<GUnmerge>(MRI.getVRegDef(In))) {
+ if (Unmerge->getNumDefs() == 2 && Unmerge->getOperand(0).getReg() == In &&
+ MRI.getType(In).getSizeInBits() == 16) {
+ Out = Unmerge->getSourceReg();
+ return true;
+ }
+ }
+
+ // A truncation from 32 to 16 bits keeps the low half in place.
+ Register Trunc;
+ if (mi_match(In, MRI, m_GTrunc(m_Reg(Trunc))) &&
+ MRI.getType(Trunc).getSizeInBits() == 32) {
+ Out = stripBitCast(Trunc, MRI);
+ return true;
+ }
+
+ return false;
+}
+
bool AMDGPUInstructionSelector::selectG_FPEXT(MachineInstr &I) const {
if (!Subtarget->hasSALUFloatInsts())
return false;
@@ -7120,6 +7145,26 @@ AMDGPUInstructionSelector::selectSMRDBufferSgprImm(MachineOperand &Root) const {
[=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedOffset); }}};
}
+// Place a 16-bit source into the low half of a new 32-bit VGPR.
+static Register createVOP3PSrc32FromLo16(Register Src, MachineInstr *InsertPt,
+ MachineRegisterInfo &MRI) {
+ MachineIRBuilder B(*InsertPt);
+
+ // Create an vgpr_16 for the hi16 part using IMPLICIT_DEF
+ Register ImpdefReg = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
+ B.buildInstr(TargetOpcode::IMPLICIT_DEF).addDef(ImpdefReg);
+
+ Register DstReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ B.buildInstr(AMDGPU::REG_SEQUENCE)
+ .addDef(DstReg)
+ .addReg(Src)
+ .addImm(AMDGPU::lo16)
+ .addReg(ImpdefReg)
+ .addImm(AMDGPU::hi16);
+
+ return DstReg;
+}
+
std::pair<Register, unsigned>
AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
bool &Matched) const {
@@ -7161,9 +7206,20 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
Mods |= SISrcMods::OP_SEL_1;
+ // The instruction reads a 32-bit source and selects a half of it, so look
+ // for the 32-bit register the 16-bit value is a half of.
if (isExtractHiElt(*MRI, Src, Src)) {
+ // Src is now the 32-bit source and op_sel picks its high half.
Mods |= SISrcMods::OP_SEL_0;
CheckAbsNeg();
+ } else if (!isExtractLoElt(*MRI, Src, Src)) {
+ // Src is genuinely 16 bits wide. With real true16 instructions a 16-bit
+ // VALU value lives in a VGPR_16, which the mix instructions cannot read,
+ // so widen it. 16-bit SALU values already occupy a full SGPR_32.
+ const RegisterBank *SrcRB = RBI.getRegBank(Src, *MRI, TRI);
+ if (Subtarget->useRealTrue16Insts() && SrcRB &&
+ SrcRB->getID() == AMDGPU::VGPRRegBankID)
+ Src = createVOP3PSrc32FromLo16(Src, Root.getParent(), *MRI);
}
Matched = true;
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
index 7fd10a09d032d..db028d4364f35 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
@@ -5,8 +5,7 @@
; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,SDAG-VI %s
; RUN: llc -mtriple=amdgpu7.01 < %s | FileCheck -check-prefixes=SDAG-CI %s
-; FIXME-TRUE16. fix gisel
-; XUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
; RUN: llc -global-isel -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9,GISEL-GFX9 %s
; RUN: llc -global-isel -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
@@ -126,14 +125,21 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo(half %src0, half %s
; SDAG-CI-NEXT: v_or_b32_e32 v0, 0x3c00, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v3, 0x3c00
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:
+; GISEL-GFX11-TRUE16: ; %bb.0:
+; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3c00
+; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:
+; GISEL-GFX11-FAKE16: ; %bb.0:
+; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0x3c00
+; GISEL-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:
; GISEL-VI: ; %bb.0:
@@ -301,14 +307,23 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, ha
; SDAG-CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GISEL-GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
+; GISEL-GFX11-TRUE16: ; %bb.0:
+; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l
+; GISEL-GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
+; GISEL-GFX11-FAKE16: ; %bb.0:
+; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GISEL-GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GISEL-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
; GISEL-GFX9: ; %bb.0:
@@ -473,15 +488,23 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %
; SDAG-CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX11-NEXT: v_and_b32_e64 v1, 0xffff, s0
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
-; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
+; GISEL-GFX11-TRUE16: ; %bb.0:
+; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v0
+; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
+; GISEL-GFX11-FAKE16: ; %bb.0:
+; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX11-FAKE16-NEXT: v_and_b32_e64 v1, 0xffff, s0
+; GISEL-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GISEL-GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GISEL-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
; GISEL-GFX9: ; %bb.0:
@@ -737,5 +760,3 @@ declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #
attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
attributes #1 = { nounwind readnone speculatable }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GISEL-GFX11-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
index 2361da33368b2..11494c1e2126b 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
@@ -6,8 +6,7 @@
; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,SDAG-VI %s
; RUN: llc -mtriple=amdgpu7.01 < %s | FileCheck -check-prefixes=SDAG-CI %s
-; FIXME-TRUE16. enable gisel
-; XUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
; RUN: llc -global-isel -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
; RUN: llc -global-isel -mtriple=amdgpu9.06 < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
@@ -388,13 +387,21 @@ define half @v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt(half %src0, half %src
; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt:
; GISEL-CI: ; %bb.0:
@@ -487,14 +494,23 @@ define <2 x half> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half
; SDAG-CI-NEXT: v_or_b32_e32 v0, v1, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-VI-LABEL: v_mad_mix_v2f32:
; GISEL-VI: ; %bb.0:
@@ -628,17 +644,27 @@ define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half
; SDAG-CI-NEXT: v_or_b32_e32 v0, v2, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v3f32:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_and_b32 v1, 0xffff, v1
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v3f32:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v6
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v3f32:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_and_b32 v1, 0xffff, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v3f32:
; GISEL-GFX900: ; %bb.0:
@@ -829,17 +855,29 @@ define <4 x half> @v_mad_mix_v4f32(<4 x half> %src0, <4 x half> %src1, <4 x half
; SDAG-CI-NEXT: v_or_b32_e32 v1, v3, v4
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v4f32:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v7, v1, v3, v5 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v4f32:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v2, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v6
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v4f32:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v7, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v4f32:
; GISEL-GFX900: ; %bb.0:
@@ -1024,14 +1062,23 @@ define <2 x half> @v_mad_mix_v2f32_clamp_postcvt(<2 x half> %src0, <2 x half> %s
; SDAG-CI-NEXT: v_or_b32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_clamp_postcvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_clamp_postcvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_clamp_postcvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-VI-LABEL: v_mad_mix_v2f32_clamp_postcvt:
; GISEL-VI: ; %bb.0:
@@ -1212,18 +1259,29 @@ define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %s
; SDAG-CI-NEXT: v_or_b32_e32 v0, v0, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v3f32_clamp_postcvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_and_b32 v1, 0xffff, v1
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GISEL-GFX1100-NEXT: v_pk_max_f16 v1, v1, v1 clamp
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v3f32_clamp_postcvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1 clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v3f32_clamp_postcvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_and_b32 v1, 0xffff, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GISEL-GFX1100-FAKE16-NEXT: v_pk_max_f16 v1, v1, v1 clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v3f32_clamp_postcvt:
; GISEL-GFX900: ; %bb.0:
@@ -1470,17 +1528,29 @@ define <4 x half> @v_mad_mix_v4f32_clamp_postcvt(<4 x half> %src0, <4 x half> %s
; SDAG-CI-NEXT: v_or_b32_e32 v1, v3, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v4f32_clamp_postcvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v7, v1, v3, v5 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v4f32_clamp_postcvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v2, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v6
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v4f32_clamp_postcvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v7, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-VI-LABEL: v_mad_mix_v4f32_clamp_postcvt:
; GISEL-VI: ; %bb.0:
@@ -1664,18 +1734,29 @@ define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_lo(<2 x half> %src0, <2 x half>
; SDAG-CI-NEXT: v_or_b32_e32 v0, v1, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_clamp_postcvt_lo:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v4, v3
-; GISEL-GFX1100-NEXT: v_max_f16_e64 v3, v3, v3 clamp
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v4, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_bfe_u32 v0, v3, 0, 16
-; GISEL-GFX1100-NEXT: v_and_or_b32 v0, 0xffff0000, v4, v0
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_clamp_postcvt_lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v4, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v4, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_bfe_u32 v0, v3, 0, 16
+; GISEL-GFX1100-TRUE16-NEXT: v_and_or_b32 v0, 0xffff0000, v4, v0
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_clamp_postcvt_lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v4, v3
+; GISEL-GFX1100-FAKE16-NEXT: v_max_f16_e64 v3, v3, v3 clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v4, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_bfe_u32 v0, v3, 0, 16
+; GISEL-GFX1100-FAKE16-NEXT: v_and_or_b32 v0, 0xffff0000, v4, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32_clamp_postcvt_lo:
; GISEL-GFX900: ; %bb.0:
@@ -1839,18 +1920,31 @@ define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_hi(<2 x half> %src0, <2 x half>
; SDAG-CI-NEXT: v_or_b32_e32 v0, v1, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_clamp_postcvt_hi:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v4, v0, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_bfe_u32 v3, v3, 0, 16
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v4, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_lshlrev_b32_e32 v0, 16, v3
-; GISEL-GFX1100-NEXT: v_and_or_b32 v0, 0xffff, v4, v0
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_clamp_postcvt_hi:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v4, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v4, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_bfe_u32 v3, v3, 0, 16
+; GISEL-GFX1100-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v3
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_and_or_b32 v0, 0xffff, v4, v0
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_clamp_postcvt_hi:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v4, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_bfe_u32 v3, v3, 0, 16
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v4, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v3
+; GISEL-GFX1100-FAKE16-NEXT: v_and_or_b32 v0, 0xffff, v4, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32_clamp_postcvt_hi:
; GISEL-GFX900: ; %bb.0:
@@ -2022,17 +2116,27 @@ define <2 x half> @v_mad_mix_v2f32_clamp_precvt(<2 x half> %src0, <2 x half> %sr
; SDAG-CI-NEXT: v_or_b32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_clamp_precvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v1, v3
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_pack_b32_f16 v0, v1, v0
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_clamp_precvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v3
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_clamp_precvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v3
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32_clamp_precvt:
; GISEL-GFX900: ; %bb.0:
@@ -2203,22 +2307,35 @@ define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %sr
; SDAG-CI-NEXT: v_or_b32_e32 v0, v0, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v3f32_clamp_precvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v2, v3
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX1100-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_pack_b32_f16 v0, v2, v0
-; GISEL-GFX1100-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v3f32_clamp_precvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v6
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v3f32_clamp_precvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v3
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GISEL-GFX1100-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_pack_b32_f16 v0, v2, v0
+; GISEL-GFX1100-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v3f32_clamp_precvt:
; GISEL-GFX900: ; %bb.0:
@@ -2433,23 +2550,38 @@ define <4 x half> @v_mad_mix_v4f32_clamp_precvt(<4 x half> %src0, <4 x half> %sr
; SDAG-CI-NEXT: v_or_b32_e32 v1, v1, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v4f32_clamp_precvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v2, v1, v3, v5 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v3, v6
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_pack_b32_f16 v0, v3, v0
-; GISEL-GFX1100-NEXT: v_pack_b32_f16 v1, v2, v1
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v4f32_clamp_precvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v4, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v6
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v4
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v3
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v4f32_clamp_precvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v6
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_pack_b32_f16 v0, v3, v0
+; GISEL-GFX1100-FAKE16-NEXT: v_pack_b32_f16 v1, v2, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v4f32_clamp_precvt:
; GISEL-GFX900: ; %bb.0:
@@ -2604,13 +2736,21 @@ define i32 @mixlo_zext(float %src0, float %src1, float %src2) #0 {
; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: mixlo_zext:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: mixlo_zext:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: mixlo_zext:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: mixlo_zext:
; GISEL-CI: ; %bb.0:
@@ -2838,4 +2978,4 @@ declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #
attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
attributes #1 = { nounwind readnone speculatable }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GISEL-GFX1100-FAKE16: {{.*}}
+; GISEL-GFX1100: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix.ll b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
index 5969309df7294..55cbdc07fbe52 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
@@ -7,8 +7,7 @@
; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,SDAG-VI %s
; RUN: llc -mtriple=amdgpu7.01 < %s | FileCheck -check-prefixes=CI,SDAG-CI %s
-; FIXME-TRUE16. enable gisel
-; XUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
; RUN: llc -global-isel -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
; RUN: llc -global-isel -mtriple=amdgpu9.06 < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
@@ -2224,14 +2223,22 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo(i32 %src0.arg, half %
; SDAG-CI-NEXT: v_mac_f32_e32 v0, v3, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.h
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo:
; GISEL-CI: ; %bb.0:
@@ -2254,11 +2261,11 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo(i32 %src0.arg, half %
}
define float @v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo:
; GFX900: ; %bb.0:
@@ -2299,6 +2306,20 @@ define float @v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo(i32 %src0.arg, half %src1
; CI-NEXT: v_cvt_f32_f16_e32 v0, v2
; CI-NEXT: v_mac_f32_e32 v0, v3, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%src0 = extractelement <2 x half> %src0.arg.bc, i32 1
%src0.abs = call half @llvm.fabs.f16(half %src0)
@@ -2310,11 +2331,11 @@ define float @v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo(i32 %src0.arg, half %src1
}
define float @v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
; GFX900: ; %bb.0:
@@ -2356,6 +2377,20 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half
; SDAG-CI-NEXT: v_mac_f32_e32 v0, v3, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
; GISEL-GFX9GEN: ; %bb.0:
; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2397,11 +2432,11 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half
}
define float @v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
; GFX900: ; %bb.0:
@@ -2443,6 +2478,20 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo(i32 %src0.arg, half
; SDAG-CI-NEXT: v_mac_f32_e32 v0, v3, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
; GISEL-GFX9GEN: ; %bb.0:
; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2484,11 +2533,11 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo(i32 %src0.arg, half
}
define float @v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
; GFX900: ; %bb.0:
@@ -2530,6 +2579,20 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo(i32 %src0.arg,
; SDAG-CI-NEXT: v_mac_f32_e32 v0, v3, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -|v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
; GISEL-GFX9GEN: ; %bb.0:
; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3759,14 +3822,22 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo(i32 %src0.arg, half %sr
; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.h
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo:
; GISEL-CI: ; %bb.0:
@@ -3787,11 +3858,11 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo(i32 %src0.arg, half %sr
}
define float @v_mad_mix_f32_precvtabsf16hi_add_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo:
; GFX900: ; %bb.0:
@@ -3831,6 +3902,20 @@ define float @v_mad_mix_f32_precvtabsf16hi_add_f16lo(i32 %src0.arg, half %src1)
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_add_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%src0 = extractelement <2 x half> %src0.arg.bc, i32 1
%src0.abs = call half @llvm.fabs.f16(half %src0)
@@ -3841,11 +3926,11 @@ define float @v_mad_mix_f32_precvtabsf16hi_add_f16lo(i32 %src0.arg, half %src1)
}
define float @v_mad_mix_f32_preextractfneg_f16hi_add_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -3886,6 +3971,20 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_add_f16lo(i32 %src0.arg, half %
; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3932,11 +4031,11 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_add_f16lo(i32 %src0.arg, half %
}
define float @v_mad_mix_f32_preextractfabs_f16hi_add_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -3977,6 +4076,20 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_add_f16lo(i32 %src0.arg, half %
; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4023,11 +4136,11 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_add_f16lo(i32 %src0.arg, half %
}
define float @v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -4068,6 +4181,20 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo(i32 %src0.arg, ha
; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5239,14 +5366,22 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo(i32 %src0.arg, half %sr
; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.h
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo:
; GISEL-CI: ; %bb.0:
@@ -5267,11 +5402,11 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo(i32 %src0.arg, half %sr
}
define float @v_mad_mix_f32_precvtabsf16hi_mul_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo:
; GFX900: ; %bb.0:
@@ -5311,6 +5446,20 @@ define float @v_mad_mix_f32_precvtabsf16hi_mul_f16lo(i32 %src0.arg, half %src1)
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_mul_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%src0 = extractelement <2 x half> %src0.arg.bc, i32 1
%src0.abs = call half @llvm.fabs.f16(half %src0)
@@ -5321,11 +5470,11 @@ define float @v_mad_mix_f32_precvtabsf16hi_mul_f16lo(i32 %src0.arg, half %src1)
}
define float @v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -5366,6 +5515,20 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo(i32 %src0.arg, half %
; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5412,11 +5575,11 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo(i32 %src0.arg, half %
}
define float @v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -5457,6 +5620,20 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo(i32 %src0.arg, half %
; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5503,11 +5680,11 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo(i32 %src0.arg, half %
}
define float @v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -5548,6 +5725,20 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo(i32 %src0.arg, ha
; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5894,5 +6085,3 @@ declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #
attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
attributes #1 = { nounwind denormal_fpenv(float: ieee|ieee) }
attributes #2 = { nounwind readnone speculatable }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GISEL-GFX1100-FAKE16: {{.*}}
>From 56676a97aafd2866a44895679ba5afc0ec54615f Mon Sep 17 00:00:00 2001
From: Domenic Nutile <domenic.nutile at gmail.com>
Date: Wed, 9 Sep 2026 11:07:37 -0400
Subject: [PATCH 2/4] Refactor widening to occur in complex renderer functions
when adding registers, a la copyToVGPRIfSrcFolded
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 78 +++++++++++--------
.../Target/AMDGPU/AMDGPUInstructionSelector.h | 2 +
2 files changed, 48 insertions(+), 32 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index d3e2224e47470..ada783906980c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -4752,6 +4752,34 @@ Register AMDGPUInstructionSelector::copyToVGPRIfSrcFolded(
return Src;
}
+/// The mix instructions read 32-bit sources. With real true16 instructions a
+/// 16-bit VALU value lives in a VGPR_16, which they cannot read, so place it in
+/// the low half of a new 32-bit VGPR.
+Register AMDGPUInstructionSelector::widenMadMixSrcIfVGPR16(
+ Register Src, MachineInstr *InsertPt) const {
+ if (!Subtarget->useRealTrue16Insts() || MRI->getType(Src) != LLT::scalar(16))
+ return Src;
+
+ const RegisterBank *SrcRB = RBI.getRegBank(Src, *MRI, TRI);
+ if (!SrcRB || SrcRB->getID() != AMDGPU::VGPRRegBankID)
+ return Src;
+
+ MachineIRBuilder B(*InsertPt);
+
+ Register ImpDefReg = MRI->createVirtualRegister(&AMDGPU::VGPR_16RegClass);
+ B.buildInstr(TargetOpcode::IMPLICIT_DEF).addDef(ImpDefReg);
+
+ Register DstReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ B.buildInstr(AMDGPU::REG_SEQUENCE)
+ .addDef(DstReg)
+ .addReg(Src)
+ .addImm(AMDGPU::lo16)
+ .addReg(ImpDefReg)
+ .addImm(AMDGPU::hi16);
+
+ return DstReg;
+}
+
///
/// This will select either an SGPR or VGPR operand and will save us from
/// having to write an extra tablegen pattern.
@@ -7145,26 +7173,6 @@ AMDGPUInstructionSelector::selectSMRDBufferSgprImm(MachineOperand &Root) const {
[=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedOffset); }}};
}
-// Place a 16-bit source into the low half of a new 32-bit VGPR.
-static Register createVOP3PSrc32FromLo16(Register Src, MachineInstr *InsertPt,
- MachineRegisterInfo &MRI) {
- MachineIRBuilder B(*InsertPt);
-
- // Create an vgpr_16 for the hi16 part using IMPLICIT_DEF
- Register ImpdefReg = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
- B.buildInstr(TargetOpcode::IMPLICIT_DEF).addDef(ImpdefReg);
-
- Register DstReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
- B.buildInstr(AMDGPU::REG_SEQUENCE)
- .addDef(DstReg)
- .addReg(Src)
- .addImm(AMDGPU::lo16)
- .addReg(ImpdefReg)
- .addImm(AMDGPU::hi16);
-
- return DstReg;
-}
-
std::pair<Register, unsigned>
AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
bool &Matched) const {
@@ -7212,14 +7220,12 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
// Src is now the 32-bit source and op_sel picks its high half.
Mods |= SISrcMods::OP_SEL_0;
CheckAbsNeg();
- } else if (!isExtractLoElt(*MRI, Src, Src)) {
- // Src is genuinely 16 bits wide. With real true16 instructions a 16-bit
- // VALU value lives in a VGPR_16, which the mix instructions cannot read,
- // so widen it. 16-bit SALU values already occupy a full SGPR_32.
- const RegisterBank *SrcRB = RBI.getRegBank(Src, *MRI, TRI);
- if (Subtarget->useRealTrue16Insts() && SrcRB &&
- SrcRB->getID() == AMDGPU::VGPRRegBankID)
- Src = createVOP3PSrc32FromLo16(Src, Root.getParent(), *MRI);
+ } else {
+ // op_sel already picks the low half, so use the 32-bit source directly if
+ // the 16-bit value is the low half of one. Otherwise Src is genuinely 16
+ // bits wide and widenMadMixSrcIfVGPR16 widens it when the operand is
+ // rendered.
+ isExtractLoElt(*MRI, Src, Src);
}
Matched = true;
@@ -7239,7 +7245,9 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsExt(
return {};
return {{
- [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
+ [=](MachineInstrBuilder &MIB) {
+ MIB.addReg(widenMadMixSrcIfVGPR16(Src, MIB));
+ },
[=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
}};
}
@@ -7252,7 +7260,9 @@ AMDGPUInstructionSelector::selectVOP3PMadMixMods(MachineOperand &Root) const {
std::tie(Src, Mods) = selectVOP3PMadMixModsImpl(Root, Matched);
return {{
- [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
+ [=](MachineInstrBuilder &MIB) {
+ MIB.addReg(widenMadMixSrcIfVGPR16(Src, MIB));
+ },
[=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
}};
}
@@ -7268,7 +7278,9 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsExtNeg(
return {};
return {{
- [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
+ [=](MachineInstrBuilder &MIB) {
+ MIB.addReg(widenMadMixSrcIfVGPR16(Src, MIB));
+ },
[=](MachineInstrBuilder &MIB) {
MIB.addImm(Mods ^ SISrcMods::NEG);
} // src_mods
@@ -7284,7 +7296,9 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsNeg(
std::tie(Src, Mods) = selectVOP3PMadMixModsImpl(Root, Matched);
return {{
- [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
+ [=](MachineInstrBuilder &MIB) {
+ MIB.addReg(widenMadMixSrcIfVGPR16(Src, MIB));
+ },
[=](MachineInstrBuilder &MIB) {
MIB.addImm(Mods ^ SISrcMods::NEG);
} // src_mods
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
index ce3a090651d0e..b84b970a3c7fa 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
@@ -168,6 +168,8 @@ class AMDGPUInstructionSelector final : public InstructionSelector {
MachineOperand Root, MachineInstr *InsertPt,
bool ForceVGPR = false) const;
+ Register widenMadMixSrcIfVGPR16(Register Src, MachineInstr *InsertPt) const;
+
InstructionSelector::ComplexRendererFns
selectVCSRC(MachineOperand &Root) const;
>From 6b4b338e4ffd0ace37ea896fafa5ff2a621405f1 Mon Sep 17 00:00:00 2001
From: Domenic Nutile <domenic.nutile at gmail.com>
Date: Wed, 9 Sep 2026 12:13:43 -0400
Subject: [PATCH 3/4] Rename helper function to be generic
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 25 +++++++------------
.../Target/AMDGPU/AMDGPUInstructionSelector.h | 2 +-
2 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index ada783906980c..758e66aa12cea 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -4752,11 +4752,12 @@ Register AMDGPUInstructionSelector::copyToVGPRIfSrcFolded(
return Src;
}
-/// The mix instructions read 32-bit sources. With real true16 instructions a
+/// Some instructions must have 32-bit sources. With real true16 instructions a
/// 16-bit VALU value lives in a VGPR_16, which they cannot read, so place it in
/// the low half of a new 32-bit VGPR.
-Register AMDGPUInstructionSelector::widenMadMixSrcIfVGPR16(
- Register Src, MachineInstr *InsertPt) const {
+Register
+AMDGPUInstructionSelector::widenSrcIfVGPR16(Register Src,
+ MachineInstr *InsertPt) const {
if (!Subtarget->useRealTrue16Insts() || MRI->getType(Src) != LLT::scalar(16))
return Src;
@@ -7223,7 +7224,7 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
} else {
// op_sel already picks the low half, so use the 32-bit source directly if
// the 16-bit value is the low half of one. Otherwise Src is genuinely 16
- // bits wide and widenMadMixSrcIfVGPR16 widens it when the operand is
+ // bits wide and widenSrcIfVGPR16 widens it when the operand is
// rendered.
isExtractLoElt(*MRI, Src, Src);
}
@@ -7245,9 +7246,7 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsExt(
return {};
return {{
- [=](MachineInstrBuilder &MIB) {
- MIB.addReg(widenMadMixSrcIfVGPR16(Src, MIB));
- },
+ [=](MachineInstrBuilder &MIB) { MIB.addReg(widenSrcIfVGPR16(Src, MIB)); },
[=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
}};
}
@@ -7260,9 +7259,7 @@ AMDGPUInstructionSelector::selectVOP3PMadMixMods(MachineOperand &Root) const {
std::tie(Src, Mods) = selectVOP3PMadMixModsImpl(Root, Matched);
return {{
- [=](MachineInstrBuilder &MIB) {
- MIB.addReg(widenMadMixSrcIfVGPR16(Src, MIB));
- },
+ [=](MachineInstrBuilder &MIB) { MIB.addReg(widenSrcIfVGPR16(Src, MIB)); },
[=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
}};
}
@@ -7278,9 +7275,7 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsExtNeg(
return {};
return {{
- [=](MachineInstrBuilder &MIB) {
- MIB.addReg(widenMadMixSrcIfVGPR16(Src, MIB));
- },
+ [=](MachineInstrBuilder &MIB) { MIB.addReg(widenSrcIfVGPR16(Src, MIB)); },
[=](MachineInstrBuilder &MIB) {
MIB.addImm(Mods ^ SISrcMods::NEG);
} // src_mods
@@ -7296,9 +7291,7 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsNeg(
std::tie(Src, Mods) = selectVOP3PMadMixModsImpl(Root, Matched);
return {{
- [=](MachineInstrBuilder &MIB) {
- MIB.addReg(widenMadMixSrcIfVGPR16(Src, MIB));
- },
+ [=](MachineInstrBuilder &MIB) { MIB.addReg(widenSrcIfVGPR16(Src, MIB)); },
[=](MachineInstrBuilder &MIB) {
MIB.addImm(Mods ^ SISrcMods::NEG);
} // src_mods
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
index b84b970a3c7fa..71e815bf122d8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
@@ -168,7 +168,7 @@ class AMDGPUInstructionSelector final : public InstructionSelector {
MachineOperand Root, MachineInstr *InsertPt,
bool ForceVGPR = false) const;
- Register widenMadMixSrcIfVGPR16(Register Src, MachineInstr *InsertPt) const;
+ Register widenSrcIfVGPR16(Register Src, MachineInstr *InsertPt) const;
InstructionSelector::ComplexRendererFns
selectVCSRC(MachineOperand &Root) const;
>From b22e6cd2f0a37efde3e903eb7d2190ca6f488a53 Mon Sep 17 00:00:00 2001
From: Domenic Nutile <domenic.nutile at gmail.com>
Date: Wed, 9 Sep 2026 15:49:04 -0400
Subject: [PATCH 4/4] Re-enable fold for true16 that was disabled earlier,
since this PR fixes it
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 2 +-
.../AMDGPU/GlobalISel/fma-mix-true16.ll | 21 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll | 439 +++++++++---------
3 files changed, 227 insertions(+), 235 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 758e66aa12cea..01d3657cd2f04 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -7183,7 +7183,7 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
unsigned Mods;
std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
- if (!STI.useRealTrue16Insts() && mi_match(Src, *MRI, m_GFPExt(m_Reg(Src)))) {
+ if (mi_match(Src, *MRI, m_GFPExt(m_Reg(Src)))) {
assert(MRI->getType(Src) == LLT::scalar(16));
// Only change Src if src modifier could be gained. In such cases new Src
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll
index be15af54b0429..1927647ade200 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll
@@ -3,18 +3,15 @@
; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
; With real true16 instructions s16 values live in 16-bit register classes,
-; and folding an fpext into a mix instruction's 32-bit source operand leaves
-; an unselectable 16-bit def. Check that the fold is skipped instead of
-; crashing the selector.
+; which the mix instructions cannot read. Check that folding an fpext into a
+; mix instruction's 32-bit source operand widens such a source instead of
+; leaving an unselectable 16-bit def, so that true16 matches fake16 here.
define float @v_mul_f32_fpext_f16(half %x, half %y) {
; GFX11-TRUE16-LABEL: v_mul_f32_fpext_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_mul_f32_fpext_f16:
@@ -32,10 +29,7 @@ define float @v_fma_f32_fpext_f16(half %x, half %y, float %z) {
; GFX11-TRUE16-LABEL: v_fma_f32_fpext_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v0, v0, v1, v2
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fma_f32_fpext_f16:
@@ -53,10 +47,7 @@ define float @v_fma_f32_fpext_fneg_f16(half %x, half %y, float %z) {
; GFX11-TRUE16-LABEL: v_fma_f32_fpext_fneg_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v0, v0, v1, v2
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,0]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fma_f32_fpext_fneg_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
index c62344f055d7a..384868d0e706f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
@@ -699,10 +699,10 @@ define half @v_pow_f16(half %x, half %y) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v1
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v4
; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
@@ -714,23 +714,25 @@ define half @v_pow_f16(half %x, half %y) {
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v4, v2
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v3
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v6, v3
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mov_b32 v3, 0.5
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v3, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v1
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v6, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v3
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0
; GFX11-TRUE16-NEXT: s_xor_b32 s0, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -1094,76 +1096,76 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: v_dual_mul_f32 v9, 0.5, v1 :: v_dual_and_b32 v10, 0x80000000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0x80000000, v0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v1, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_mul_dx9_zero_f32 v3, v7, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0x80000000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.h
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v7, v3 :: v_dual_mul_dx9_zero_f32 v4, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, 0.5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v9
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v4, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v5
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, 0.5, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0x80000000, v2
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v10, v1, v6, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v7
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v10
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v2, v5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v7
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v8, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(TRANS32_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v2, v5
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v3, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, v13
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v12, v1
; GFX11-TRUE16-NEXT: s_xor_b32 s6, vcc_lo, exec_lo
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v8, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v3
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v5
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v3, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v7, v5
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v3, v1
-; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v0, v10
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, v11
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, s2
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v9
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v14
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, s1, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_v2f16:
@@ -1564,14 +1566,10 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, 0.5, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
@@ -1581,65 +1579,67 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v8, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0x80000000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
-; GFX11-TRUE16-NEXT: s_xor_b32 s6, s1, exec_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v1, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_mul_dx9_zero_f32 v3, v7, v3
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.h
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v7, v3 :: v_dual_mul_dx9_zero_f32 v4, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0x80000000, v0
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v1, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v5
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, 0.5, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v4, v2
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v1, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, 0.5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v10, v1, v6, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v9
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v6
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v7, v5
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, v10
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v10
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v6, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v8, v10
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v9, v5
+; GFX11-TRUE16-NEXT: s_xor_b32 s6, s1, exec_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0x80000000, v2
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v11, v1
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v3, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v3, v0, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, v1, s0
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, vcc_lo, exec_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, s2
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, v7
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, exec_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v4, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_lhs:
@@ -2042,73 +2042,74 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v5.l
; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, 0.5, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v1, v4
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v7 :: v_dual_mov_b32 v7, 0.5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v5.h
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0x80000000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v8, v3 :: v_dual_mul_dx9_zero_f32 v4, v6, v4
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v13, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0x80000000, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v4, v6
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v5
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, 0.5, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v6, v1
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, v11
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x80000000, v0
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v0, v3
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v3, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v7
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v3, v5
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v10
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v12, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v13, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v9 :: v_dual_add_f32 v4, v4, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0x80000000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v3
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v3, v1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v10, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v3, v1
+; GFX11-TRUE16-NEXT: s_xor_b32 s6, s0, exec_lo
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v0, v9
-; GFX11-TRUE16-NEXT: s_xor_b32 s6, vcc_lo, exec_lo
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v3, v5
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v7, v10
-; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v2, v4
-; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, v8
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v2, v0
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v4, v11
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, s2
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v7
+; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v1, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -2515,78 +2516,78 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v5.l
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0x80000000, v2
; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: v_dual_mul_f32 v9, 0.5, v1 :: v_dual_and_b32 v10, 0x80000000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v1, v4
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v7 :: v_dual_mov_b32 v7, 0.5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_mul_dx9_zero_f32 v3, v7, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0x80000000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v5.h
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v8, v3 :: v_dual_mul_dx9_zero_f32 v4, v6, v4
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v9
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v4, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v5
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, 0.5, v7
-; GFX11-TRUE16-NEXT: s_xor_b32 s6, vcc_lo, exec_lo
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v8, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v3
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v5
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v3, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v7, v5
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v3, v1
-; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v0, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v9 :: v_dual_add_f32 v4, v4, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x80000000, v0
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v8
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v9, v8
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v10, v5
+; GFX11-TRUE16-NEXT: s_xor_b32 s6, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, v11
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v4, v13
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, s2
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v2, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, v3, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, s2, exec_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
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