[llvm] [RISCV] Add RV64 RUN lines to orc-b-patterns.ll. NFC (PR #222424)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 9 11:52:30 PDT 2026
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/222424
None
>From d888294b6865469083d93846a5d3e72f60943478 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 9 Sep 2026 11:51:02 -0700
Subject: [PATCH] [RISCV] Add RV64 RUN lines to orc-b-patterns.ll. NFC
---
llvm/test/CodeGen/RISCV/orc-b-patterns.ll | 594 +++++++++++++++++-----
1 file changed, 459 insertions(+), 135 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/orc-b-patterns.ll b/llvm/test/CodeGen/RISCV/orc-b-patterns.ll
index 3f0ae7d1c35f8..9aa2fb809c5d6 100644
--- a/llvm/test/CodeGen/RISCV/orc-b-patterns.ll
+++ b/llvm/test/CodeGen/RISCV/orc-b-patterns.ll
@@ -1,8 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I
+; RUN: | FileCheck %s -check-prefixes=I,RV32I
; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB
+; RUN: | FileCheck %s -check-prefixes=ZBB,RV32ZBB
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefixes=I,RV64I
+; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefixes=ZBB,RV64ZBB
define i32 @orc_b_i32_mul255(i32 %x) nounwind {
; RV32I-LABEL: orc_b_i32_mul255:
@@ -14,13 +18,22 @@ define i32 @orc_b_i32_mul255(i32 %x) nounwind {
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: orc_b_i32_mul255:
-; RV32ZBB: # %bb.0: # %entry
-; RV32ZBB-NEXT: lui a1, 4112
-; RV32ZBB-NEXT: addi a1, a1, 257
-; RV32ZBB-NEXT: and a0, a0, a1
-; RV32ZBB-NEXT: orc.b a0, a0
-; RV32ZBB-NEXT: ret
+; ZBB-LABEL: orc_b_i32_mul255:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: lui a1, 4112
+; ZBB-NEXT: addi a1, a1, 257
+; ZBB-NEXT: and a0, a0, a1
+; ZBB-NEXT: orc.b a0, a0
+; ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_mul255:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a1, 4112
+; RV64I-NEXT: addi a1, a1, 257
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a1, a0, 8
+; RV64I-NEXT: subw a0, a1, a0
+; RV64I-NEXT: ret
entry:
%and = and i32 %x, 16843009
%mul = mul i32 %and, 255
@@ -38,13 +51,22 @@ define i32 @orc_b_i32_sub_shl8x_x_lsb(i32 %x) {
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_lsb:
-; RV32ZBB: # %bb.0: # %entry
-; RV32ZBB-NEXT: lui a1, 4112
-; RV32ZBB-NEXT: addi a1, a1, 257
-; RV32ZBB-NEXT: and a0, a0, a1
-; RV32ZBB-NEXT: orc.b a0, a0
-; RV32ZBB-NEXT: ret
+; ZBB-LABEL: orc_b_i32_sub_shl8x_x_lsb:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: lui a1, 4112
+; ZBB-NEXT: addi a1, a1, 257
+; ZBB-NEXT: and a0, a0, a1
+; ZBB-NEXT: orc.b a0, a0
+; ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_shl8x_x_lsb:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a1, 4112
+; RV64I-NEXT: addi a1, a1, 257
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a1, a0, 8
+; RV64I-NEXT: subw a0, a1, a0
+; RV64I-NEXT: ret
entry:
%and = and i32 %x, 16843009
%sub = mul i32 %and, 255
@@ -52,24 +74,24 @@ entry:
}
define i32 @orc_b_i32_sub_shl8x_x_lsb_preshifted(i32 %x){
-; RV32I-LABEL: orc_b_i32_sub_shl8x_x_lsb_preshifted:
-; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: lui a1, 16
-; RV32I-NEXT: srli a0, a0, 11
-; RV32I-NEXT: addi a1, a1, 257
-; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: slli a1, a0, 8
-; RV32I-NEXT: sub a0, a1, a0
-; RV32I-NEXT: ret
+; I-LABEL: orc_b_i32_sub_shl8x_x_lsb_preshifted:
+; I: # %bb.0: # %entry
+; I-NEXT: lui a1, 16
+; I-NEXT: srli a0, a0, 11
+; I-NEXT: addi a1, a1, 257
+; I-NEXT: and a0, a0, a1
+; I-NEXT: slli a1, a0, 8
+; I-NEXT: sub a0, a1, a0
+; I-NEXT: ret
;
-; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_lsb_preshifted:
-; RV32ZBB: # %bb.0: # %entry
-; RV32ZBB-NEXT: lui a1, 16
-; RV32ZBB-NEXT: srli a0, a0, 11
-; RV32ZBB-NEXT: addi a1, a1, 257
-; RV32ZBB-NEXT: and a0, a0, a1
-; RV32ZBB-NEXT: orc.b a0, a0
-; RV32ZBB-NEXT: ret
+; ZBB-LABEL: orc_b_i32_sub_shl8x_x_lsb_preshifted:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: lui a1, 16
+; ZBB-NEXT: srli a0, a0, 11
+; ZBB-NEXT: addi a1, a1, 257
+; ZBB-NEXT: and a0, a0, a1
+; ZBB-NEXT: orc.b a0, a0
+; ZBB-NEXT: ret
entry:
%shr = lshr i32 %x, 11
%and = and i32 %shr, 16843009
@@ -89,13 +111,23 @@ define i32 @orc_b_i32_sub_shl8x_x_b1(i32 %x) {
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1:
-; RV32ZBB: # %bb.0: # %entry
-; RV32ZBB-NEXT: lui a1, 8224
-; RV32ZBB-NEXT: addi a1, a1, 514
-; RV32ZBB-NEXT: and a0, a0, a1
-; RV32ZBB-NEXT: orc.b a0, a0
-; RV32ZBB-NEXT: ret
+; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: lui a1, 8224
+; ZBB-NEXT: addi a1, a1, 514
+; ZBB-NEXT: and a0, a0, a1
+; ZBB-NEXT: orc.b a0, a0
+; ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b1:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a1, 8224
+; RV64I-NEXT: addi a1, a1, 514
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a1, a0, 7
+; RV64I-NEXT: srli a0, a0, 1
+; RV64I-NEXT: subw a0, a1, a0
+; RV64I-NEXT: ret
entry:
%and = and i32 %x, 33686018
%shl = shl i32 %and, 7
@@ -116,13 +148,23 @@ define i32 @orc_b_i32_sub_shl8x_x_b2(i32 %x) {
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b2:
-; RV32ZBB: # %bb.0: # %entry
-; RV32ZBB-NEXT: lui a1, 16448
-; RV32ZBB-NEXT: addi a1, a1, 1028
-; RV32ZBB-NEXT: and a0, a0, a1
-; RV32ZBB-NEXT: orc.b a0, a0
-; RV32ZBB-NEXT: ret
+; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b2:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: lui a1, 16448
+; ZBB-NEXT: addi a1, a1, 1028
+; ZBB-NEXT: and a0, a0, a1
+; ZBB-NEXT: orc.b a0, a0
+; ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b2:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a1, 16448
+; RV64I-NEXT: addi a1, a1, 1028
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a1, a0, 6
+; RV64I-NEXT: srli a0, a0, 2
+; RV64I-NEXT: subw a0, a1, a0
+; RV64I-NEXT: ret
entry:
%and = and i32 %x, 67372036
%shl = shl i32 %and, 6
@@ -143,13 +185,23 @@ define i32 @orc_b_i32_sub_shl8x_x_b3(i32 %x) {
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b3:
-; RV32ZBB: # %bb.0: # %entry
-; RV32ZBB-NEXT: lui a1, 32897
-; RV32ZBB-NEXT: addi a1, a1, -2040
-; RV32ZBB-NEXT: and a0, a0, a1
-; RV32ZBB-NEXT: orc.b a0, a0
-; RV32ZBB-NEXT: ret
+; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b3:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: lui a1, 32897
+; ZBB-NEXT: addi a1, a1, -2040
+; ZBB-NEXT: and a0, a0, a1
+; ZBB-NEXT: orc.b a0, a0
+; ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b3:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a1, 32897
+; RV64I-NEXT: addi a1, a1, -2040
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a1, a0, 5
+; RV64I-NEXT: srli a0, a0, 3
+; RV64I-NEXT: subw a0, a1, a0
+; RV64I-NEXT: ret
entry:
%and = and i32 %x, 134744072
%shl = shl i32 %and, 5
@@ -170,13 +222,23 @@ define i32 @orc_b_i32_sub_shl8x_x_b4(i32 %x) {
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b4:
-; RV32ZBB: # %bb.0: # %entry
-; RV32ZBB-NEXT: lui a1, 65793
-; RV32ZBB-NEXT: addi a1, a1, 16
-; RV32ZBB-NEXT: and a0, a0, a1
-; RV32ZBB-NEXT: orc.b a0, a0
-; RV32ZBB-NEXT: ret
+; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b4:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: lui a1, 65793
+; ZBB-NEXT: addi a1, a1, 16
+; ZBB-NEXT: and a0, a0, a1
+; ZBB-NEXT: orc.b a0, a0
+; ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b4:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a1, 65793
+; RV64I-NEXT: addi a1, a1, 16
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a1, a0, 4
+; RV64I-NEXT: srli a0, a0, 4
+; RV64I-NEXT: subw a0, a1, a0
+; RV64I-NEXT: ret
entry:
%and = and i32 %x, 269488144
%shl = shl i32 %and, 4
@@ -197,13 +259,23 @@ define i32 @orc_b_i32_sub_shl8x_x_b5(i32 %x) {
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b5:
-; RV32ZBB: # %bb.0: # %entry
-; RV32ZBB-NEXT: lui a1, 131586
-; RV32ZBB-NEXT: addi a1, a1, 32
-; RV32ZBB-NEXT: and a0, a0, a1
-; RV32ZBB-NEXT: orc.b a0, a0
-; RV32ZBB-NEXT: ret
+; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b5:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: lui a1, 131586
+; ZBB-NEXT: addi a1, a1, 32
+; ZBB-NEXT: and a0, a0, a1
+; ZBB-NEXT: orc.b a0, a0
+; ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b5:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a1, 131586
+; RV64I-NEXT: addi a1, a1, 32
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a1, a0, 3
+; RV64I-NEXT: srli a0, a0, 5
+; RV64I-NEXT: subw a0, a1, a0
+; RV64I-NEXT: ret
entry:
%and = and i32 %x, 538976288
%shl = shl i32 %and, 3
@@ -224,13 +296,23 @@ define i32 @orc_b_i32_sub_shl8x_x_b6(i32 %x) {
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b6:
-; RV32ZBB: # %bb.0: # %entry
-; RV32ZBB-NEXT: lui a1, 263172
-; RV32ZBB-NEXT: addi a1, a1, 64
-; RV32ZBB-NEXT: and a0, a0, a1
-; RV32ZBB-NEXT: orc.b a0, a0
-; RV32ZBB-NEXT: ret
+; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b6:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: lui a1, 263172
+; ZBB-NEXT: addi a1, a1, 64
+; ZBB-NEXT: and a0, a0, a1
+; ZBB-NEXT: orc.b a0, a0
+; ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b6:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a1, 263172
+; RV64I-NEXT: addi a1, a1, 64
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a1, a0, 2
+; RV64I-NEXT: srli a0, a0, 6
+; RV64I-NEXT: subw a0, a1, a0
+; RV64I-NEXT: ret
entry:
%and = and i32 %x, 1077952576
%shl = shl i32 %and, 2
@@ -251,13 +333,27 @@ define i32 @orc_b_i32_sub_shl8x_x_b7(i32 %x) {
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b7:
-; RV32ZBB: # %bb.0: # %entry
-; RV32ZBB-NEXT: lui a1, 526344
-; RV32ZBB-NEXT: addi a1, a1, 128
-; RV32ZBB-NEXT: and a0, a0, a1
-; RV32ZBB-NEXT: orc.b a0, a0
-; RV32ZBB-NEXT: ret
+; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b7:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: lui a1, 526344
+; ZBB-NEXT: addi a1, a1, 128
+; ZBB-NEXT: and a0, a0, a1
+; ZBB-NEXT: orc.b a0, a0
+; ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b7:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a1, 65793
+; RV64I-NEXT: slli a1, a1, 3
+; RV64I-NEXT: lui a2, 2056
+; RV64I-NEXT: addi a1, a1, 128
+; RV64I-NEXT: addi a2, a2, 128
+; RV64I-NEXT: and a1, a0, a1
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: slli a0, a0, 1
+; RV64I-NEXT: srli a1, a1, 7
+; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: ret
entry:
%and = and i32 %x, 2155905152
%shl = shl i32 %and, 1
@@ -278,15 +374,26 @@ define i32 @orc_b_i32_sub_shl8x_x_b1_shl_used(i32 %x, ptr %arr) {
; RV32I-NEXT: sw a3, 0(a1)
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_shl_used:
-; RV32ZBB: # %bb.0: # %entry
-; RV32ZBB-NEXT: lui a2, 8224
-; RV32ZBB-NEXT: addi a2, a2, 514
-; RV32ZBB-NEXT: and a2, a0, a2
-; RV32ZBB-NEXT: orc.b a0, a2
-; RV32ZBB-NEXT: srli a2, a2, 1
-; RV32ZBB-NEXT: sw a2, 0(a1)
-; RV32ZBB-NEXT: ret
+; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_shl_used:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: lui a2, 8224
+; ZBB-NEXT: addi a2, a2, 514
+; ZBB-NEXT: and a2, a0, a2
+; ZBB-NEXT: orc.b a0, a2
+; ZBB-NEXT: srli a2, a2, 1
+; ZBB-NEXT: sw a2, 0(a1)
+; ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b1_shl_used:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a2, 8224
+; RV64I-NEXT: addi a2, a2, 514
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: slli a2, a0, 7
+; RV64I-NEXT: srli a3, a0, 1
+; RV64I-NEXT: subw a0, a2, a3
+; RV64I-NEXT: sw a3, 0(a1)
+; RV64I-NEXT: ret
entry:
%and = and i32 %x, 33686018
%shl = shl i32 %and, 7
@@ -308,15 +415,29 @@ define i32 @orc_b_i32_sub_shl8x_x_b1_srl_used(i32 %x, ptr %arr) {
; RV32I-NEXT: sw a2, 0(a1)
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_srl_used:
-; RV32ZBB: # %bb.0: # %entry
-; RV32ZBB-NEXT: lui a2, 8224
-; RV32ZBB-NEXT: addi a2, a2, 514
-; RV32ZBB-NEXT: and a2, a0, a2
-; RV32ZBB-NEXT: orc.b a0, a2
-; RV32ZBB-NEXT: slli a2, a2, 7
-; RV32ZBB-NEXT: sw a2, 0(a1)
-; RV32ZBB-NEXT: ret
+; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_srl_used:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: lui a2, 8224
+; ZBB-NEXT: addi a2, a2, 514
+; ZBB-NEXT: and a2, a0, a2
+; ZBB-NEXT: orc.b a0, a2
+; ZBB-NEXT: slli a2, a2, 7
+; ZBB-NEXT: sw a2, 0(a1)
+; ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b1_srl_used:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a2, 8224
+; RV64I-NEXT: addi a2, a2, 514
+; RV64I-NEXT: lui a3, 4112
+; RV64I-NEXT: and a2, a0, a2
+; RV64I-NEXT: slli a0, a0, 7
+; RV64I-NEXT: addi a3, a3, 256
+; RV64I-NEXT: and a3, a0, a3
+; RV64I-NEXT: srli a2, a2, 1
+; RV64I-NEXT: sub a0, a3, a2
+; RV64I-NEXT: sw a3, 0(a1)
+; RV64I-NEXT: ret
entry:
%and = and i32 %x, 33686018
%shl = shl i32 %and, 7
@@ -338,13 +459,23 @@ define i32 @orc_b_i32_sub_shl8x_x_b1_not_used(i32 %x, ptr %arr) {
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_not_used:
-; RV32ZBB: # %bb.0: # %entry
-; RV32ZBB-NEXT: lui a1, 8224
-; RV32ZBB-NEXT: addi a1, a1, 514
-; RV32ZBB-NEXT: and a0, a0, a1
-; RV32ZBB-NEXT: orc.b a0, a0
-; RV32ZBB-NEXT: ret
+; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_not_used:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: lui a1, 8224
+; ZBB-NEXT: addi a1, a1, 514
+; ZBB-NEXT: and a0, a0, a1
+; ZBB-NEXT: orc.b a0, a0
+; ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b1_not_used:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a1, 8224
+; RV64I-NEXT: addi a1, a1, 514
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a1, a0, 7
+; RV64I-NEXT: srli a0, a0, 1
+; RV64I-NEXT: subw a0, a1, a0
+; RV64I-NEXT: ret
entry:
%and = and i32 %x, 33686018
%shl = shl i32 %and, 7
@@ -354,15 +485,49 @@ entry:
}
define i32 @orc_b_i32_sub_shl8x_x_shl_used(i32 %x, ptr %arr){
-; CHECK-LABEL: orc_b_i32_sub_shl8x_x_shl_used:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lui a2, 4112
-; CHECK-NEXT: addi a2, a2, 257
-; CHECK-NEXT: and a0, a0, a2
-; CHECK-NEXT: slli a2, a0, 8
-; CHECK-NEXT: sub a0, a2, a0
-; CHECK-NEXT: sw a2, 0(a1)
-; CHECK-NEXT: ret
+; RV32I-LABEL: orc_b_i32_sub_shl8x_x_shl_used:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a2, 4112
+; RV32I-NEXT: addi a2, a2, 257
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: slli a2, a0, 8
+; RV32I-NEXT: sub a0, a2, a0
+; RV32I-NEXT: sw a2, 0(a1)
+; RV32I-NEXT: ret
+;
+; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_shl_used:
+; RV32ZBB: # %bb.0: # %entry
+; RV32ZBB-NEXT: lui a2, 4112
+; RV32ZBB-NEXT: addi a2, a2, 257
+; RV32ZBB-NEXT: and a0, a0, a2
+; RV32ZBB-NEXT: slli a2, a0, 8
+; RV32ZBB-NEXT: sub a0, a2, a0
+; RV32ZBB-NEXT: sw a2, 0(a1)
+; RV32ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_shl8x_x_shl_used:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a2, 4112
+; RV64I-NEXT: addi a3, a2, 257
+; RV64I-NEXT: slli a4, a0, 8
+; RV64I-NEXT: addi a2, a2, 256
+; RV64I-NEXT: and a0, a0, a3
+; RV64I-NEXT: and a2, a4, a2
+; RV64I-NEXT: sub a0, a2, a0
+; RV64I-NEXT: sw a2, 0(a1)
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: orc_b_i32_sub_shl8x_x_shl_used:
+; RV64ZBB: # %bb.0: # %entry
+; RV64ZBB-NEXT: lui a2, 4112
+; RV64ZBB-NEXT: addi a3, a2, 257
+; RV64ZBB-NEXT: slli a4, a0, 8
+; RV64ZBB-NEXT: addi a2, a2, 256
+; RV64ZBB-NEXT: and a0, a0, a3
+; RV64ZBB-NEXT: and a2, a4, a2
+; RV64ZBB-NEXT: sub a0, a2, a0
+; RV64ZBB-NEXT: sw a2, 0(a1)
+; RV64ZBB-NEXT: ret
entry:
%and = and i32 %x, 16843009
%shl = shl i32 %and, 8
@@ -372,17 +537,57 @@ entry:
}
define i32 @orc_b_i32_sub_shl8x_x_b1_both_used(i32 %x, ptr %arr) {
-; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b1_both_used:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lui a2, 8224
-; CHECK-NEXT: addi a2, a2, 514
-; CHECK-NEXT: and a0, a0, a2
-; CHECK-NEXT: slli a2, a0, 7
-; CHECK-NEXT: srli a3, a0, 1
-; CHECK-NEXT: sub a0, a2, a3
-; CHECK-NEXT: sw a2, 0(a1)
-; CHECK-NEXT: sw a3, 4(a1)
-; CHECK-NEXT: ret
+; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_both_used:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a2, 8224
+; RV32I-NEXT: addi a2, a2, 514
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: slli a2, a0, 7
+; RV32I-NEXT: srli a3, a0, 1
+; RV32I-NEXT: sub a0, a2, a3
+; RV32I-NEXT: sw a2, 0(a1)
+; RV32I-NEXT: sw a3, 4(a1)
+; RV32I-NEXT: ret
+;
+; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_both_used:
+; RV32ZBB: # %bb.0: # %entry
+; RV32ZBB-NEXT: lui a2, 8224
+; RV32ZBB-NEXT: addi a2, a2, 514
+; RV32ZBB-NEXT: and a0, a0, a2
+; RV32ZBB-NEXT: slli a2, a0, 7
+; RV32ZBB-NEXT: srli a3, a0, 1
+; RV32ZBB-NEXT: sub a0, a2, a3
+; RV32ZBB-NEXT: sw a2, 0(a1)
+; RV32ZBB-NEXT: sw a3, 4(a1)
+; RV32ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b1_both_used:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a2, 4112
+; RV64I-NEXT: slli a3, a0, 7
+; RV64I-NEXT: addi a4, a2, 256
+; RV64I-NEXT: srli a0, a0, 1
+; RV64I-NEXT: addi a2, a2, 257
+; RV64I-NEXT: and a3, a3, a4
+; RV64I-NEXT: and a2, a0, a2
+; RV64I-NEXT: sub a0, a3, a2
+; RV64I-NEXT: sw a3, 0(a1)
+; RV64I-NEXT: sw a2, 4(a1)
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_both_used:
+; RV64ZBB: # %bb.0: # %entry
+; RV64ZBB-NEXT: lui a2, 4112
+; RV64ZBB-NEXT: slli a3, a0, 7
+; RV64ZBB-NEXT: addi a4, a2, 256
+; RV64ZBB-NEXT: srli a0, a0, 1
+; RV64ZBB-NEXT: addi a2, a2, 257
+; RV64ZBB-NEXT: and a3, a3, a4
+; RV64ZBB-NEXT: and a2, a0, a2
+; RV64ZBB-NEXT: sub a0, a3, a2
+; RV64ZBB-NEXT: sw a3, 0(a1)
+; RV64ZBB-NEXT: sw a2, 4(a1)
+; RV64ZBB-NEXT: ret
entry:
%and = and i32 %x, 33686018
%shl = shl i32 %and, 7
@@ -396,17 +601,136 @@ entry:
define i32 @orc_b_i32_sub_x_shr8x(i32 %x) {
-; CHECK-LABEL: orc_b_i32_sub_x_shr8x:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lui a1, 4112
-; CHECK-NEXT: addi a1, a1, 257
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: srli a1, a0, 8
-; CHECK-NEXT: sub a0, a0, a1
-; CHECK-NEXT: ret
+; RV32I-LABEL: orc_b_i32_sub_x_shr8x:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 4112
+; RV32I-NEXT: addi a1, a1, 257
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: srli a1, a0, 8
+; RV32I-NEXT: sub a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32ZBB-LABEL: orc_b_i32_sub_x_shr8x:
+; RV32ZBB: # %bb.0: # %entry
+; RV32ZBB-NEXT: lui a1, 4112
+; RV32ZBB-NEXT: addi a1, a1, 257
+; RV32ZBB-NEXT: and a0, a0, a1
+; RV32ZBB-NEXT: srli a1, a0, 8
+; RV32ZBB-NEXT: sub a0, a0, a1
+; RV32ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i32_sub_x_shr8x:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a1, 4112
+; RV64I-NEXT: addi a2, a1, 256
+; RV64I-NEXT: addi a1, a1, 257
+; RV64I-NEXT: and a2, a0, a2
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: srli a2, a2, 8
+; RV64I-NEXT: sub a0, a0, a2
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: orc_b_i32_sub_x_shr8x:
+; RV64ZBB: # %bb.0: # %entry
+; RV64ZBB-NEXT: lui a1, 4112
+; RV64ZBB-NEXT: addi a2, a1, 256
+; RV64ZBB-NEXT: addi a1, a1, 257
+; RV64ZBB-NEXT: and a2, a0, a2
+; RV64ZBB-NEXT: and a0, a0, a1
+; RV64ZBB-NEXT: srli a2, a2, 8
+; RV64ZBB-NEXT: sub a0, a0, a2
+; RV64ZBB-NEXT: ret
entry:
%and = and i32 %x, 16843009
%shr = lshr i32 %and, 8
%sub = sub i32 %and, %shr
ret i32 %sub
}
+
+define i16 @orc_b_i16_sub_shl8x_x_b1(i16 %x) {
+; I-LABEL: orc_b_i16_sub_shl8x_x_b1:
+; I: # %bb.0: # %entry
+; I-NEXT: andi a0, a0, 514
+; I-NEXT: slli a1, a0, 7
+; I-NEXT: srli a0, a0, 1
+; I-NEXT: sub a0, a1, a0
+; I-NEXT: ret
+;
+; ZBB-LABEL: orc_b_i16_sub_shl8x_x_b1:
+; ZBB: # %bb.0: # %entry
+; ZBB-NEXT: andi a0, a0, 514
+; ZBB-NEXT: orc.b a0, a0
+; ZBB-NEXT: ret
+entry:
+ %and = and i16 %x, u0x0202
+ %shl = shl i16 %and, 7
+ %shr = lshr i16 %and, 1
+ %sub = sub i16 %shl, %shr
+ ret i16 %sub
+}
+
+define i64 @orc_b_i64_sub_shl8x_x_b2(i64 %x) {
+; RV32I-LABEL: orc_b_i64_sub_shl8x_x_b2:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a2, 16448
+; RV32I-NEXT: addi a2, a2, 1028
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: srli a2, a0, 26
+; RV32I-NEXT: slli a3, a1, 6
+; RV32I-NEXT: slli a4, a0, 6
+; RV32I-NEXT: or a2, a3, a2
+; RV32I-NEXT: srli a1, a1, 2
+; RV32I-NEXT: srli a0, a0, 2
+; RV32I-NEXT: sltu a3, a4, a0
+; RV32I-NEXT: sub a1, a2, a1
+; RV32I-NEXT: sub a1, a1, a3
+; RV32I-NEXT: sub a0, a4, a0
+; RV32I-NEXT: ret
+;
+; RV32ZBB-LABEL: orc_b_i64_sub_shl8x_x_b2:
+; RV32ZBB: # %bb.0: # %entry
+; RV32ZBB-NEXT: lui a2, 16448
+; RV32ZBB-NEXT: addi a2, a2, 1028
+; RV32ZBB-NEXT: and a1, a1, a2
+; RV32ZBB-NEXT: and a0, a0, a2
+; RV32ZBB-NEXT: srli a2, a0, 26
+; RV32ZBB-NEXT: slli a3, a1, 6
+; RV32ZBB-NEXT: slli a4, a0, 6
+; RV32ZBB-NEXT: or a2, a3, a2
+; RV32ZBB-NEXT: srli a1, a1, 2
+; RV32ZBB-NEXT: srli a0, a0, 2
+; RV32ZBB-NEXT: sltu a3, a4, a0
+; RV32ZBB-NEXT: sub a1, a2, a1
+; RV32ZBB-NEXT: sub a1, a1, a3
+; RV32ZBB-NEXT: sub a0, a4, a0
+; RV32ZBB-NEXT: ret
+;
+; RV64I-LABEL: orc_b_i64_sub_shl8x_x_b2:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lui a1, 16448
+; RV64I-NEXT: addi a1, a1, 1028
+; RV64I-NEXT: slli a2, a1, 32
+; RV64I-NEXT: add a1, a1, a2
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a1, a0, 6
+; RV64I-NEXT: srli a0, a0, 2
+; RV64I-NEXT: sub a0, a1, a0
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: orc_b_i64_sub_shl8x_x_b2:
+; RV64ZBB: # %bb.0: # %entry
+; RV64ZBB-NEXT: lui a1, 16448
+; RV64ZBB-NEXT: addi a1, a1, 1028
+; RV64ZBB-NEXT: slli a2, a1, 32
+; RV64ZBB-NEXT: add a1, a1, a2
+; RV64ZBB-NEXT: and a0, a0, a1
+; RV64ZBB-NEXT: orc.b a0, a0
+; RV64ZBB-NEXT: ret
+entry:
+ %and = and i64 %x, u0x0404040404040404
+ %shl = shl i64 %and, 6
+ %shr = lshr exact i64 %and, 2
+ %sub = sub nsw i64 %shl, %shr
+ ret i64 %sub
+}
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