[llvm] 0c5f85f - [RISCV] Use run-pass instead of start-before in macrofusion tests. NFC (#222390)

via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 9 10:46:39 PDT 2026 

Author: Craig Topper
Date: 2026-09-09T17:46:34Z
New Revision: 0c5f85f9a24a0cdeccb05a362cd40b03da6f1783

URL: https://github.com/llvm/llvm-project/commit/0c5f85f9a24a0cdeccb05a362cd40b03da6f1783
DIFF: https://github.com/llvm/llvm-project/commit/0c5f85f9a24a0cdeccb05a362cd40b03da6f1783.diff

LOG: [RISCV] Use run-pass instead of start-before in macrofusion tests. NFC (#222390)

We're only checking the debug output from the scheduler pass, we don't
need to more of the pipeline.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/macro-fusion-add-mem.mir
    llvm/test/CodeGen/RISCV/macro-fusion-logic-imm-reg.mir
    llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-imm.mir
    llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-reg.mir
    llvm/test/CodeGen/RISCV/macro-fusion-mul-add.mir
    llvm/test/CodeGen/RISCV/macro-fusion-shift-bit-extract.mir
    llvm/test/CodeGen/RISCV/macro-fusions-xqci.mir
    llvm/test/CodeGen/RISCV/macro-fusions.mir
    llvm/test/CodeGen/RISCV/xqci-macro-fusions.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/macro-fusion-add-mem.mir b/llvm/test/CodeGen/RISCV/macro-fusion-add-mem.mir
index 66029bda38e80..d98e2af1d7872 100644
--- a/llvm/test/CodeGen/RISCV/macro-fusion-add-mem.mir
+++ b/llvm/test/CodeGen/RISCV/macro-fusion-add-mem.mir
@@ -1,6 +1,6 @@
 # REQUIRES: asserts
 # RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \
-# RUN:   -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \
+# RUN:   -debug-only=machine-scheduler -run-pass=machine-scheduler 2>&1 \
 # RUN:   -mattr=+fusion-add-mem | FileCheck %s
 
 # Test add-mem fusion: ADD + load/store with offset 0

diff  --git a/llvm/test/CodeGen/RISCV/macro-fusion-logic-imm-reg.mir b/llvm/test/CodeGen/RISCV/macro-fusion-logic-imm-reg.mir
index 55261abaad531..b531e85f156d0 100644
--- a/llvm/test/CodeGen/RISCV/macro-fusion-logic-imm-reg.mir
+++ b/llvm/test/CodeGen/RISCV/macro-fusion-logic-imm-reg.mir
@@ -1,6 +1,6 @@
 # REQUIRES: asserts
 # RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \
-# RUN:   -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \
+# RUN:   -debug-only=machine-scheduler -run-pass=machine-scheduler 2>&1 \
 # RUN:   -mattr=+fusion-logic-imm-reg | FileCheck %s
 
 # Test logic immediate-register fusion: ANDI/ORI/XORI + AND/OR/XOR

diff  --git a/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-imm.mir b/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-imm.mir
index eba113b97c99c..4829049fd0f51 100644
--- a/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-imm.mir
+++ b/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-imm.mir
@@ -1,6 +1,6 @@
 # REQUIRES: asserts
 # RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \
-# RUN:   -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \
+# RUN:   -debug-only=machine-scheduler -run-pass=machine-scheduler 2>&1 \
 # RUN:   -mattr=+fusion-logic-reg-imm | FileCheck %s
 
 # Test logic register-immediate fusion: AND/OR/XOR + ANDI/ORI/XORI

diff  --git a/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-reg.mir b/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-reg.mir
index 582d7c77280e5..6ab4a5751cfee 100644
--- a/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-reg.mir
+++ b/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-reg.mir
@@ -1,6 +1,6 @@
 # REQUIRES: asserts
 # RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \
-# RUN:   -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \
+# RUN:   -debug-only=machine-scheduler -run-pass=machine-scheduler 2>&1 \
 # RUN:   -mattr=+fusion-logic-reg-reg | FileCheck %s
 
 # Test logic register-register fusion: AND/OR/XOR + AND/OR/XOR

diff  --git a/llvm/test/CodeGen/RISCV/macro-fusion-mul-add.mir b/llvm/test/CodeGen/RISCV/macro-fusion-mul-add.mir
index 08c3f24575642..e3f36eab57c92 100644
--- a/llvm/test/CodeGen/RISCV/macro-fusion-mul-add.mir
+++ b/llvm/test/CodeGen/RISCV/macro-fusion-mul-add.mir
@@ -1,6 +1,6 @@
 # REQUIRES: asserts
 # RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \
-# RUN:   -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \
+# RUN:   -debug-only=machine-scheduler -run-pass=machine-scheduler 2>&1 \
 # RUN:   -mattr=+m,+fusion-mul-add | FileCheck %s
 
 # Test mul-add fusion: MUL + ADD and MULW + ADDW

diff  --git a/llvm/test/CodeGen/RISCV/macro-fusion-shift-bit-extract.mir b/llvm/test/CodeGen/RISCV/macro-fusion-shift-bit-extract.mir
index 4ce6c1431081c..8bb2cc4270cc6 100644
--- a/llvm/test/CodeGen/RISCV/macro-fusion-shift-bit-extract.mir
+++ b/llvm/test/CodeGen/RISCV/macro-fusion-shift-bit-extract.mir
@@ -1,6 +1,6 @@
 # REQUIRES: asserts
 # RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \
-# RUN:   -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \
+# RUN:   -debug-only=machine-scheduler -run-pass=machine-scheduler 2>&1 \
 # RUN:   -mattr=+fusion-shift-bit-extract | FileCheck %s
 
 # Test shift-bit-extract fusion: SLLI + SRLI/SRAI

diff  --git a/llvm/test/CodeGen/RISCV/macro-fusions-xqci.mir b/llvm/test/CodeGen/RISCV/macro-fusions-xqci.mir
index 96d6cd18d550c..2496b09d0caf7 100644
--- a/llvm/test/CodeGen/RISCV/macro-fusions-xqci.mir
+++ b/llvm/test/CodeGen/RISCV/macro-fusions-xqci.mir
@@ -1,6 +1,6 @@
 # REQUIRES: asserts
 # RUN: llc -mtriple=riscv32-linux-gnu -x=mir < %s \
-# RUN:   -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \
+# RUN:   -debug-only=machine-scheduler -run-pass=machine-scheduler 2>&1 \
 # RUN:   -mattr=+xqcilia,+xqcili,+xqcilo,+zmmul,+fusion-xqci-movimm-alu \
 # RUN:   -mattr=+fusion-xqci-movimm-mul,+fusion-xqci-movimm-ldst \
 # RUN:   -mattr=+fusion-xqci-movimm-jump \

diff  --git a/llvm/test/CodeGen/RISCV/macro-fusions.mir b/llvm/test/CodeGen/RISCV/macro-fusions.mir
index 77fc03c4237fe..ad18e71102860 100644
--- a/llvm/test/CodeGen/RISCV/macro-fusions.mir
+++ b/llvm/test/CodeGen/RISCV/macro-fusions.mir
@@ -1,12 +1,12 @@
 # REQUIRES: asserts
 # RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \
-# RUN:   -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \
+# RUN:   -debug-only=machine-scheduler -run-pass=machine-scheduler 2>&1 \
 # RUN:   -mattr=+fusion-lui-addi,+fusion-auipc-addi,+fusion-zexth,+fusion-zextw,+fusion-shifted-zextw,+fusion-ld-add \
 # RUN:   -mattr=+fusion-add-load,+fusion-auipc-load,+fusion-lui-load,+fusion-addi-load \
 # RUN:   -mattr=+zba,+fusion-shxadd-load \
 # RUN:   | FileCheck %s
 # RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \
-# RUN:   -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \
+# RUN:   -debug-only=machine-scheduler -run-pass=machine-scheduler 2>&1 \
 # RUN:   -mattr=+zba,+fusion-bfext | FileCheck --check-prefixes=CHECK-BFEXT %s
 
 # CHECK: lui_addi:%bb.0

diff  --git a/llvm/test/CodeGen/RISCV/xqci-macro-fusions.mir b/llvm/test/CodeGen/RISCV/xqci-macro-fusions.mir
index ccd70ad74fb47..65b9c4c24acbd 100644
--- a/llvm/test/CodeGen/RISCV/xqci-macro-fusions.mir
+++ b/llvm/test/CodeGen/RISCV/xqci-macro-fusions.mir
@@ -1,6 +1,6 @@
 # REQUIRES: asserts
 # RUN: llc -mtriple=riscv32-linux-gnu -x=mir < %s \
-# RUN:   -debug-only=machine-scheduler -start-before=machine-scheduler -stop-after=machine-scheduler 2>&1 \
+# RUN:   -debug-only=machine-scheduler -run-pass=machine-scheduler 2>&1 \
 # RUN:   -mattr=+xqcili,+fusion-qc-e-li-load-store \
 # RUN:   | FileCheck %s

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