[llvm] [X86][CodeGen] Support partial-reduce dot products (PR #205373)

[Simon Pilgrim via llvm-commits]

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@@ -0,0 +1,141 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512vl,+avx512bw,+avx512bf16,+avxvnni,+avxvnniint8,+avxvnniint16 | FileCheck %s --check-prefixes=AVX512-VEXVNNI
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx10.2 | FileCheck %s --check-prefixes=AVX10
+
+; With 512-bit vectors disabled by the preferred vector width, type
+; legalization splits the partial reductions into 256-bit halves.
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RKSimon wrote:

Why the separate file instead another RUN line in vector-partial-reduce-dot-product.ll? You can use -mattr=prefer-256-bit

https://github.com/llvm/llvm-project/pull/205373