[llvm] [AMDGPU] Reduce unnecessary src2 bridge copies in RewriteMFMAFormStage (PR #215806)

[Romanov Vlad via llvm-commits]

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@@ -2317,19 +2321,21 @@ void GCNSchedStage::modifyRegionSchedule(unsigned RegionIdx,
 }
 
 /// Returns true if reaching def \p RD will be in AGPR form after the rewrite
-/// and so needs no bridge copy: a candidate MFMA in \p RewriteSet, an
-/// AV_MOV_*_IMM_PSEUDO, or a copy from a candidate src2 reg in \p CandSrc2Regs.
-/// A non-candidate MFMA stays in VGPR form and still needs a bridge.
+/// and so needs no bridge copy.
 static bool isReachingDefAGPRForm(
     MachineInstr *RD, const SmallPtrSetImpl<MachineInstr *> &RewriteSet,
     const DenseSet<Register> &CandSrc2Regs, const SIInstrInfo &TII) {
   if (TII.isMAI(*RD))
     return RewriteSet.contains(RD);
-  if (RD->getOpcode() == AMDGPU::AV_MOV_B32_IMM_PSEUDO ||
-      RD->getOpcode() == AMDGPU::AV_MOV_B64_IMM_PSEUDO)
-    return true;
   if (RD->isCopy() && CandSrc2Regs.contains(RD->getOperand(1).getReg()))
     return true;
+  // Instructions whose def operand accepts AGPR (DS_READ, AV_MOV, etc.)
+  // will produce AGPR after reclassification - no bridge copy needed.
+  const SIRegisterInfo &SRI =
+      static_cast<const SIRegisterInfo &>(TII.getRegisterInfo());
+  const TargetRegisterClass *DefRC = TII.getRegClass(RD->getDesc(), 0);
+  if (DefRC && (SRI.isAGPRClass(DefRC) || SRI.isVectorSuperClass(DefRC)))
+    return true;
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romanovvlad wrote:

Right. The issue should be fixed in https://github.com/llvm/llvm-project/pull/217396

https://github.com/llvm/llvm-project/pull/215806