[llvm] [AMDGPU] Fix pow with a negative base (PR #222248)
Arseniy Obolenskiy via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 9 05:46:04 PDT 2026
https://github.com/aobolensk updated https://github.com/llvm/llvm-project/pull/222248
>From e034fc899d8cf454d77fff170a04ef81eb1a5906 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Wed, 9 Sep 2026 08:14:37 +0200
Subject: [PATCH 1/3] [AMDGPU] Fix pow with a negative base
v_log_f32 of a negative value is NaN, so the old expansion returned NaN for every negative base
Take the log of `|x|` and fix up the sign
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 69 +-
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 +
.../AMDGPU/AMDGPUInstructionSelector.cpp | 2 +-
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 86 +-
llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 2 +
llvm/lib/Target/AMDGPU/SIInstructions.td | 5 -
.../AMDGPU/GlobalISel/fma-mix-true16.ll | 74 +
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll | 5396 +++++++++++++----
.../AMDGPU/GlobalISel/legalize-fpow.mir | 1054 +++-
.../AMDGPU/GlobalISel/legalize-fpowi.mir | 148 +-
.../CodeGen/AMDGPU/GlobalISel/llvm.powi.ll | 316 +-
llvm/test/CodeGen/AMDGPU/fpow.ll | 4673 ++++++++++++--
llvm/test/CodeGen/AMDGPU/llvm.powi.ll | 281 +-
13 files changed, 10092 insertions(+), 2015 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 43a6cf7bd7229..97a13012305e4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -412,9 +412,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
// Library functions. These default to Expand, but we have instructions
// for them.
- setOperationAction({ISD::FCEIL, ISD::FPOW, ISD::FABS, ISD::FFLOOR,
- ISD::FROUNDEVEN, ISD::FTRUNC},
- {MVT::f16, MVT::f32}, Legal);
+ setOperationAction(
+ {ISD::FCEIL, ISD::FABS, ISD::FFLOOR, ISD::FROUNDEVEN, ISD::FTRUNC},
+ {MVT::f16, MVT::f32}, Legal);
setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, MVT::f32, Legal);
setOperationAction(ISD::FLOG2, MVT::f32, Custom);
@@ -423,8 +423,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
{MVT::f16, MVT::f32, MVT::f64}, Expand);
setOperationAction(
- {ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32,
- Custom);
+ {ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10, ISD::FPOW},
+ MVT::f32, Custom);
setOperationAction({ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f64, Custom);
setOperationAction(ISD::FNEARBYINT, {MVT::f16, MVT::f32, MVT::f64}, Custom);
@@ -1461,6 +1461,8 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
return lowerFEXP(Op, DAG);
case ISD::FEXP2:
return lowerFEXP2(Op, DAG);
+ case ISD::FPOW:
+ return lowerFPOW(Op, DAG);
case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);
@@ -3310,6 +3312,63 @@ SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {
return R;
}
+// No pow instruction or libcall to fall back on. fmul_legacy returns 0 for a
+// zero operand even against an infinity or a NaN, so pow(x, 0) and pow(1, y)
+// fall out as exp2(0) = 1.
+SDValue AMDGPUTargetLowering::lowerFPOW(SDValue Op, SelectionDAG &DAG) const {
+ EVT VT = Op.getValueType();
+ assert(VT == MVT::f32);
+
+ SDLoc SL(Op);
+ SDValue X = Op.getOperand(0);
+ SDValue Y = Op.getOperand(1);
+ SDNodeFlags Flags = Op->getFlags();
+
+ // Fast expansion: ignores denormals, NaN for a negative base.
+ if (allowApproxFunc(DAG, Flags)) {
+ SDValue Log = DAG.getNode(AMDGPUISD::LOG, SL, VT, X, Flags);
+ SDValue Mul = DAG.getNode(AMDGPUISD::FMUL_LEGACY, SL, VT, Y, Log, Flags);
+ return DAG.getNode(AMDGPUISD::EXP, SL, VT, Mul, Flags);
+ }
+
+ SDValue Abs = DAG.getNode(ISD::FABS, SL, VT, X, Flags);
+ SDValue Log = DAG.getNode(ISD::FLOG2, SL, VT, Abs, Flags);
+ SDValue Mul = DAG.getNode(AMDGPUISD::FMUL_LEGACY, SL, VT, Y, Log, Flags);
+ SDValue R = DAG.getNode(ISD::FEXP2, SL, VT, Mul, Flags);
+
+ EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+ SDValue One = DAG.getConstantFP(1.0, SL, VT);
+
+ // Infinities count as integers, and every f32 >= 2^24 in magnitude is even.
+ SDValue YTrunc = DAG.getNode(ISD::FTRUNC, SL, VT, Y);
+ SDValue YIsInt = DAG.getSetCC(SL, SetCCVT, YTrunc, Y, ISD::SETOEQ);
+ SDValue YHalf =
+ DAG.getNode(ISD::FMUL, SL, VT, Y, DAG.getConstantFP(0.5, SL, VT));
+ SDValue YHalfTrunc = DAG.getNode(ISD::FTRUNC, SL, VT, YHalf);
+ SDValue YIsOdd =
+ DAG.getNode(ISD::AND, SL, SetCCVT, YIsInt,
+ DAG.getSetCC(SL, SetCCVT, YHalfTrunc, YHalf, ISD::SETONE));
+
+ // pow(-x, odd y) = -pow(x, y).
+ R = DAG.getNode(ISD::FCOPYSIGN, SL, VT, R,
+ DAG.getNode(ISD::SELECT, SL, VT, YIsOdd, X, One));
+
+ if (Flags.hasNoNaNs())
+ return R;
+
+ // A negative finite base to a non-integral power is NaN. -inf is excluded:
+ // the core already gives pow(+inf, y).
+ SDValue XNegFinite = DAG.getNode(
+ ISD::IS_FPCLASS, SL, SetCCVT, X,
+ DAG.getTargetConstant(fcNegNormal | fcNegSubnormal, SL, MVT::i32));
+ // Not a SETONE compare: pow(-1, NaN) needs the NaN-true behavior of !SETOEQ.
+ SDValue NegNonInt = DAG.getNode(ISD::AND, SL, SetCCVT, XNegFinite,
+ DAG.getNOT(SL, YIsInt, SetCCVT));
+ SDValue NaN =
+ DAG.getConstantFP(APFloat::getQNaN(VT.getFltSemantics()), SL, VT);
+ return DAG.getNode(ISD::SELECT, SL, VT, NegNonInt, NaN, R);
+}
+
static bool isCtlzOpc(unsigned Opc) {
return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_POISON;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 33ca92d5b7a51..9316f83fac06e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -87,6 +87,7 @@ class AMDGPUTargetLowering : public TargetLowering {
SDNodeFlags Flags) const;
SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFEXPF64(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerFPOW(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerCTLZResults(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 7475d7dbec091..99aa8ea34d222 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -7129,7 +7129,7 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
unsigned Mods;
std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
- if (mi_match(Src, *MRI, m_GFPExt(m_Reg(Src)))) {
+ if (!STI.useRealTrue16Insts() && mi_match(Src, *MRI, m_GFPExt(m_Reg(Src)))) {
assert(MRI->getType(Src) == LLT::scalar(16));
// Only change Src if src modifier could be gained. In such cases new Src
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 49d055461ccb1..36fbec46c2014 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -729,7 +729,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
const std::initializer_list<LLT> FPTypesPK16_64 = {F32, F64, F16, V2F16,
V2F64};
- const LLT MinExtendedFPTy = ST.has16BitInsts() ? F16 : F32;
const LLT I1 = LLT::integer(1);
const LLT I16 = LLT::integer(16);
const LLT I32 = LLT::integer(32);
@@ -1355,17 +1354,12 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
FCmpBuilder.widenScalarToNextPow2(1).minScalar(1, F32).scalarize(0);
- // FIXME: fpow has a selection pattern that should move to custom lowering.
- auto &ExpOps = getActionDefinitionsBuilder(G_FPOW);
- if (ST.has16BitInsts())
- ExpOps.customFor({{F32}, {F16}});
- else
- ExpOps.customFor({F32});
- ExpOps.clampScalar(0, MinExtendedFPTy, F32).scalarize(0);
+ getActionDefinitionsBuilder(G_FPOW)
+ .customFor({F32})
+ .clampScalar(0, F32, F32)
+ .scalarize(0);
- getActionDefinitionsBuilder(G_FPOWI)
- .clampScalar(0, MinExtendedFPTy, F32)
- .lower();
+ getActionDefinitionsBuilder(G_FPOWI).clampScalar(0, F32, F32).lower();
getActionDefinitionsBuilder(G_FLOG2)
.legalFor(ST.has16BitInsts(), {F16})
@@ -4281,37 +4275,61 @@ bool AMDGPULegalizerInfo::legalizeFExp(MachineInstr &MI,
return true;
}
+// Keep in sync with AMDGPUTargetLowering::lowerFPOW, which documents this.
bool AMDGPULegalizerInfo::legalizeFPow(MachineInstr &MI,
MachineIRBuilder &B) const {
Register Dst = MI.getOperand(0).getReg();
- Register Src0 = MI.getOperand(1).getReg();
- Register Src1 = MI.getOperand(2).getReg();
+ Register X = MI.getOperand(1).getReg();
+ Register Y = MI.getOperand(2).getReg();
unsigned Flags = MI.getFlags();
- LLT Ty = B.getMRI()->getType(Dst);
+ assert(B.getMRI()->getType(Dst) == F32);
- if (Ty == F32) {
- auto Log = B.buildFLog2(F32, Src0, Flags);
- auto Mul = B.buildIntrinsic(Intrinsic::amdgcn_fmul_legacy, {F32})
- .addUse(Log.getReg(0))
- .addUse(Src1)
+ // Fast expansion: ignores denormals, NaN for a negative base.
+ if (allowApproxFunc(B.getMF(), Flags)) {
+ auto Log = B.buildIntrinsic(Intrinsic::amdgcn_log, {F32})
+ .addUse(X)
.setMIFlags(Flags);
- B.buildFExp2(Dst, Mul, Flags);
- } else if (Ty == F16) {
- // There's no f16 fmul_legacy, so we need to convert for it.
- auto Log = B.buildFLog2(F16, Src0, Flags);
- auto Ext0 = B.buildFPExt(F32, Log, Flags);
- auto Ext1 = B.buildFPExt(F32, Src1, Flags);
auto Mul = B.buildIntrinsic(Intrinsic::amdgcn_fmul_legacy, {F32})
- .addUse(Ext0.getReg(0))
- .addUse(Ext1.getReg(0))
+ .addUse(Y)
+ .addUse(Log.getReg(0))
.setMIFlags(Flags);
- // The f32 product is finite whenever the original fpow was, but it can
- // still be outside the f16 range. Drop ninf from the truncation and from
- // the exp2, since neither can assume a finite value here.
- unsigned FlagsNoNInf = Flags & ~MachineInstr::FmNoInfs;
- B.buildFExp2(Dst, B.buildFPTrunc(F16, Mul, FlagsNoNInf), FlagsNoNInf);
- } else
- return false;
+ buildExp(B, Dst, Mul.getReg(0), Flags);
+ MI.eraseFromParent();
+ return true;
+ }
+
+ auto Abs = B.buildFAbs(F32, X, Flags);
+ auto Log = B.buildFLog2(F32, Abs, Flags);
+ auto Mul = B.buildIntrinsic(Intrinsic::amdgcn_fmul_legacy, {F32})
+ .addUse(Y)
+ .addUse(Log.getReg(0))
+ .setMIFlags(Flags);
+ Register R = B.buildFExp2(F32, Mul, Flags).getReg(0);
+
+ auto One = B.buildFConstant(F32, 1.0);
+
+ auto YTrunc = B.buildIntrinsicTrunc(F32, Y);
+ auto YIsInt = B.buildFCmp(CmpInst::FCMP_OEQ, S1, YTrunc, Y);
+ auto YHalf = B.buildFMul(F32, Y, B.buildFConstant(F32, 0.5));
+ auto YHalfTrunc = B.buildIntrinsicTrunc(F32, YHalf);
+ auto YIsOdd = B.buildAnd(
+ S1, YIsInt, B.buildFCmp(CmpInst::FCMP_ONE, S1, YHalfTrunc, YHalf));
+
+ // pow(-x, odd y) = -pow(x, y).
+ auto Sign = B.buildSelect(F32, YIsOdd, X, One);
+ if (Flags & MachineInstr::FmNoNans) {
+ B.buildFCopysign(Dst, R, Sign);
+ MI.eraseFromParent();
+ return true;
+ }
+ R = B.buildFCopysign(F32, R, Sign).getReg(0);
+
+ // A negative finite base to a non-integral power is NaN. Not an ONE compare:
+ // pow(-1, NaN) needs the NaN-true behavior of !OEQ.
+ auto XNegFinite = B.buildIsFPClass(S1, X, fcNegNormal | fcNegSubnormal);
+ auto NegNonInt = B.buildAnd(S1, XNegFinite, B.buildNot(S1, YIsInt));
+ auto NaN = B.buildFConstant(F32, APFloat::getQNaN(APFloat::IEEEsingle()));
+ B.buildSelect(Dst, NegNonInt, NaN, R);
MI.eraseFromParent();
return true;
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index ad088c81335ef..7595f285b5eea 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -110,6 +110,8 @@ R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FROUNDEVEN, ISD::FFLOOR},
MVT::f64, Custom);
+ setOperationAction(ISD::FPOW, MVT::f32, Legal);
+
setOperationAction(ISD::SELECT_CC, {MVT::f32, MVT::i32}, Custom);
setOperationAction(ISD::SETCC, {MVT::i32, MVT::f32}, Expand);
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index af08bf0861215..fbe3c9f5ac20b 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2757,11 +2757,6 @@ def : GCNPat <(i1 imm:$imm),
/********** Intrinsic Patterns **********/
/********** ================== **********/
-def : GCNPat <
- (f32 (fpow (VOP3Mods f32:$src0, i32:$src0_mods), (VOP3Mods f32:$src1, i32:$src1_mods))),
- (V_EXP_F32_e64 SRCMODS.NONE, (V_MUL_LEGACY_F32_e64 $src1_mods, $src1, SRCMODS.NONE, (V_LOG_F32_e64 $src0_mods, $src0), 0, 0))
->;
-
def : GCNPat <
(i32 (sext i1:$src0)),
(V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll
new file mode 100644
index 0000000000000..01c99e7731ef3
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll
@@ -0,0 +1,74 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
+
+; With real true16 instructions s16 values live in 16-bit register classes,
+; and folding an fpext into a mix instruction's 32-bit source operand leaves
+; an unselectable 16-bit def. Check that the fold is skipped instead of
+; crashing the selector.
+
+define float @v_mul_f32_fpext_f16(half %x, half %y) {
+; GFX11-TRUE16-LABEL: v_mul_f32_fpext_f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_mul_f32_fpext_f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+ %ex = fpext half %x to float
+ %ey = fpext half %y to float
+ %mul = fmul float %ex, %ey
+ ret float %mul
+}
+
+define float @v_fma_f32_fpext_f16(half %x, half %y, float %z) {
+; GFX11-TRUE16-LABEL: v_fma_f32_fpext_f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v0, v0, v1, v2
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fma_f32_fpext_f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+ %ex = fpext half %x to float
+ %ey = fpext half %y to float
+ %fma = call float @llvm.fma.f32(float %ex, float %ey, float %z)
+ ret float %fma
+}
+
+define float @v_fma_f32_fpext_fneg_f16(half %x, half %y, float %z) {
+; GFX11-TRUE16-LABEL: v_fma_f32_fpext_fneg_f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v0, v0, v1, v2
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fma_f32_fpext_fneg_f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,0]
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+ %neg.x = fneg half %x
+ %ex = fpext half %neg.x to float
+ %ey = fpext half %y to float
+ %fma = call float @llvm.fma.f32(float %ex, float %ey, float %z)
+ ret float %fma
+}
+
+declare float @llvm.fma.f32(float, float, float)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
index b84ec70d3e35d..6a48a4b2a219f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
@@ -11,116 +11,190 @@ define float @v_pow_f32(float %x, float %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_not_b32_e32 v1, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_not_b32_e32 v1, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_not_b32_e32 v1, 63
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e32 v5, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX10-NEXT: v_log_f32_e32 v2, v2
+; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX10-NEXT: v_trunc_f32_e32 v6, v3
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v6, v3
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX10-NEXT: v_exp_f32_e32 v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, s5
+; GFX10-NEXT: v_cmp_class_f32_e64 s5, v0, 24
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX10-NEXT: s_xor_b32 s4, s4, exec_lo
+; GFX10-NEXT: s_and_b32 s4, s5, s4
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: v_trunc_f32_e32 v5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_and_b32 vcc_lo, s0, s1
+; GFX11-NEXT: v_cmp_class_f32_e64 s1, v0, 24
+; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX11-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_and_b32 s0, s1, s0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow
@@ -131,189 +205,330 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v4, 0x800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v4
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 5, v5
-; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v5
-; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v4
-; GFX6-NEXT: v_log_f32_e32 v1, v1
-; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
-; GFX6-NEXT: v_sub_f32_e32 v0, v0, v6
-; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2
-; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
-; GFX6-NEXT: v_sub_f32_e32 v1, v1, v5
-; GFX6-NEXT: v_mov_b32_e32 v6, 0x42800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
-; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
+; GFX6-NEXT: v_ldexp_f32_e64 v5, |v0|, v5
+; GFX6-NEXT: v_log_f32_e32 v5, v5
+; GFX6-NEXT: v_mov_b32_e32 v6, 0x42000000
; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v7
-; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX6-NEXT: v_exp_f32_e32 v1, v1
-; GFX6-NEXT: v_not_b32_e32 v4, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
-; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v8, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v5, v5, v7
+; GFX6-NEXT: v_mul_legacy_f32_e32 v5, v2, v5
+; GFX6-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v5, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX6-NEXT: v_add_f32_e32 v5, v5, v9
+; GFX6-NEXT: v_exp_f32_e32 v5, v5
+; GFX6-NEXT: v_not_b32_e32 v9, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
+; GFX6-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24
+; GFX6-NEXT: v_ldexp_f32_e32 v5, v5, v10
+; GFX6-NEXT: v_trunc_f32_e32 v10, v2
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v10, v2
+; GFX6-NEXT: v_mul_f32_e32 v2, 0.5, v2
+; GFX6-NEXT: v_trunc_f32_e32 v10, v2
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v2
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 1.0, v0, s[4:5]
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; GFX6-NEXT: v_ldexp_f32_e64 v0, |v1|, v0
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_and_b32_e32 v5, 0x7fffffff, v5
+; GFX6-NEXT: v_and_b32_e32 v2, 0x80000000, v2
+; GFX6-NEXT: v_or_b32_e32 v2, v5, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v5
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v3, v0
+; GFX6-NEXT: s_xor_b64 s[10:11], vcc, exec
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v5
+; GFX6-NEXT: v_exp_f32_e32 v5, v0
+; GFX6-NEXT: v_mov_b32_e32 v4, 0x7fc00000
+; GFX6-NEXT: s_and_b64 s[4:5], s[8:9], s[10:11]
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v9, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v5, v2
+; GFX6-NEXT: v_trunc_f32_e32 v5, v3
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v3
+; GFX6-NEXT: v_mul_f32_e32 v3, 0.5, v3
+; GFX6-NEXT: v_trunc_f32_e32 v5, v3
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v3
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 1.0, v1, s[4:5]
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v3
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
+; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_v2f32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, 0x800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v4
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v5, 5, v5
-; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_ldexp_f32 v1, v1, v4
-; GFX8-NEXT: v_log_f32_e32 v1, v1
-; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
-; GFX8-NEXT: v_sub_f32_e32 v0, v0, v6
-; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
-; GFX8-NEXT: v_sub_f32_e32 v1, v1, v5
-; GFX8-NEXT: v_mov_b32_e32 v6, 0x42800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX8-NEXT: v_log_f32_e32 v5, v5
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x42000000
; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v7
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX8-NEXT: v_exp_f32_e32 v1, v1
-; GFX8-NEXT: v_not_b32_e32 v4, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
-; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v8, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v5, v5, v7
+; GFX8-NEXT: v_mul_legacy_f32_e32 v5, v2, v5
+; GFX8-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v5, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX8-NEXT: v_add_f32_e32 v5, v5, v9
+; GFX8-NEXT: v_exp_f32_e32 v5, v5
+; GFX8-NEXT: v_not_b32_e32 v9, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24
+; GFX8-NEXT: v_ldexp_f32 v5, v5, v10
+; GFX8-NEXT: v_trunc_f32_e32 v10, v2
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v10, v2
+; GFX8-NEXT: v_mul_f32_e32 v2, 0.5, v2
+; GFX8-NEXT: v_trunc_f32_e32 v10, v2
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v2
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 1.0, v0, s[4:5]
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; GFX8-NEXT: v_ldexp_f32 v0, |v1|, v0
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_and_b32_e32 v5, 0x7fffffff, v5
+; GFX8-NEXT: v_and_b32_e32 v2, 0x80000000, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v5, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v5
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v3, v0
+; GFX8-NEXT: s_xor_b64 s[10:11], vcc, exec
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v5
+; GFX8-NEXT: v_exp_f32_e32 v5, v0
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x7fc00000
+; GFX8-NEXT: s_and_b64 s[4:5], s[8:9], s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v9, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v5, v2
+; GFX8-NEXT: v_trunc_f32_e32 v5, v3
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v3
+; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v3
+; GFX8-NEXT: v_trunc_f32_e32 v5, v3
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v3
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, 1.0, v1, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v3
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
+; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_v2f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v4, 0x800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v4
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 5, v5
-; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v5
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_ldexp_f32 v1, v1, v4
-; GFX9-NEXT: v_log_f32_e32 v1, v1
-; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
-; GFX9-NEXT: v_sub_f32_e32 v0, v0, v6
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v2
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
-; GFX9-NEXT: v_sub_f32_e32 v1, v1, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, 0x42800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX9-NEXT: v_log_f32_e32 v5, v5
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x42000000
; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
-; GFX9-NEXT: v_add_f32_e32 v0, v0, v7
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX9-NEXT: v_exp_f32_e32 v1, v1
-; GFX9-NEXT: v_not_b32_e32 v4, 63
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
-; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v8, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v5, v5, v7
+; GFX9-NEXT: v_mul_legacy_f32_e32 v5, v2, v5
+; GFX9-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v5, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v5, v5, v9
+; GFX9-NEXT: v_exp_f32_e32 v5, v5
+; GFX9-NEXT: v_not_b32_e32 v9, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24
+; GFX9-NEXT: v_ldexp_f32 v5, v5, v10
+; GFX9-NEXT: v_trunc_f32_e32 v10, v2
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v10, v2
+; GFX9-NEXT: v_mul_f32_e32 v2, 0.5, v2
+; GFX9-NEXT: v_trunc_f32_e32 v10, v2
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v2
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 1.0, v0, s[4:5]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; GFX9-NEXT: v_ldexp_f32 v0, |v1|, v0
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_bfrev_b32_e32 v10, -2
+; GFX9-NEXT: v_and_b32_e32 v2, 0x80000000, v2
+; GFX9-NEXT: v_and_or_b32 v2, v5, v10, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v5
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v3, v0
+; GFX9-NEXT: s_xor_b64 s[10:11], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v5
+; GFX9-NEXT: v_exp_f32_e32 v5, v0
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x7fc00000
+; GFX9-NEXT: s_and_b64 s[4:5], s[8:9], s[10:11]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v9, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v5, v2
+; GFX9-NEXT: v_trunc_f32_e32 v5, v3
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v3
+; GFX9-NEXT: v_mul_f32_e32 v3, 0.5, v3
+; GFX9-NEXT: v_trunc_f32_e32 v5, v3
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v3
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 1.0, v1, s[4:5]
+; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v3
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
+; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX9-NEXT: v_and_or_b32 v2, v2, v10, v3
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v1|
+; GFX10-NEXT: v_mul_f32_e32 v9, 0.5, v3
+; GFX10-NEXT: v_trunc_f32_e32 v8, v3
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s5
+; GFX10-NEXT: v_cmp_eq_f32_e64 s7, v8, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 5, v5
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v4
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s4
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_log_f32_e32 v1, v1
-; GFX10-NEXT: v_sub_f32_e32 v0, v0, v4
-; GFX10-NEXT: v_sub_f32_e32 v1, v1, v5
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s4
-; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s4
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
-; GFX10-NEXT: v_exp_f32_e32 v1, v1
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX10-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX10-NEXT: v_ldexp_f32 v5, |v1|, v5
+; GFX10-NEXT: v_log_f32_e32 v4, v4
+; GFX10-NEXT: v_log_f32_e32 v5, v5
+; GFX10-NEXT: v_sub_f32_e32 v4, v4, v6
+; GFX10-NEXT: v_sub_f32_e32 v5, v5, v7
+; GFX10-NEXT: v_mul_f32_e32 v7, 0.5, v2
+; GFX10-NEXT: v_trunc_f32_e32 v6, v2
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v2, v4
+; GFX10-NEXT: v_mul_legacy_f32_e32 v5, v3, v5
+; GFX10-NEXT: v_trunc_f32_e32 v12, v7
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v6, v2
+; GFX10-NEXT: v_trunc_f32_e32 v2, v9
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v5
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v12, v7
+; GFX10-NEXT: v_cmp_lg_f32_e64 s8, v2, v9
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s4
+; GFX10-NEXT: s_and_b32 s6, s5, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v10
+; GFX10-NEXT: v_add_f32_e32 v5, v5, v11
+; GFX10-NEXT: s_xor_b32 s5, s5, exec_lo
+; GFX10-NEXT: s_and_b32 s4, s4, s5
+; GFX10-NEXT: v_exp_f32_e32 v2, v4
+; GFX10-NEXT: v_exp_f32_e32 v3, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 1.0, v0, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: s_and_b32 vcc_lo, s7, s8
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v1, 24
+; GFX10-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc_lo
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX10-NEXT: s_xor_b32 s7, s7, exec_lo
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v6
+; GFX10-NEXT: v_ldexp_f32 v3, v3, v7
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v2, v4
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
+; GFX10-NEXT: s_and_b32 s4, s6, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_v2f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, v1
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v1|
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: v_mul_f32_e32 v9, 0.5, v3
+; GFX11-NEXT: v_trunc_f32_e32 v8, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-NEXT: v_cmp_eq_f32_e64 s3, v8, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 5, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v5
-; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
-; GFX11-NEXT: v_log_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_dual_sub_f32 v1, v1, v5 :: v_dual_lshlrev_b32 v4, 5, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v4
-; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, vcc_lo
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, v1, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_ldexp_f32 v5, |v1|, v5
+; GFX11-NEXT: v_log_f32_e32 v5, v5
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v3
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_exp_f32_e32 v1, v1
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_dual_sub_f32 v5, v5, v7 :: v_dual_lshlrev_b32 v4, 5, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX11-NEXT: v_mul_f32_e32 v7, 0.5, v2
+; GFX11-NEXT: v_log_f32_e32 v4, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v12, v7
+; GFX11-NEXT: v_cmp_lg_f32_e64 s2, v12, v7
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_sub_f32_e32 v4, v4, v6
+; GFX11-NEXT: v_trunc_f32_e32 v6, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v4, v2, v4
+; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v6, v2
+; GFX11-NEXT: v_trunc_f32_e32 v2, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
+; GFX11-NEXT: s_and_b32 s2, s1, s2
+; GFX11-NEXT: v_cmp_lg_f32_e64 s4, v2, v9
+; GFX11-NEXT: s_xor_b32 s1, s1, exec_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mul_dx9_zero_f32 v5, v3, v5 :: v_dual_add_f32 v4, v4, v10
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v2, v4
+; GFX11-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 1.0, v0, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX11-NEXT: v_cmp_class_f32_e64 s2, v1, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_add_f32 v5, v5, v11 :: v_dual_and_b32 v4, 0x80000000, v4
+; GFX11-NEXT: s_and_b32 s0, s0, s1
+; GFX11-NEXT: v_exp_f32_e32 v3, v5
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_and_b32 vcc_lo, s3, s4
+; GFX11-NEXT: s_xor_b32 s3, s3, exec_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX11-NEXT: v_and_b32_e32 v5, 0x80000000, v6
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX11-NEXT: v_ldexp_f32 v3, v3, v7
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v2, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-NEXT: s_and_b32 s0, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y)
ret <2 x float> %pow
@@ -324,80 +539,253 @@ define half @v_pow_f16(half %x, half %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
-; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_not_b32_e32 v1, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_log_f16_e32 v0, v0
-; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_exp_f16_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_log_f16_e32 v0, v0
-; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT: v_exp_f16_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_log_f16_e32 v0, v0
-; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v1
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e32 v5, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX10-NEXT: v_log_f32_e32 v2, v2
+; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mov_b32_e32 v3, 0.5
+; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v4, v2
+; GFX10-NEXT: v_fma_mix_f32 v1, v1, v3, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX10-NEXT: v_trunc_f32_e32 v6, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v6, v1
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_exp_f32_e32 v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, s5
+; GFX10-NEXT: v_cmp_class_f32_e64 s5, v0, 24
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX10-NEXT: s_xor_b32 s4, s4, exec_lo
+; GFX10-NEXT: s_and_b32 s4, s5, s4
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX10-NEXT: v_exp_f16_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_pow_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, s1
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_exp_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v5, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mov_b32 v3, 0.5
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v4, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v3, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v6, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, s1
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_exp_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%pow = call half @llvm.pow.f16(half %x, half %y)
ret half %pow
@@ -408,34 +796,77 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x800000
+; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX6-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX6-NEXT: v_ldexp_f32_e64 v4, |v2|, v4
+; GFX6-NEXT: v_log_f32_e32 v4, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX6-NEXT: v_mov_b32_e32 v8, 0x42800000
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX6-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX6-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX6-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX6-NEXT: v_exp_f32_e32 v4, v4
+; GFX6-NEXT: v_not_b32_e32 v9, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_cvt_f32_f16_e32 v4, v1
-; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v10
+; GFX6-NEXT: v_trunc_f32_e32 v10, v5
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5
+; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v5
+; GFX6-NEXT: v_trunc_f32_e32 v10, v5
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: s_xor_b64 s[8:9], vcc, exec
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_log_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
-; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v2, v4
-; GFX6-NEXT: v_mov_b32_e32 v5, 0x42800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
-; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v5, vcc
-; GFX6-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX6-NEXT: v_not_b32_e32 v4, 63
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v4, vcc
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v3
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX6-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
+; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX6-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v5
; GFX6-NEXT: v_exp_f32_e32 v2, v2
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_ldexp_f32_e32 v1, v2, v6
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_trunc_f32_e32 v5, v1
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v5, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
-; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
+; GFX6-NEXT: v_bfe_u32 v1, v4, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -443,19 +874,75 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX8-LABEL: v_pow_v2f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_log_f16_e32 v2, v0
-; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x800000
+; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX8-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX8-NEXT: v_log_f32_e32 v4, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX8-NEXT: v_mov_b32_e32 v8, 0x42800000
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX8-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX8-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX8-NEXT: v_exp_f32_e32 v4, v4
+; GFX8-NEXT: v_not_b32_e32 v9, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_ldexp_f32 v4, v4, v10
+; GFX8-NEXT: v_trunc_f32_e32 v10, v5
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5
+; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v5
+; GFX8-NEXT: v_trunc_f32_e32 v10, v5
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: s_xor_b64 s[8:9], vcc, exec
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
+; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX8-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v4
; GFX8-NEXT: v_mov_b32_e32 v2, 16
-; GFX8-NEXT: v_exp_f16_e32 v0, v0
-; GFX8-NEXT: v_exp_f16_e32 v1, v1
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -463,83 +950,305 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX9-LABEL: v_pow_v2f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_log_f16_e32 v2, v0
-; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x800000
+; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX9-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX9-NEXT: v_log_f32_e32 v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX9-NEXT: v_mov_b32_e32 v8, 0x42800000
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX9-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX9-NEXT: v_exp_f32_e32 v4, v4
+; GFX9-NEXT: v_not_b32_e32 v9, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX9-NEXT: v_ldexp_f32 v4, v4, v10
+; GFX9-NEXT: v_trunc_f32_e32 v10, v5
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5
+; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v5
+; GFX9-NEXT: v_trunc_f32_e32 v10, v5
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: s_xor_b64 s[8:9], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: v_bfrev_b32_e32 v10, -2
+; GFX9-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX9-NEXT: v_and_or_b32 v4, v4, v10, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX9-NEXT: v_and_or_b32 v1, v2, v10, v1
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT: v_exp_f16_e32 v1, v1
-; GFX9-NEXT: v_exp_f16_e32 v0, v0
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-NEXT: v_pack_b32_f16 v0, v4, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_log_f16_e32 v2, v0
-; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_f16_e32 v8, v1
+; GFX10-NEXT: v_mov_b32_e32 v7, 0.5
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX10-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX10-NEXT: v_log_f32_e32 v3, v3
+; GFX10-NEXT: v_log_f32_e32 v4, v4
+; GFX10-NEXT: v_sub_f32_e32 v3, v3, v5
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_sub_f32_e32 v4, v4, v6
+; GFX10-NEXT: v_fma_mix_f32 v6, v1, v7, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_fma_mix_f32 v1, v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v8, v3
+; GFX10-NEXT: v_trunc_f32_e32 v7, v8
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_trunc_f32_e32 v9, v6
+; GFX10-NEXT: v_trunc_f32_e32 v12, v5
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX10-NEXT: v_trunc_f32_e32 v13, v1
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v7, v8
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v9, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e64 s7, v12, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s4
+; GFX10-NEXT: v_cmp_lg_f32_e64 s8, v13, v1
+; GFX10-NEXT: s_and_b32 s6, s5, s6
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v11
+; GFX10-NEXT: s_and_b32 vcc_lo, s7, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_exp_f32_e32 v1, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_exp_f32_e32 v3, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s6
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, v2, 24
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
+; GFX10-NEXT: s_xor_b32 s5, s5, exec_lo
+; GFX10-NEXT: s_xor_b32 s7, s7, exec_lo
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX10-NEXT: s_and_b32 s4, s4, s5
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v6
+; GFX10-NEXT: v_ldexp_f32 v3, v3, v7
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
+; GFX10-NEXT: s_and_b32 s4, s6, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX10-NEXT: v_exp_f16_e32 v1, v1
-; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_pow_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v1
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, 0.5, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, v8, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v2, v3, v2 :: v_dual_mul_dx9_zero_f32 v1, v0, v1
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v2
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v6, 0.5, v7
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v1, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v11
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v5, v7
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, s2
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s4, v5, v9
+; GFX11-TRUE16-NEXT: s_xor_b32 s1, s1, exec_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s3, s4
+; GFX11-TRUE16-NEXT: s_xor_b32 s3, s3, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, 1.0, v0 :: v_dual_add_f32 v3, v3, v10
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v3
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s2
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0x80000000, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, v7
+; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GFX11-TRUE16-NEXT: v_exp_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_exp_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_v2f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_log_f16_e32 v2, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v1, v2, v1 :: v_dual_mul_dx9_zero_f32 v0, v0, v3
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v8, v1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, 0.5
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_dual_sub_f32 v3, v3, v5 :: v_dual_lshlrev_b32 v4, 5, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v1, v6, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v8
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v8, v3
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v6, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v4, v9
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s2, v9, v5
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s0, s2
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, v4, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 1.0, v0, s2
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v5, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, s1
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s3
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, 1.0, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s3, v2, 24
+; GFX11-FAKE16-NEXT: s_xor_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v3, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0x80000000, v7
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v1, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s3, s2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_exp_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_exp_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y)
ret <2 x half> %pow
@@ -551,34 +1260,77 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x800000
+; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX6-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX6-NEXT: v_ldexp_f32_e64 v4, |v2|, v4
+; GFX6-NEXT: v_log_f32_e32 v4, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX6-NEXT: v_mov_b32_e32 v8, 0x42800000
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX6-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX6-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX6-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX6-NEXT: v_exp_f32_e32 v4, v4
+; GFX6-NEXT: v_not_b32_e32 v9, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_cvt_f32_f16_e32 v4, v1
-; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v10
+; GFX6-NEXT: v_trunc_f32_e32 v10, v5
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5
+; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v5
+; GFX6-NEXT: v_trunc_f32_e32 v10, v5
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: s_xor_b64 s[8:9], vcc, exec
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_log_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
-; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v2, v4
-; GFX6-NEXT: v_mov_b32_e32 v5, 0x42800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
-; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v5, vcc
-; GFX6-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX6-NEXT: v_not_b32_e32 v4, 63
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v4, vcc
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v3
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX6-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
+; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX6-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v5
; GFX6-NEXT: v_exp_f32_e32 v2, v2
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_ldexp_f32_e32 v1, v2, v6
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_trunc_f32_e32 v5, v1
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v5, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
-; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
+; GFX6-NEXT: v_bfe_u32 v1, v4, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -587,19 +1339,75 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX8-NEXT: v_log_f16_e32 v2, v0
-; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x800000
+; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX8-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX8-NEXT: v_log_f32_e32 v4, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX8-NEXT: v_mov_b32_e32 v8, 0x42800000
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX8-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX8-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX8-NEXT: v_exp_f32_e32 v4, v4
+; GFX8-NEXT: v_not_b32_e32 v9, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_ldexp_f32 v4, v4, v10
+; GFX8-NEXT: v_trunc_f32_e32 v10, v5
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5
+; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v5
+; GFX8-NEXT: v_trunc_f32_e32 v10, v5
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: s_xor_b64 s[8:9], vcc, exec
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
+; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX8-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v4
; GFX8-NEXT: v_mov_b32_e32 v2, 16
-; GFX8-NEXT: v_exp_f16_e32 v0, v0
-; GFX8-NEXT: v_exp_f16_e32 v1, v1
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -608,88 +1416,310 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX9-NEXT: v_log_f16_e32 v2, v0
-; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x800000
+; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX9-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX9-NEXT: v_log_f32_e32 v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX9-NEXT: v_mov_b32_e32 v8, 0x42800000
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX9-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX9-NEXT: v_exp_f32_e32 v4, v4
+; GFX9-NEXT: v_not_b32_e32 v9, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX9-NEXT: v_ldexp_f32 v4, v4, v10
+; GFX9-NEXT: v_trunc_f32_e32 v10, v5
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5
+; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v5
+; GFX9-NEXT: v_trunc_f32_e32 v10, v5
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: s_xor_b64 s[8:9], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: v_bfrev_b32_e32 v10, -2
+; GFX9-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX9-NEXT: v_and_or_b32 v4, v4, v10, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX9-NEXT: v_and_or_b32 v1, v2, v10, v1
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT: v_exp_f16_e32 v1, v1
-; GFX9-NEXT: v_exp_f16_e32 v0, v0
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-NEXT: v_pack_b32_f16 v0, v4, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f16_fneg_lhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_log_f16_e32 v2, v0
-; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX10-NEXT: v_cvt_f32_f16_e32 v8, v1
+; GFX10-NEXT: v_mov_b32_e32 v7, 0.5
+; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX10-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX10-NEXT: v_log_f32_e32 v3, v3
+; GFX10-NEXT: v_log_f32_e32 v4, v4
+; GFX10-NEXT: v_sub_f32_e32 v3, v3, v5
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_sub_f32_e32 v4, v4, v6
+; GFX10-NEXT: v_fma_mix_f32 v6, v1, v7, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_fma_mix_f32 v1, v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v8, v3
+; GFX10-NEXT: v_trunc_f32_e32 v7, v8
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_trunc_f32_e32 v9, v6
+; GFX10-NEXT: v_trunc_f32_e32 v12, v5
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX10-NEXT: v_trunc_f32_e32 v13, v1
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v7, v8
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v9, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e64 s7, v12, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s4
+; GFX10-NEXT: v_cmp_lg_f32_e64 s8, v13, v1
+; GFX10-NEXT: s_and_b32 s6, s5, s6
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v11
+; GFX10-NEXT: s_and_b32 vcc_lo, s7, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_exp_f32_e32 v1, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_exp_f32_e32 v3, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s6
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, v2, 24
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
+; GFX10-NEXT: s_xor_b32 s5, s5, exec_lo
+; GFX10-NEXT: s_xor_b32 s7, s7, exec_lo
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX10-NEXT: s_and_b32 s4, s4, s5
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v6
+; GFX10-NEXT: v_ldexp_f32 v3, v3, v7
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
+; GFX10-NEXT: s_and_b32 s4, s6, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX10-NEXT: v_exp_f16_e32 v1, v1
-; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_lhs:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v1
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, 0.5, v1
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, v8, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v2, v3, v2 :: v_dual_mul_dx9_zero_f32 v1, v0, v1
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v2
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v6, 0.5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v1, v4
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v12, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v5, v7
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, s2
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s4, v5, v9
+; GFX11-TRUE16-NEXT: s_xor_b32 s1, s1, exec_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s3, s4
+; GFX11-TRUE16-NEXT: s_xor_b32 s3, s3, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, 1.0, v0 :: v_dual_add_f32 v3, v3, v10
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v3
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s2
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0x80000000, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, v7
+; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GFX11-TRUE16-NEXT: v_exp_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_exp_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_lhs:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_log_f16_e32 v2, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v8, v1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, 0.5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v1, v2, v1 :: v_dual_mul_dx9_zero_f32 v0, v0, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v7
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_dual_sub_f32 v3, v3, v5 :: v_dual_lshlrev_b32 v4, 5, v4
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v1, v6, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v8
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v8, v3
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v6, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v4, v9
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s2, v9, v5
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s0, s2
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, v4, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 1.0, v0, s2
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v5, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, s1
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s3
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, 1.0, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s3, v2, 24
+; GFX11-FAKE16-NEXT: s_xor_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v3, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0x80000000, v7
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v1, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s3, s2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_exp_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: v_exp_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%x.fneg = fneg <2 x half> %x
%pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y)
@@ -701,35 +1731,78 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x800000
; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX6-NEXT: v_ldexp_f32_e64 v4, |v2|, v4
+; GFX6-NEXT: v_log_f32_e32 v4, v4
+; GFX6-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX6-NEXT: v_mov_b32_e32 v8, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX6-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX6-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX6-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX6-NEXT: v_exp_f32_e32 v4, v4
+; GFX6-NEXT: v_not_b32_e32 v9, 63
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v10
+; GFX6-NEXT: v_trunc_f32_e32 v10, v5
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5
+; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v5
+; GFX6-NEXT: v_trunc_f32_e32 v10, v5
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: s_xor_b64 s[8:9], vcc, exec
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_log_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mov_b32_e32 v4, 0xc2fc0000
-; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
-; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
+; GFX6-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
+; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX6-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
; GFX6-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX6-NEXT: v_not_b32_e32 v5, 63
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX6-NEXT: v_exp_f32_e32 v2, v2
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_ldexp_f32_e32 v1, v2, v6
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_trunc_f32_e32 v5, v1
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v5, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
-; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
+; GFX6-NEXT: v_bfe_u32 v1, v4, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -737,20 +1810,76 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX8-LABEL: v_pow_v2f16_fneg_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_log_f16_e32 v2, v0
-; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x800000
; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX8-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX8-NEXT: v_log_f32_e32 v4, v4
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX8-NEXT: v_mov_b32_e32 v8, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX8-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX8-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX8-NEXT: v_exp_f32_e32 v4, v4
+; GFX8-NEXT: v_not_b32_e32 v9, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_ldexp_f32 v4, v4, v10
+; GFX8-NEXT: v_trunc_f32_e32 v10, v5
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5
+; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v5
+; GFX8-NEXT: v_trunc_f32_e32 v10, v5
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: s_xor_b64 s[8:9], vcc, exec
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
+; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX8-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v4
; GFX8-NEXT: v_mov_b32_e32 v2, 16
-; GFX8-NEXT: v_exp_f16_e32 v0, v0
-; GFX8-NEXT: v_exp_f16_e32 v1, v1
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -758,88 +1887,311 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX9-LABEL: v_pow_v2f16_fneg_rhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_log_f16_e32 v2, v0
-; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x800000
; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX9-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX9-NEXT: v_log_f32_e32 v4, v4
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX9-NEXT: v_mov_b32_e32 v8, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX9-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX9-NEXT: v_exp_f32_e32 v4, v4
+; GFX9-NEXT: v_not_b32_e32 v9, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_ldexp_f32 v4, v4, v10
+; GFX9-NEXT: v_trunc_f32_e32 v10, v5
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5
+; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v5
+; GFX9-NEXT: v_trunc_f32_e32 v10, v5
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: s_xor_b64 s[8:9], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
-; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX9-NEXT: v_bfrev_b32_e32 v10, -2
+; GFX9-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX9-NEXT: v_and_or_b32 v4, v4, v10, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX9-NEXT: v_and_or_b32 v1, v2, v10, v1
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT: v_exp_f16_e32 v1, v2
-; GFX9-NEXT: v_exp_f16_e32 v0, v0
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-NEXT: v_pack_b32_f16 v0, v4, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f16_fneg_rhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_log_f16_e32 v2, v0
-; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
+; GFX10-NEXT: v_mov_b32_e32 v8, 0.5
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
+; GFX10-NEXT: v_cvt_f32_f16_e32 v9, v5
+; GFX10-NEXT: v_fma_mix_f32 v1, -v1, v8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX10-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX10-NEXT: v_log_f32_e32 v3, v3
+; GFX10-NEXT: v_log_f32_e32 v4, v4
+; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX10-NEXT: v_fma_mix_f32 v5, v5, v8, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_trunc_f32_e32 v8, v9
+; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v9, v3
+; GFX10-NEXT: v_trunc_f32_e32 v7, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_trunc_f32_e32 v12, v5
+; GFX10-NEXT: v_trunc_f32_e32 v13, v6
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v8, v9
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v12, v5
+; GFX10-NEXT: v_cmp_lg_f32_e64 s7, v7, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e64 s8, v13, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s4
+; GFX10-NEXT: s_and_b32 s6, s5, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v10
+; GFX10-NEXT: s_and_b32 vcc_lo, s8, s7
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v11
+; GFX10-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_exp_f32_e32 v1, v3
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, v2, 24
+; GFX10-NEXT: v_exp_f32_e32 v3, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s6
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
+; GFX10-NEXT: s_xor_b32 s5, s5, exec_lo
+; GFX10-NEXT: s_xor_b32 s7, s8, exec_lo
+; GFX10-NEXT: s_and_b32 s4, s4, s5
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v6
+; GFX10-NEXT: v_ldexp_f32 v3, v3, v7
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
+; GFX10-NEXT: s_and_b32 s4, s6, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX10-NEXT: v_exp_f16_e32 v1, v1
-; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_rhs:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_mul_f32 v9, 0.5, v1 :: v_dual_lshlrev_b32 v4, 5, v4
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, v8, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v2, v3, v2 :: v_dual_mul_dx9_zero_f32 v1, v0, v1
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v2
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v6, 0.5, v7
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v1, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v11
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v5, v7
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, s2
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s4, v5, v9
+; GFX11-TRUE16-NEXT: s_xor_b32 s1, s1, exec_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s3, s4
+; GFX11-TRUE16-NEXT: s_xor_b32 s3, s3, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, 1.0, v0 :: v_dual_add_f32 v3, v3, v10
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v3
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s2
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0x80000000, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, v7
+; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GFX11-TRUE16-NEXT: v_exp_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_exp_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_rhs:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_log_f16_e32 v2, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, 0.5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v5
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v9, v5
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v1
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s2, v11, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v7, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_dual_sub_f32 v4, v4, v10 :: v_dual_lshlrev_b32 v3, 5, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v1, v2, v1 :: v_dual_mul_dx9_zero_f32 v0, v0, v3
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v8
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v9
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_exp_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_exp_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v8, v9
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v1, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s0, s2
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 1.0, v0, s2
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v1, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, s1
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v9, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, s1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v8
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s3
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s3, v2, 24
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, 1.0, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v10
+; GFX11-FAKE16-NEXT: s_xor_b32 s2, s2, exec_lo
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v1, v6
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x80000000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v3, v5
+; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s3, s2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%y.fneg = fneg <2 x half> %y
%pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y.fneg)
@@ -852,35 +2204,78 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x800000
; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX6-NEXT: v_ldexp_f32_e64 v4, |v2|, v4
+; GFX6-NEXT: v_log_f32_e32 v4, v4
+; GFX6-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX6-NEXT: v_mov_b32_e32 v8, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX6-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX6-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX6-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX6-NEXT: v_exp_f32_e32 v4, v4
+; GFX6-NEXT: v_not_b32_e32 v9, 63
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v10
+; GFX6-NEXT: v_trunc_f32_e32 v10, v5
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5
+; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v5
+; GFX6-NEXT: v_trunc_f32_e32 v10, v5
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: s_xor_b64 s[8:9], vcc, exec
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_log_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mov_b32_e32 v4, 0xc2fc0000
-; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
-; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
+; GFX6-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
+; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX6-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
; GFX6-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX6-NEXT: v_not_b32_e32 v5, 63
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX6-NEXT: v_exp_f32_e32 v2, v2
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_ldexp_f32_e32 v1, v2, v6
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_trunc_f32_e32 v5, v1
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v5, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
-; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
+; GFX6-NEXT: v_bfe_u32 v1, v4, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -889,20 +2284,76 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX8-NEXT: v_log_f16_e32 v2, v0
-; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x800000
; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX8-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX8-NEXT: v_log_f32_e32 v4, v4
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX8-NEXT: v_mov_b32_e32 v8, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX8-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX8-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX8-NEXT: v_exp_f32_e32 v4, v4
+; GFX8-NEXT: v_not_b32_e32 v9, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_ldexp_f32 v4, v4, v10
+; GFX8-NEXT: v_trunc_f32_e32 v10, v5
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5
+; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v5
+; GFX8-NEXT: v_trunc_f32_e32 v10, v5
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: s_xor_b64 s[8:9], vcc, exec
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
+; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX8-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v4
; GFX8-NEXT: v_mov_b32_e32 v2, 16
-; GFX8-NEXT: v_exp_f16_e32 v0, v0
-; GFX8-NEXT: v_exp_f16_e32 v1, v1
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -911,40 +2362,144 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX9-NEXT: v_log_f16_e32 v2, v0
-; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x800000
; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX9-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX9-NEXT: v_log_f32_e32 v4, v4
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX9-NEXT: v_mov_b32_e32 v8, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX9-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_mov_b32_e32 v7, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX9-NEXT: v_exp_f32_e32 v4, v4
+; GFX9-NEXT: v_not_b32_e32 v9, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_ldexp_f32 v4, v4, v10
+; GFX9-NEXT: v_trunc_f32_e32 v10, v5
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5
+; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v5
+; GFX9-NEXT: v_trunc_f32_e32 v10, v5
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: s_xor_b64 s[8:9], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
-; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX9-NEXT: v_bfrev_b32_e32 v10, -2
+; GFX9-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX9-NEXT: v_and_or_b32 v4, v4, v10, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX9-NEXT: v_and_or_b32 v1, v2, v10, v1
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT: v_exp_f16_e32 v1, v2
-; GFX9-NEXT: v_exp_f16_e32 v0, v0
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-NEXT: v_pack_b32_f16 v0, v4, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX10-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX10-NEXT: v_log_f16_e32 v2, v0
-; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX10-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
+; GFX10-NEXT: v_mov_b32_e32 v8, 0.5
+; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_f16_e32 v9, v5
+; GFX10-NEXT: v_fma_mix_f32 v1, -v1, v8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX10-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX10-NEXT: v_log_f32_e32 v3, v3
+; GFX10-NEXT: v_log_f32_e32 v4, v4
+; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX10-NEXT: v_fma_mix_f32 v5, v5, v8, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_trunc_f32_e32 v8, v9
+; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v9, v3
+; GFX10-NEXT: v_trunc_f32_e32 v7, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_trunc_f32_e32 v12, v5
+; GFX10-NEXT: v_trunc_f32_e32 v13, v6
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v8, v9
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v12, v5
+; GFX10-NEXT: v_cmp_lg_f32_e64 s7, v7, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e64 s8, v13, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s4
+; GFX10-NEXT: s_and_b32 s6, s5, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v10
+; GFX10-NEXT: s_and_b32 vcc_lo, s8, s7
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v11
+; GFX10-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_exp_f32_e32 v1, v3
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, v2, 24
+; GFX10-NEXT: v_exp_f32_e32 v3, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s6
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
+; GFX10-NEXT: s_xor_b32 s5, s5, exec_lo
+; GFX10-NEXT: s_xor_b32 s7, s8, exec_lo
+; GFX10-NEXT: s_and_b32 s4, s4, s5
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v6
+; GFX10-NEXT: v_ldexp_f32 v3, v3, v7
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
+; GFX10-NEXT: s_and_b32 s4, s6, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX10-NEXT: v_exp_f16_e32 v1, v1
-; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_lhs_rhs:
@@ -952,52 +2507,171 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v1
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, 0.5, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, v8, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v2, v3, v2 :: v_dual_mul_dx9_zero_f32 v1, v0, v1
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v2
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v6, 0.5, v7
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v1, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v11
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v5, v7
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, s2
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s4, v5, v9
+; GFX11-TRUE16-NEXT: s_xor_b32 s1, s1, exec_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s3, s4
+; GFX11-TRUE16-NEXT: s_xor_b32 s3, s3, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, 1.0, v0 :: v_dual_add_f32 v3, v3, v10
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v3
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s2
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0x80000000, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, v7
+; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GFX11-TRUE16-NEXT: v_exp_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_exp_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_log_f16_e32 v2, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, 0.5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v5
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v9, v5
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v5
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v1
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s2, v11, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v7, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v1, v2, v1 :: v_dual_mul_dx9_zero_f32 v0, v0, v3
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_dual_sub_f32 v4, v4, v10 :: v_dual_lshlrev_b32 v3, 5, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v8
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v9
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_exp_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_exp_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v8, v9
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v1, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s0, s2
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 1.0, v0, s2
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v1, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, s1
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v9, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, s1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0x80000000, v5
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v8
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s3
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s3, v2, 24
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, 1.0, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v10
+; GFX11-FAKE16-NEXT: s_xor_b32 s2, s2, exec_lo
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v1, v6
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x80000000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v3, v5
+; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s3, s2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%x.fneg = fneg <2 x half> %x
%y.fneg = fneg <2 x half> %y
@@ -1019,21 +2693,36 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v2
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_not_b32_e32 v1, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, |v0|, s[4:5]
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], |v0|, 24
+; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fabs_lhs:
@@ -1043,21 +2732,36 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v2
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_not_b32_e32 v1, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, |v0|, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], |v0|, 24
+; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fabs_lhs:
@@ -1067,65 +2771,108 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v2
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_not_b32_e32 v1, 63
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, |v0|, s[4:5]
+; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], |v0|, 24
+; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_lhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e32 v5, v1
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX10-NEXT: v_log_f32_e32 v2, v2
+; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX10-NEXT: v_trunc_f32_e32 v6, v3
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v6, v3
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: s_and_b32 s5, s4, s5
+; GFX10-NEXT: s_xor_b32 s4, s4, exec_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 1.0, |v0|, s5
+; GFX10-NEXT: v_cmp_class_f32_e64 s5, |v0|, 24
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX10-NEXT: s_and_b32 s4, s5, s4
+; GFX10-NEXT: v_exp_f32_e32 v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_lhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_and_b32 s1, s0, s1
+; GFX11-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 1.0, |v0|, s1
+; GFX11-NEXT: v_cmp_class_f32_e64 s1, |v0|, 24
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX11-NEXT: s_and_b32 s0, s1, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
%pow = call float @llvm.pow.f32(float %fabs.x, float %y)
@@ -1137,116 +2884,190 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
-; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_not_b32_e32 v1, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_trunc_f32_e64 v3, |v1|
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, |v1|
+; GFX6-NEXT: v_mul_f32_e64 v1, |v1|, 0.5
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: s_xor_b64 s[4:5], s[6:7], exec
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fabs_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
-; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_not_b32_e32 v1, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_trunc_f32_e64 v3, |v1|
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, |v1|
+; GFX8-NEXT: v_mul_f32_e64 v1, |v1|, 0.5
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: s_xor_b64 s[4:5], s[6:7], exec
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fabs_rhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_not_b32_e32 v1, 63
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX9-NEXT: v_trunc_f32_e64 v3, |v1|
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, |v1|
+; GFX9-NEXT: v_mul_f32_e64 v1, |v1|, 0.5
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
+; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_rhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e64 v5, |v1|
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v5, |v1|
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX10-NEXT: s_xor_b32 s5, s6, exec_lo
+; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX10-NEXT: v_log_f32_e32 v2, v2
+; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
+; GFX10-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
+; GFX10-NEXT: v_trunc_f32_e32 v6, v3
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v6, v3
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX10-NEXT: v_exp_f32_e32 v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: s_and_b32 vcc_lo, s6, s4
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX10-NEXT: s_and_b32 s4, s4, s5
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_rhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: v_trunc_f32_e64 v5, |v1|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-NEXT: v_cmp_eq_f32_e64 s2, v5, |v1|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-NEXT: s_xor_b32 s1, s2, exec_lo
+; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, |v1|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
+; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v2, |v1|, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v6, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_and_b32 vcc_lo, s2, s0
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX11-NEXT: s_and_b32 s0, s0, s1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call float @llvm.fabs.f32(float %y)
%pow = call float @llvm.pow.f32(float %x, float %fabs.y)
@@ -1261,21 +3082,36 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v2
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
-; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_not_b32_e32 v1, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_trunc_f32_e64 v3, |v1|
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, |v1|
+; GFX6-NEXT: v_mul_f32_e64 v1, |v1|, 0.5
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX6-NEXT: s_and_b64 s[8:9], s[6:7], vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, |v0|, s[8:9]
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cmp_class_f32_e64 s[8:9], |v0|, 24
+; GFX6-NEXT: s_xor_b64 s[4:5], s[6:7], exec
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs:
@@ -1285,21 +3121,36 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v2
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
-; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_not_b32_e32 v1, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_trunc_f32_e64 v3, |v1|
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, |v1|
+; GFX8-NEXT: v_mul_f32_e64 v1, |v1|, 0.5
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX8-NEXT: s_and_b64 s[8:9], s[6:7], vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, |v0|, s[8:9]
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cmp_class_f32_e64 s[8:9], |v0|, 24
+; GFX8-NEXT: s_xor_b64 s[4:5], s[6:7], exec
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs:
@@ -1309,65 +3160,109 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v2
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_not_b32_e32 v1, 63
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX9-NEXT: v_trunc_f32_e64 v3, |v1|
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, |v1|
+; GFX9-NEXT: v_mul_f32_e64 v1, |v1|, 0.5
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX9-NEXT: s_and_b64 s[8:9], s[6:7], vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, |v0|, s[8:9]
+; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cmp_class_f32_e64 s[8:9], |v0|, 24
+; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e64 v5, |v1|
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v5, |v1|
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX10-NEXT: s_xor_b32 s5, s6, exec_lo
+; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX10-NEXT: v_log_f32_e32 v2, v2
+; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
+; GFX10-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
+; GFX10-NEXT: v_trunc_f32_e32 v6, v3
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v6, v3
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: s_and_b32 s4, s6, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 1.0, |v0|, s4
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, |v0|, 24
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX10-NEXT: s_and_b32 s4, s4, s5
+; GFX10-NEXT: v_exp_f32_e32 v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e64 v5, |v1|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-NEXT: v_cmp_eq_f32_e64 s2, v5, |v1|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: s_xor_b32 s1, s2, exec_lo
+; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, |v1|
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
+; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v2, |v1|, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v6, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_and_b32 s0, s2, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 1.0, |v0|, s0
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, |v0|, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX11-NEXT: s_and_b32 s0, s0, s1
+; GFX11-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
%fabs.y = call float @llvm.fabs.f32(float %y)
@@ -1379,126 +3274,223 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX6-LABEL: v_pow_f32_sgpr_vgpr:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
-; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[2:3], |s0|, v1
+; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_cselect_b32 s1, 1, 0
; GFX6-NEXT: s_lshl_b32 s2, s2, 5
; GFX6-NEXT: v_mov_b32_e32 v1, s2
-; GFX6-NEXT: v_ldexp_f32_e32 v1, s0, v1
+; GFX6-NEXT: v_ldexp_f32_e64 v1, |s0|, v1
; GFX6-NEXT: v_log_f32_e32 v1, v1
; GFX6-NEXT: s_cmp_lg_u32 s1, 0
-; GFX6-NEXT: s_cselect_b32 s0, 0x42000000, 0
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX6-NEXT: v_subrev_f32_e32 v1, s0, v1
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_not_b32_e32 v1, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: s_cselect_b32 s1, 0x42000000, 0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX6-NEXT: v_subrev_f32_e32 v1, s1, v1
+; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v0, v1
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX6-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_exp_f32_e32 v1, v1
+; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v2, s0
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v0
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GFX6-NEXT: v_trunc_f32_e32 v3, v0
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[2:3], v3, v0
+; GFX6-NEXT: s_and_b64 s[2:3], vcc, s[2:3]
+; GFX6-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
+; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e64 v0, 1.0, v2, s[2:3]
+; GFX6-NEXT: s_cselect_b32 s2, 1, 0
+; GFX6-NEXT: s_xor_b64 s[0:1], vcc, exec
+; GFX6-NEXT: s_cmp_lg_u32 s2, 0
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX6-NEXT: s_cselect_b64 s[2:3], exec, 0
+; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: v_pow_f32_sgpr_vgpr:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
-; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[2:3], |s0|, v1
+; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_lshl_b32 s2, s2, 5
; GFX8-NEXT: v_mov_b32_e32 v1, s2
-; GFX8-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX8-NEXT: v_ldexp_f32 v1, |s0|, v1
; GFX8-NEXT: v_log_f32_e32 v1, v1
; GFX8-NEXT: s_cmp_lg_u32 s1, 0
-; GFX8-NEXT: s_cselect_b32 s0, 0x42000000, 0
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX8-NEXT: v_subrev_f32_e32 v1, s0, v1
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_not_b32_e32 v1, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: s_cselect_b32 s1, 0x42000000, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX8-NEXT: v_subrev_f32_e32 v1, s1, v1
+; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v0, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX8-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX8-NEXT: v_exp_f32_e32 v1, v1
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v0
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v0
+; GFX8-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GFX8-NEXT: v_trunc_f32_e32 v3, v0
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[2:3], v3, v0
+; GFX8-NEXT: s_and_b64 s[2:3], vcc, s[2:3]
+; GFX8-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
+; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX8-NEXT: v_cndmask_b32_e64 v0, 1.0, v2, s[2:3]
+; GFX8-NEXT: s_cselect_b32 s2, 1, 0
+; GFX8-NEXT: s_xor_b64 s[0:1], vcc, exec
+; GFX8-NEXT: s_cmp_lg_u32 s2, 0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX8-NEXT: s_cselect_b64 s[2:3], exec, 0
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: v_pow_f32_sgpr_vgpr:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[2:3], |s0|, v1
+; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: s_lshl_b32 s2, s2, 5
; GFX9-NEXT: v_mov_b32_e32 v1, s2
-; GFX9-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX9-NEXT: v_ldexp_f32 v1, |s0|, v1
; GFX9-NEXT: v_log_f32_e32 v1, v1
; GFX9-NEXT: s_cmp_lg_u32 s1, 0
-; GFX9-NEXT: s_cselect_b32 s0, 0x42000000, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX9-NEXT: v_subrev_f32_e32 v1, s0, v1
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_not_b32_e32 v1, 63
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX9-NEXT: s_cselect_b32 s1, 0x42000000, 0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX9-NEXT: v_subrev_f32_e32 v1, s1, v1
+; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX9-NEXT: v_exp_f32_e32 v1, v1
+; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v0
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GFX9-NEXT: v_trunc_f32_e32 v3, v0
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[2:3], v3, v0
+; GFX9-NEXT: s_and_b64 s[2:3], vcc, s[2:3]
+; GFX9-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: v_cndmask_b32_e64 v0, 1.0, v2, s[2:3]
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_xor_b64 s[0:1], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u32 s2, 0
+; GFX9-NEXT: v_bfrev_b32_e32 v2, -2
+; GFX9-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX9-NEXT: s_cselect_b64 s[2:3], exec, 0
+; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: v_pow_f32_sgpr_vgpr:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0|
+; GFX10-NEXT: v_mul_f32_e32 v2, 0.5, v0
+; GFX10-NEXT: v_trunc_f32_e32 v4, v0
; GFX10-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10-NEXT: v_trunc_f32_e32 v5, v2
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: s_lshl_b32 s2, s2, 5
; GFX10-NEXT: s_cmp_lg_u32 s1, 0
-; GFX10-NEXT: v_ldexp_f32 v1, s0, s2
-; GFX10-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX10-NEXT: v_ldexp_f32 v1, |s0|, s2
+; GFX10-NEXT: s_cselect_b32 s1, 0x42000000, 0
+; GFX10-NEXT: v_cmp_lg_f32_e64 s2, v5, v2
; GFX10-NEXT: v_log_f32_e32 v1, v1
-; GFX10-NEXT: v_subrev_f32_e32 v1, s0, v1
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX10-NEXT: v_subrev_f32_e32 v1, s1, v1
+; GFX10-NEXT: v_cmp_eq_f32_e64 s1, v4, v0
+; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v0, v1
+; GFX10-NEXT: s_and_b32 s2, s1, s2
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX10-NEXT: v_exp_f32_e32 v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, s0, s2
+; GFX10-NEXT: v_cmp_class_f32_e64 s0, s0, 24
+; GFX10-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX10-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-NEXT: s_cselect_b32 s0, 1, 0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX10-NEXT: s_xor_b32 s1, s1, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-NEXT: s_cselect_b32 s0, exec_lo, 0
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v0, v1
+; GFX10-NEXT: s_and_b32 s0, s0, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_pow_f32_sgpr_vgpr:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0|
+; GFX11-NEXT: v_trunc_f32_e32 v4, v0
+; GFX11-NEXT: v_mul_f32_e32 v2, 0.5, v0
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-NEXT: s_cselect_b32 s1, 1, 0
; GFX11-NEXT: s_lshl_b32 s2, s2, 5
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
-; GFX11-NEXT: v_ldexp_f32 v1, s0, s2
-; GFX11-NEXT: s_cselect_b32 s0, 0x42000000, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_ldexp_f32 v1, |s0|, s2
+; GFX11-NEXT: s_cselect_b32 s1, 0x42000000, 0
+; GFX11-NEXT: v_trunc_f32_e32 v5, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v1, v1
+; GFX11-NEXT: v_cmp_lg_f32_e64 s2, v5, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_subrev_f32_e32 v1, s0, v1
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_subrev_f32_e32 v1, s1, v1
+; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v4, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, v0, v1
+; GFX11-NEXT: s_and_b32 s2, s1, s2
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11-NEXT: v_exp_f32_e32 v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, s0, s2
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, s0, 24
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX11-NEXT: s_xor_b32 s1, s1, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-NEXT: s_cselect_b32 s0, exec_lo, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v0, v1
+; GFX11-NEXT: s_and_b32 s0, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow
@@ -1508,112 +3500,226 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX6-LABEL: v_pow_f32_vgpr_sgpr:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
-; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_not_b32_e32 v1, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_ldexp_f32_e64 v1, |v0|, v1
+; GFX6-NEXT: v_log_f32_e32 v1, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v1, s0, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX6-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_exp_f32_e32 v1, v1
+; GFX6-NEXT: v_not_b32_e32 v2, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, s0
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, s0, v2
+; GFX6-NEXT: v_mul_f32_e64 v2, s0, 0.5
+; GFX6-NEXT: v_trunc_f32_e32 v3, v2
+; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX6-NEXT: s_cselect_b32 s2, 1, 0
+; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GFX6-NEXT: s_cselect_b32 s0, 1, 0
+; GFX6-NEXT: s_and_b32 s0, s2, s0
+; GFX6-NEXT: s_cmp_lg_u32 s0, 0
+; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX6-NEXT: s_xor_b32 s2, s2, 1
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; GFX6-NEXT: s_cmp_lg_u32 s2, 0
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX6-NEXT: v_and_b32_e32 v2, 0x80000000, v2
+; GFX6-NEXT: v_cmp_class_f32_e64 s[0:1], v0, 24
+; GFX6-NEXT: s_cselect_b64 s[2:3], exec, 0
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: v_pow_f32_vgpr_sgpr:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
-; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_not_b32_e32 v1, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: v_ldexp_f32 v1, |v0|, v1
+; GFX8-NEXT: v_log_f32_e32 v1, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v1, s0, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX8-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX8-NEXT: v_exp_f32_e32 v1, v1
+; GFX8-NEXT: v_not_b32_e32 v2, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX8-NEXT: v_trunc_f32_e32 v2, s0
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, s0, v2
+; GFX8-NEXT: v_mul_f32_e64 v2, s0, 0.5
+; GFX8-NEXT: v_trunc_f32_e32 v3, v2
+; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX8-NEXT: s_cselect_b32 s2, 1, 0
+; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX8-NEXT: s_cselect_b32 s0, 1, 0
+; GFX8-NEXT: s_and_b32 s0, s2, s0
+; GFX8-NEXT: s_cmp_lg_u32 s0, 0
+; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX8-NEXT: s_xor_b32 s2, s2, 1
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; GFX8-NEXT: s_cmp_lg_u32 s2, 0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX8-NEXT: v_and_b32_e32 v2, 0x80000000, v2
+; GFX8-NEXT: v_cmp_class_f32_e64 s[0:1], v0, 24
+; GFX8-NEXT: s_cselect_b64 s[2:3], exec, 0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: v_pow_f32_vgpr_sgpr:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX9-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_not_b32_e32 v1, 63
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX9-NEXT: v_ldexp_f32 v1, |v0|, v1
+; GFX9-NEXT: v_log_f32_e32 v1, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v1, s0, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX9-NEXT: v_exp_f32_e32 v1, v1
+; GFX9-NEXT: v_not_b32_e32 v2, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX9-NEXT: v_trunc_f32_e32 v2, s0
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, s0, v2
+; GFX9-NEXT: v_mul_f32_e64 v2, s0, 0.5
+; GFX9-NEXT: v_trunc_f32_e32 v3, v2
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-NEXT: s_and_b32 s0, s2, s0
+; GFX9-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX9-NEXT: s_xor_b32 s2, s2, 1
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; GFX9-NEXT: s_cmp_lg_u32 s2, 0
+; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
+; GFX9-NEXT: v_and_b32_e32 v2, 0x80000000, v2
+; GFX9-NEXT: v_cmp_class_f32_e64 s[0:1], v0, 24
+; GFX9-NEXT: s_cselect_b64 s[2:3], exec, 0
+; GFX9-NEXT: v_and_or_b32 v1, v1, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: v_pow_f32_vgpr_sgpr:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX10-NEXT: v_mul_f32_e64 v3, s0, 0.5
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s1
+; GFX10-NEXT: v_trunc_f32_e32 v4, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX10-NEXT: v_ldexp_f32 v1, |v0|, v1
+; GFX10-NEXT: v_log_f32_e32 v1, v1
+; GFX10-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_trunc_f32_e32 v2, s0
+; GFX10-NEXT: v_mul_legacy_f32_e32 v1, s0, v1
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, s0, v2
+; GFX10-NEXT: v_cmp_lg_f32_e64 s0, v4, v3
+; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0xc2fc0000, v1
+; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, s1
+; GFX10-NEXT: s_cselect_b32 s0, 1, 0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s1
+; GFX10-NEXT: s_and_b32 s0, s2, s0
+; GFX10-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX10-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
+; GFX10-NEXT: s_xor_b32 s1, s2, 1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX10-NEXT: v_exp_f32_e32 v1, v1
+; GFX10-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v2
+; GFX10-NEXT: s_cselect_b32 s1, exec_lo, 0
+; GFX10-NEXT: s_and_b32 s0, s0, s1
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_pow_f32_vgpr_sgpr:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-NEXT: v_mul_f32_e64 v3, s0, 0.5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s1
+; GFX11-NEXT: v_trunc_f32_e32 v4, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: v_ldexp_f32 v1, |v0|, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_log_f32_e32 v1, v1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_trunc_f32_e32 v2, s0
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, s0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, s0, v2
+; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v4, v3
+; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0xc2fc0000, v1
+; GFX11-NEXT: s_cmp_lg_u32 vcc_lo, 0
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, s1
+; GFX11-NEXT: s_cselect_b32 s0, 1, 0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s1
+; GFX11-NEXT: s_and_b32 s0, s2, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
+; GFX11-NEXT: s_xor_b32 s1, s2, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc_lo
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX11-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-NEXT: s_cmp_lg_u32 s1, 0
+; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v2
+; GFX11-NEXT: s_cselect_b32 s1, exec_lo, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_and_b32 s0, s0, s1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow
@@ -1623,125 +3729,249 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX6-LABEL: v_pow_f32_sgpr_sgpr:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[2:3], |s0|, v0
+; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
; GFX6-NEXT: s_cselect_b32 s3, 1, 0
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_lshl_b32 s3, s3, 5
; GFX6-NEXT: v_mov_b32_e32 v0, s3
-; GFX6-NEXT: v_ldexp_f32_e32 v0, s0, v0
+; GFX6-NEXT: v_ldexp_f32_e64 v0, |s0|, v0
; GFX6-NEXT: v_log_f32_e32 v0, v0
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
-; GFX6-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX6-NEXT: s_cselect_b32 s2, 0x42000000, 0
; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX6-NEXT: v_subrev_f32_e32 v0, s0, v0
+; GFX6-NEXT: v_subrev_f32_e32 v0, s2, v0
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
-; GFX6-NEXT: s_cselect_b32 s0, 0x42800000, 0
-; GFX6-NEXT: v_add_f32_e32 v0, s0, v0
+; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GFX6-NEXT: s_cselect_b32 s2, 0x42800000, 0
+; GFX6-NEXT: v_add_f32_e32 v0, s2, v0
; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
-; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s0
+; GFX6-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s2
+; GFX6-NEXT: v_readfirstlane_b32 s4, v0
+; GFX6-NEXT: v_trunc_f32_e32 v0, s1
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, s1, v0
+; GFX6-NEXT: v_mul_f32_e64 v0, s1, 0.5
+; GFX6-NEXT: v_trunc_f32_e32 v1, v0
+; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v1, v0
+; GFX6-NEXT: s_cselect_b32 s5, 1, 0
+; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GFX6-NEXT: s_cselect_b32 s1, 1, 0
+; GFX6-NEXT: s_and_b32 s1, s5, s1
+; GFX6-NEXT: s_cmp_lg_u32 s1, 0
+; GFX6-NEXT: s_cselect_b32 s1, s0, 1.0
+; GFX6-NEXT: s_and_b32 s2, s4, 0x7fffffff
+; GFX6-NEXT: s_and_b32 s1, s1, 0x80000000
+; GFX6-NEXT: s_or_b32 s2, s2, s1
+; GFX6-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
+; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
+; GFX6-NEXT: s_cselect_b32 s0, 1, 0
+; GFX6-NEXT: s_xor_b32 s1, s5, 1
+; GFX6-NEXT: s_and_b32 s0, s0, s1
+; GFX6-NEXT: s_cmp_lg_u32 s0, 0
+; GFX6-NEXT: s_cselect_b32 s0, 0x7fc00000, s2
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: v_pow_f32_sgpr_sgpr:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[2:3], |s0|, v0
+; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8-NEXT: s_cselect_b32 s3, 1, 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_lshl_b32 s3, s3, 5
; GFX8-NEXT: v_mov_b32_e32 v0, s3
-; GFX8-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX8-NEXT: v_ldexp_f32 v0, |s0|, v0
; GFX8-NEXT: v_log_f32_e32 v0, v0
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
-; GFX8-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX8-NEXT: s_cselect_b32 s2, 0x42000000, 0
; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX8-NEXT: v_subrev_f32_e32 v0, s0, v0
+; GFX8-NEXT: v_subrev_f32_e32 v0, s2, v0
; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX8-NEXT: s_cselect_b32 s0, 0x42800000, 0
-; GFX8-NEXT: v_add_f32_e32 v0, s0, v0
+; GFX8-NEXT: s_cselect_b32 s2, 0x42800000, 0
+; GFX8-NEXT: v_add_f32_e32 v0, s2, v0
; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
-; GFX8-NEXT: v_ldexp_f32 v0, v0, s0
+; GFX8-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; GFX8-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX8-NEXT: v_readfirstlane_b32 s2, v0
+; GFX8-NEXT: v_trunc_f32_e32 v0, s1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, s1, v0
+; GFX8-NEXT: v_mul_f32_e64 v0, s1, 0.5
+; GFX8-NEXT: v_trunc_f32_e32 v1, v0
+; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v1, v0
+; GFX8-NEXT: s_cselect_b32 s3, 1, 0
+; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX8-NEXT: s_cselect_b32 s1, 1, 0
+; GFX8-NEXT: s_and_b32 s1, s3, s1
+; GFX8-NEXT: s_cmp_lg_u32 s1, 0
+; GFX8-NEXT: s_cselect_b32 s1, s0, 1.0
+; GFX8-NEXT: s_bitset0_b32 s2, 31
+; GFX8-NEXT: s_and_b32 s1, s1, 0x80000000
+; GFX8-NEXT: s_or_b32 s2, s2, s1
+; GFX8-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
+; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX8-NEXT: s_cselect_b32 s0, 1, 0
+; GFX8-NEXT: s_xor_b32 s1, s3, 1
+; GFX8-NEXT: s_and_b32 s0, s0, s1
+; GFX8-NEXT: s_cmp_lg_u32 s0, 0
+; GFX8-NEXT: s_cselect_b32 s0, 0x7fc00000, s2
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: v_pow_f32_sgpr_sgpr:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[2:3], |s0|, v0
+; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9-NEXT: s_cselect_b32 s3, 1, 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_lshl_b32 s3, s3, 5
; GFX9-NEXT: v_mov_b32_e32 v0, s3
-; GFX9-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX9-NEXT: v_ldexp_f32 v0, |s0|, v0
; GFX9-NEXT: v_log_f32_e32 v0, v0
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
-; GFX9-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX9-NEXT: s_cselect_b32 s2, 0x42000000, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX9-NEXT: v_subrev_f32_e32 v0, s0, v0
+; GFX9-NEXT: v_subrev_f32_e32 v0, s2, v0
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_cselect_b32 s0, 0x42800000, 0
-; GFX9-NEXT: v_add_f32_e32 v0, s0, v0
+; GFX9-NEXT: s_cselect_b32 s2, 0x42800000, 0
+; GFX9-NEXT: v_add_f32_e32 v0, s2, v0
; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
-; GFX9-NEXT: v_ldexp_f32 v0, v0, s0
+; GFX9-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; GFX9-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX9-NEXT: v_readfirstlane_b32 s2, v0
+; GFX9-NEXT: v_trunc_f32_e32 v0, s1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, s1, v0
+; GFX9-NEXT: v_mul_f32_e64 v0, s1, 0.5
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v1, v0
+; GFX9-NEXT: s_cselect_b32 s3, 1, 0
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-NEXT: s_and_b32 s1, s3, s1
+; GFX9-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-NEXT: s_cselect_b32 s1, s0, 1.0
+; GFX9-NEXT: s_bitset0_b32 s2, 31
+; GFX9-NEXT: s_and_b32 s1, s1, 0x80000000
+; GFX9-NEXT: s_or_b32 s2, s2, s1
+; GFX9-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, 1, 0
+; GFX9-NEXT: s_xor_b32 s1, s3, 1
+; GFX9-NEXT: s_and_b32 s0, s0, s1
+; GFX9-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-NEXT: s_cselect_b32 s0, 0x7fc00000, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: v_pow_f32_sgpr_sgpr:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0|
+; GFX10-NEXT: v_mul_f32_e64 v1, s1, 0.5
+; GFX10-NEXT: v_trunc_f32_e32 v2, s1
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
+; GFX10-NEXT: v_trunc_f32_e32 v3, v1
; GFX10-NEXT: s_cselect_b32 s3, 1, 0
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
; GFX10-NEXT: s_lshl_b32 s3, s3, 5
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
-; GFX10-NEXT: v_ldexp_f32 v0, s0, s3
-; GFX10-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX10-NEXT: v_ldexp_f32 v0, |s0|, s3
+; GFX10-NEXT: s_cselect_b32 s2, 0x42000000, 0
; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_subrev_f32_e32 v0, s0, v0
+; GFX10-NEXT: v_subrev_f32_e32 v0, s2, v0
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0
-; GFX10-NEXT: s_cselect_b32 s0, 0x42800000, 0
-; GFX10-NEXT: v_add_f32_e32 v0, s0, v0
-; GFX10-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, s1, v2
+; GFX10-NEXT: s_cselect_b32 s2, 0x42800000, 0
+; GFX10-NEXT: v_cmp_lg_f32_e64 s1, v3, v1
+; GFX10-NEXT: v_add_f32_e32 v0, s2, v0
+; GFX10-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0
+; GFX10-NEXT: s_cselect_b32 s3, 1, 0
; GFX10-NEXT: v_exp_f32_e32 v0, v0
-; GFX10-NEXT: v_ldexp_f32 v0, v0, s0
+; GFX10-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10-NEXT: s_and_b32 s1, s3, s1
+; GFX10-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10-NEXT: s_cselect_b32 s1, s0, 1.0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX10-NEXT: v_cmp_class_f32_e64 s0, s0, 24
+; GFX10-NEXT: s_and_b32 s1, s1, 0x80000000
+; GFX10-NEXT: v_readfirstlane_b32 s2, v0
+; GFX10-NEXT: s_bitset0_b32 s2, 31
+; GFX10-NEXT: s_or_b32 s2, s2, s1
+; GFX10-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-NEXT: s_cselect_b32 s0, 1, 0
+; GFX10-NEXT: s_xor_b32 s1, s3, 1
+; GFX10-NEXT: s_and_b32 s0, s0, s1
+; GFX10-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-NEXT: s_cselect_b32 s0, 0x7fc00000, s2
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_pow_f32_sgpr_sgpr:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0|
+; GFX11-NEXT: v_mul_f32_e64 v1, s1, 0.5
+; GFX11-NEXT: v_trunc_f32_e32 v2, s1
; GFX11-NEXT: s_cmp_lg_u32 s2, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_trunc_f32_e32 v3, v1
; GFX11-NEXT: s_cselect_b32 s3, 1, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-NEXT: s_lshl_b32 s3, s3, 5
; GFX11-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-NEXT: v_ldexp_f32 v0, s0, s3
-; GFX11-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX11-NEXT: v_ldexp_f32 v0, |s0|, s3
+; GFX11-NEXT: s_cselect_b32 s2, 0x42000000, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_subrev_f32_e32 v0, s0, v0
+; GFX11-NEXT: v_subrev_f32_e32 v0, s2, v0
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX11-NEXT: s_cmp_lg_u32 vcc_lo, 0
-; GFX11-NEXT: s_cselect_b32 s0, 0x42800000, 0
-; GFX11-NEXT: v_add_f32_e32 v0, s0, v0
-; GFX11-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, s1, v2
+; GFX11-NEXT: s_cselect_b32 s2, 0x42800000, 0
+; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v3, v1
+; GFX11-NEXT: v_add_f32_e32 v0, s2, v0
+; GFX11-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; GFX11-NEXT: s_cmp_lg_u32 vcc_lo, 0
+; GFX11-NEXT: s_cselect_b32 s3, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_cmp_lg_u32 s1, 0
+; GFX11-NEXT: s_cselect_b32 s1, 1, 0
+; GFX11-NEXT: s_and_b32 s1, s3, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cmp_lg_u32 s1, 0
+; GFX11-NEXT: s_cselect_b32 s1, s0, 1.0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, s0
+; GFX11-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, s0, 24
+; GFX11-NEXT: s_and_b32 s1, s1, 0x80000000
+; GFX11-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-NEXT: s_bitset0_b32 s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s2, s2, s1
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-NEXT: s_cselect_b32 s0, 1, 0
+; GFX11-NEXT: s_xor_b32 s1, s3, 1
+; GFX11-NEXT: s_and_b32 s0, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-NEXT: s_cselect_b32 s0, 0x7fc00000, s2
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow
@@ -1752,116 +3982,189 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v2
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX6-NEXT: v_ldexp_f32_e64 v0, -v0, v2
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_not_b32_e32 v1, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, -v0, s[4:5]
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], -v0, 24
+; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fneg_lhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v2
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX8-NEXT: v_ldexp_f32 v0, -v0, v2
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_not_b32_e32 v1, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, -v0, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], -v0, 24
+; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fneg_lhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v2
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX9-NEXT: v_ldexp_f32 v0, -v0, v2
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_not_b32_e32 v1, 63
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, -v0, s[4:5]
+; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], -v0, 24
+; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fneg_lhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, -v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e32 v5, v1
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX10-NEXT: v_ldexp_f32 v0, -v0, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX10-NEXT: v_log_f32_e32 v2, v2
+; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX10-NEXT: v_trunc_f32_e32 v6, v3
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v6, v3
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: s_and_b32 s5, s4, s5
+; GFX10-NEXT: s_xor_b32 s4, s4, exec_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 1.0, -v0, s5
+; GFX10-NEXT: v_cmp_class_f32_e64 s5, -v0, 24
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX10-NEXT: s_and_b32 s4, s5, s4
+; GFX10-NEXT: v_exp_f32_e32 v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fneg_lhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: v_trunc_f32_e32 v5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_ldexp_f32 v0, -v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_and_b32 s1, s0, s1
+; GFX11-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 1.0, -v0, s1
+; GFX11-NEXT: v_cmp_class_f32_e64 s1, -v0, 24
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX11-NEXT: s_and_b32 s0, s1, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.x = fneg float %x
%pow = call float @llvm.pow.f32(float %neg.x, float %y)
@@ -1873,122 +4176,889 @@ define float @v_pow_f32_fneg_rhs(float %x, float %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1
-; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_not_b32_e32 v1, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_mul_legacy_f32_e64 v2, -v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_trunc_f32_e64 v3, -v1
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, -v1
+; GFX6-NEXT: v_mul_f32_e64 v1, -v1, 0.5
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: s_xor_b64 s[4:5], s[6:7], exec
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fneg_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1
-; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_not_b32_e32 v1, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_mul_legacy_f32_e64 v2, -v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_trunc_f32_e64 v3, -v1
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, -v1
+; GFX8-NEXT: v_mul_f32_e64 v1, -v1, 0.5
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: s_xor_b64 s[4:5], s[6:7], exec
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fneg_rhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_not_b32_e32 v1, 63
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_mul_legacy_f32_e64 v2, -v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX9-NEXT: v_trunc_f32_e64 v3, -v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, -v1
+; GFX9-NEXT: v_mul_f32_e64 v1, -v1, 0.5
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
+; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fneg_rhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e64 v5, -v1
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v5, -v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX10-NEXT: s_xor_b32 s5, s6, exec_lo
+; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX10-NEXT: v_log_f32_e32 v2, v2
+; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e64 v3, -v1, 0.5
+; GFX10-NEXT: v_mul_legacy_f32_e64 v2, -v1, v2
+; GFX10-NEXT: v_trunc_f32_e32 v6, v3
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v6, v3
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX10-NEXT: v_exp_f32_e32 v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: s_and_b32 vcc_lo, s6, s4
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX10-NEXT: s_and_b32 s4, s4, s5
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fneg_rhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: v_trunc_f32_e64 v5, -v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-NEXT: v_cmp_eq_f32_e64 s2, v5, -v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: s_xor_b32 s1, s2, exec_lo
+; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, -v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_f32_e64 v3, -v1, 0.5
+; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v2, -v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v6, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_and_b32 vcc_lo, s2, s0
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX11-NEXT: s_and_b32 s0, s0, s1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.y = fneg float %y
%pow = call float @llvm.pow.f32(float %x, float %neg.y)
ret float %pow
}
+define float @v_pow_f32_afn(float %x, float %y) {
+; GFX6-LABEL: v_pow_f32_afn:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f32_afn:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f32_afn:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f32_afn:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_pow_f32_afn:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %pow = call afn float @llvm.pow.f32(float %x, float %y)
+ ret float %pow
+}
+
+define half @v_pow_f16_afn(half %x, half %y) {
+; GFX6-LABEL: v_pow_f16_afn:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f16_afn:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f16_afn:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f16_afn:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_pow_f16_afn:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_pow_f16_afn:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+ %pow = call afn half @llvm.pow.f16(half %x, half %y)
+ ret half %pow
+}
+
+define float @v_pow_f32_const_even_int(float %x) {
+; GFX6-LABEL: v_pow_f32_const_even_int:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v1
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f32_const_even_int:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f32_const_even_int:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX9-NEXT: v_bfrev_b32_e32 v1, -2
+; GFX9-NEXT: v_and_or_b32 v0, v0, v1, 0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f32_const_even_int:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s4
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v0, 0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_pow_f32_const_even_int:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
+; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, 2.0, v0
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v0, 0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %pow = call float @llvm.pow.f32(float %x, float 2.0)
+ ret float %pow
+}
+
+define float @v_pow_f32_const_odd_int(float %x) {
+; GFX6-LABEL: v_pow_f32_const_odd_int:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX6-NEXT: v_ldexp_f32_e64 v1, |v0|, v1
+; GFX6-NEXT: v_log_f32_e32 v1, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v1, 0x40400000, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX6-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_exp_f32_e32 v1, v1
+; GFX6-NEXT: v_not_b32_e32 v2, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f32_const_odd_int:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX8-NEXT: v_ldexp_f32 v1, |v0|, v1
+; GFX8-NEXT: v_log_f32_e32 v1, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v1, 0x40400000, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX8-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX8-NEXT: v_exp_f32_e32 v1, v1
+; GFX8-NEXT: v_not_b32_e32 v2, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f32_const_odd_int:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX9-NEXT: v_ldexp_f32 v1, |v0|, v1
+; GFX9-NEXT: v_log_f32_e32 v1, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v1, 0x40400000, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX9-NEXT: v_exp_f32_e32 v1, v1
+; GFX9-NEXT: v_not_b32_e32 v2, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX9-NEXT: v_bfrev_b32_e32 v2, -2
+; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f32_const_odd_int:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX10-NEXT: v_ldexp_f32 v1, |v0|, v1
+; GFX10-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX10-NEXT: v_log_f32_e32 v1, v1
+; GFX10-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_mul_legacy_f32_e32 v1, 0x40400000, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_exp_f32_e32 v1, v1
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_pow_f32_const_odd_int:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f32 v1, |v0|, v1
+; GFX11-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX11-NEXT: v_log_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, 0x40400000, v1
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %pow = call float @llvm.pow.f32(float %x, float 3.0)
+ ret float %pow
+}
+
+define float @v_pow_f32_const_non_int(float %x) {
+; GFX6-LABEL: v_pow_f32_const_non_int:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX6-NEXT: v_ldexp_f32_e64 v1, |v0|, v1
+; GFX6-NEXT: v_log_f32_e32 v1, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v1, 0.5, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX6-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_exp_f32_e32 v1, v1
+; GFX6-NEXT: v_not_b32_e32 v2, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_cmp_class_f32_e64 vcc, v0, 24
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f32_const_non_int:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX8-NEXT: v_ldexp_f32 v1, |v0|, v1
+; GFX8-NEXT: v_log_f32_e32 v1, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX8-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX8-NEXT: v_exp_f32_e32 v1, v1
+; GFX8-NEXT: v_not_b32_e32 v2, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v0, 24
+; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f32_const_non_int:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX9-NEXT: v_ldexp_f32 v1, |v0|, v1
+; GFX9-NEXT: v_log_f32_e32 v1, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX9-NEXT: v_exp_f32_e32 v1, v1
+; GFX9-NEXT: v_not_b32_e32 v2, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, 24
+; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX9-NEXT: v_bfrev_b32_e32 v2, -2
+; GFX9-NEXT: v_and_or_b32 v1, v1, v2, 0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f32_const_non_int:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX10-NEXT: v_ldexp_f32 v1, |v0|, v1
+; GFX10-NEXT: v_log_f32_e32 v1, v1
+; GFX10-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_mul_legacy_f32_e32 v1, 0.5, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_exp_f32_e32 v1, v1
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v1, 0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, 0x7fc00000, s4
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_pow_f32_const_non_int:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_ldexp_f32 v1, |v0|, v1
+; GFX11-NEXT: v_log_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, 0.5, v1
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v1, 0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, 0x7fc00000, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %pow = call float @llvm.pow.f32(float %x, float 5.000000e-01)
+ ret float %pow
+}
+
+define float @v_pow_f32_nnan(float %x, float %y) {
+; GFX6-LABEL: v_pow_f32_nnan:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f32_nnan:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f32_nnan:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX9-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; GFX9-NEXT: v_bfrev_b32_e32 v1, -2
+; GFX9-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX9-NEXT: v_and_or_b32 v0, v2, v1, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f32_nnan:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e32 v5, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX10-NEXT: v_log_f32_e32 v2, v2
+; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX10-NEXT: v_trunc_f32_e32 v6, v3
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v6, v3
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX10-NEXT: v_exp_f32_e32 v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, s5
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_pow_f32_nnan:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: v_trunc_f32_e32 v5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v2, v2
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_and_b32 vcc_lo, s0, s1
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
+; GFX11-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %pow = call nnan float @llvm.pow.f32(float %x, float %y)
+ ret float %pow
+}
+
declare half @llvm.pow.f16(half, half)
declare float @llvm.pow.f32(float, float)
declare double @llvm.pow.f64(double, double)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
index fa3d8377a5bd8..c33f1211a030c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
@@ -15,18 +15,19 @@ body: |
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[COPY]]
; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[SELECT]]
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FABS]], [[SELECT]]
; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[COPY1]](f32)
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[COPY1]](f32), [[FSUB]](f32)
; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
@@ -36,25 +37,48 @@ body: |
; GFX6-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
- ; GFX6-NEXT: $vgpr0 = COPY [[FMUL1]](f32)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[COPY1]]
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[COPY1]]
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[COPY1]], [[C8]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[COPY]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[COPY]](f32), 24
+ ; GFX6-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
+ ; GFX6-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX6-NEXT: $vgpr0 = COPY [[SELECT5]](f32)
;
; GFX9-LABEL: name: test_fpow_f32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[COPY]]
; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[SELECT]]
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FABS]], [[SELECT]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[COPY1]](f32)
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[COPY1]](f32), [[FSUB]](f32)
; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
@@ -64,7 +88,29 @@ body: |
; GFX9-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMUL1]](f32)
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[COPY1]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[COPY1]]
+ ; GFX9-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[COPY1]], [[C8]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[COPY]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[COPY]](f32), 24
+ ; GFX9-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
+ ; GFX9-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[SELECT5]](f32)
%0:_(f32) = COPY $vgpr0
%1:_(f32) = COPY $vgpr1
%2:_(f32) = G_FPOW %0, %1
@@ -84,18 +130,19 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
; GFX6-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[UV]]
; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[SELECT]]
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FABS]], [[SELECT]]
; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[UV2]](f32)
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[UV2]](f32), [[FSUB]](f32)
; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
@@ -105,20 +152,60 @@ body: |
; GFX6-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
- ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
- ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[SELECT4]]
- ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
- ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
- ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[INT3]], [[SELECT5]]
- ; GFX6-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](f32), [[UV3]](f32)
- ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT4]](f32), [[C5]]
- ; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C6]], [[C4]]
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INT4]], [[SELECT6]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV2]]
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[UV2]]
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[C8]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[UV]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV]](f32), 24
+ ; GFX6-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
+ ; GFX6-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[UV1]]
+ ; GFX6-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C]]
+ ; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[FABS1]], [[SELECT6]]
+ ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL3]](f32)
+ ; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C3]], [[C4]]
+ ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[INT3]], [[SELECT7]]
+ ; GFX6-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[UV3]](f32), [[FSUB1]](f32)
+ ; GFX6-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT4]](f32), [[C5]]
+ ; GFX6-NEXT: [[SELECT8:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C6]], [[C4]]
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INT4]], [[SELECT8]]
; GFX6-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
- ; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C7]], [[C2]]
- ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[INT5]], [[SELECT7]]
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMUL1]](f32), [[FMUL3]](f32)
+ ; GFX6-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C7]], [[C2]]
+ ; GFX6-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[INT5]], [[SELECT9]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV3]]
+ ; GFX6-NEXT: [[FCMP6:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC2]](f32), [[UV3]]
+ ; GFX6-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[UV3]], [[C8]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
+ ; GFX6-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
+ ; GFX6-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[UV1]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
+ ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT10]](f32)
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
+ ; GFX6-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[BITCAST4]], [[C9]]
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND5]], [[AND6]]
+ ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX6-NEXT: [[IS_FPCLASS1:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV1]](f32), 24
+ ; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[FCMP6]], [[C11]]
+ ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS1]], [[XOR1]]
+ ; GFX6-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C12]], [[BITCAST5]]
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[SELECT5]](f32), [[SELECT11]](f32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; GFX9-LABEL: name: test_fpow_v2f32
@@ -128,18 +215,19 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
; GFX9-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[UV]]
; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[SELECT]]
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FABS]], [[SELECT]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[UV2]](f32)
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[UV2]](f32), [[FSUB]](f32)
; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
@@ -149,20 +237,60 @@ body: |
; GFX9-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
- ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
- ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
- ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[SELECT4]]
- ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
- ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
- ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[INT3]], [[SELECT5]]
- ; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](f32), [[UV3]](f32)
- ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT4]](f32), [[C5]]
- ; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C6]], [[C4]]
- ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INT4]], [[SELECT6]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV2]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[UV2]]
+ ; GFX9-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[C8]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[UV]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV]](f32), 24
+ ; GFX9-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
+ ; GFX9-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[UV1]]
+ ; GFX9-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C]]
+ ; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[FABS1]], [[SELECT6]]
+ ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL3]](f32)
+ ; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C3]], [[C4]]
+ ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[INT3]], [[SELECT7]]
+ ; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[UV3]](f32), [[FSUB1]](f32)
+ ; GFX9-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT4]](f32), [[C5]]
+ ; GFX9-NEXT: [[SELECT8:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C6]], [[C4]]
+ ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INT4]], [[SELECT8]]
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
- ; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C7]], [[C2]]
- ; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[INT5]], [[SELECT7]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMUL1]](f32), [[FMUL3]](f32)
+ ; GFX9-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C7]], [[C2]]
+ ; GFX9-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[INT5]], [[SELECT9]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV3]]
+ ; GFX9-NEXT: [[FCMP6:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC2]](f32), [[UV3]]
+ ; GFX9-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[UV3]], [[C8]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
+ ; GFX9-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
+ ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
+ ; GFX9-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[UV1]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT10]](f32)
+ ; GFX9-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
+ ; GFX9-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[BITCAST4]], [[C9]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND5]], [[AND6]]
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX9-NEXT: [[IS_FPCLASS1:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV1]](f32), 24
+ ; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[FCMP6]], [[C11]]
+ ; GFX9-NEXT: [[AND7:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS1]], [[XOR1]]
+ ; GFX9-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C12]], [[BITCAST5]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[SELECT5]](f32), [[SELECT11]](f32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
%0:_(<2 x f32>) = COPY $vgpr0_vgpr1
%1:_(<2 x f32>) = COPY $vgpr2_vgpr3
@@ -183,18 +311,19 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
; GFX6-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[UV]]
; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[SELECT]]
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FABS]], [[SELECT]]
; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[UV3]](f32)
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[UV3]](f32), [[FSUB]](f32)
; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
@@ -204,33 +333,91 @@ body: |
; GFX6-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
- ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
- ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[SELECT4]]
- ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
- ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
- ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[INT3]], [[SELECT5]]
- ; GFX6-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](f32), [[UV4]](f32)
- ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT4]](f32), [[C5]]
- ; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C6]], [[C4]]
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INT4]], [[SELECT6]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV3]]
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[UV3]]
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV3]], [[C8]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[UV]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV]](f32), 24
+ ; GFX6-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
+ ; GFX6-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[UV1]]
+ ; GFX6-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C]]
+ ; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[FABS1]], [[SELECT6]]
+ ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL3]](f32)
+ ; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C3]], [[C4]]
+ ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[INT3]], [[SELECT7]]
+ ; GFX6-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[UV4]](f32), [[FSUB1]](f32)
+ ; GFX6-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT4]](f32), [[C5]]
+ ; GFX6-NEXT: [[SELECT8:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C6]], [[C4]]
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INT4]], [[SELECT8]]
; GFX6-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
- ; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C7]], [[C2]]
- ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[INT5]], [[SELECT7]]
- ; GFX6-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](f32), [[C]]
- ; GFX6-NEXT: [[SELECT8:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C1]], [[C2]]
- ; GFX6-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[SELECT8]]
- ; GFX6-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL4]](f32)
- ; GFX6-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C3]], [[C4]]
- ; GFX6-NEXT: [[FSUB2:%[0-9]+]]:_(f32) = G_FSUB [[INT6]], [[SELECT9]]
- ; GFX6-NEXT: [[INT7:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB2]](f32), [[UV5]](f32)
- ; GFX6-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT7]](f32), [[C5]]
- ; GFX6-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C6]], [[C4]]
- ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[INT7]], [[SELECT10]]
+ ; GFX6-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C7]], [[C2]]
+ ; GFX6-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[INT5]], [[SELECT9]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV4]]
+ ; GFX6-NEXT: [[FCMP6:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC2]](f32), [[UV4]]
+ ; GFX6-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[UV4]], [[C8]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
+ ; GFX6-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
+ ; GFX6-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[UV1]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
+ ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT10]](f32)
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
+ ; GFX6-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[BITCAST4]], [[C9]]
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND5]], [[AND6]]
+ ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX6-NEXT: [[IS_FPCLASS1:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV1]](f32), 24
+ ; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[FCMP6]], [[C11]]
+ ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS1]], [[XOR1]]
+ ; GFX6-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C12]], [[BITCAST5]]
+ ; GFX6-NEXT: [[FABS2:%[0-9]+]]:_(f32) = G_FABS [[UV2]]
+ ; GFX6-NEXT: [[FCMP8:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](f32), [[C]]
+ ; GFX6-NEXT: [[SELECT12:%[0-9]+]]:_(f32) = G_SELECT [[FCMP8]](s1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[FMUL6:%[0-9]+]]:_(f32) = G_FMUL [[FABS2]], [[SELECT12]]
+ ; GFX6-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL6]](f32)
+ ; GFX6-NEXT: [[SELECT13:%[0-9]+]]:_(f32) = G_SELECT [[FCMP8]](s1), [[C3]], [[C4]]
+ ; GFX6-NEXT: [[FSUB2:%[0-9]+]]:_(f32) = G_FSUB [[INT6]], [[SELECT13]]
+ ; GFX6-NEXT: [[INT7:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[UV5]](f32), [[FSUB2]](f32)
+ ; GFX6-NEXT: [[FCMP9:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT7]](f32), [[C5]]
+ ; GFX6-NEXT: [[SELECT14:%[0-9]+]]:_(f32) = G_SELECT [[FCMP9]](s1), [[C6]], [[C4]]
+ ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[INT7]], [[SELECT14]]
; GFX6-NEXT: [[INT8:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
- ; GFX6-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C7]], [[C2]]
- ; GFX6-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[INT8]], [[SELECT11]]
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FMUL1]](f32), [[FMUL3]](f32), [[FMUL5]](f32)
+ ; GFX6-NEXT: [[SELECT15:%[0-9]+]]:_(f32) = G_SELECT [[FCMP9]](s1), [[C7]], [[C2]]
+ ; GFX6-NEXT: [[FMUL7:%[0-9]+]]:_(f32) = G_FMUL [[INT8]], [[SELECT15]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC4:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV5]]
+ ; GFX6-NEXT: [[FCMP10:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC4]](f32), [[UV5]]
+ ; GFX6-NEXT: [[FMUL8:%[0-9]+]]:_(f32) = G_FMUL [[UV5]], [[C8]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC5:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL8]]
+ ; GFX6-NEXT: [[FCMP11:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC5]](f32), [[FMUL8]]
+ ; GFX6-NEXT: [[AND8:%[0-9]+]]:_(s1) = G_AND [[FCMP10]], [[FCMP11]]
+ ; GFX6-NEXT: [[SELECT16:%[0-9]+]]:_(f32) = G_SELECT [[AND8]](s1), [[UV2]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL7]](f32)
+ ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT16]](f32)
+ ; GFX6-NEXT: [[AND9:%[0-9]+]]:_(i32) = G_AND [[BITCAST6]], [[C10]]
+ ; GFX6-NEXT: [[AND10:%[0-9]+]]:_(i32) = G_AND [[BITCAST7]], [[C9]]
+ ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(i32) = disjoint G_OR [[AND9]], [[AND10]]
+ ; GFX6-NEXT: [[BITCAST8:%[0-9]+]]:_(f32) = G_BITCAST [[OR2]](i32)
+ ; GFX6-NEXT: [[IS_FPCLASS2:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV2]](f32), 24
+ ; GFX6-NEXT: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[FCMP10]], [[C11]]
+ ; GFX6-NEXT: [[AND11:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS2]], [[XOR2]]
+ ; GFX6-NEXT: [[SELECT17:%[0-9]+]]:_(f32) = G_SELECT [[AND11]](s1), [[C12]], [[BITCAST8]]
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[SELECT5]](f32), [[SELECT11]](f32), [[SELECT17]](f32)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
; GFX9-LABEL: name: test_fpow_v3f32
@@ -240,18 +427,19 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
; GFX9-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[UV]]
; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[SELECT]]
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FABS]], [[SELECT]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[UV3]](f32)
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[UV3]](f32), [[FSUB]](f32)
; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
@@ -261,33 +449,91 @@ body: |
; GFX9-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
- ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
- ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
- ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[SELECT4]]
- ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
- ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
- ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[INT3]], [[SELECT5]]
- ; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](f32), [[UV4]](f32)
- ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT4]](f32), [[C5]]
- ; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C6]], [[C4]]
- ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INT4]], [[SELECT6]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV3]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[UV3]]
+ ; GFX9-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV3]], [[C8]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[UV]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV]](f32), 24
+ ; GFX9-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
+ ; GFX9-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[UV1]]
+ ; GFX9-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C]]
+ ; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[FABS1]], [[SELECT6]]
+ ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL3]](f32)
+ ; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C3]], [[C4]]
+ ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[INT3]], [[SELECT7]]
+ ; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[UV4]](f32), [[FSUB1]](f32)
+ ; GFX9-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT4]](f32), [[C5]]
+ ; GFX9-NEXT: [[SELECT8:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C6]], [[C4]]
+ ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INT4]], [[SELECT8]]
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
- ; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C7]], [[C2]]
- ; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[INT5]], [[SELECT7]]
- ; GFX9-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](f32), [[C]]
- ; GFX9-NEXT: [[SELECT8:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C1]], [[C2]]
- ; GFX9-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[SELECT8]]
- ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL4]](f32)
- ; GFX9-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C3]], [[C4]]
- ; GFX9-NEXT: [[FSUB2:%[0-9]+]]:_(f32) = G_FSUB [[INT6]], [[SELECT9]]
- ; GFX9-NEXT: [[INT7:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB2]](f32), [[UV5]](f32)
- ; GFX9-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT7]](f32), [[C5]]
- ; GFX9-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C6]], [[C4]]
- ; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[INT7]], [[SELECT10]]
+ ; GFX9-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C7]], [[C2]]
+ ; GFX9-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[INT5]], [[SELECT9]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV4]]
+ ; GFX9-NEXT: [[FCMP6:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC2]](f32), [[UV4]]
+ ; GFX9-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[UV4]], [[C8]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
+ ; GFX9-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
+ ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
+ ; GFX9-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[UV1]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT10]](f32)
+ ; GFX9-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
+ ; GFX9-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[BITCAST4]], [[C9]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND5]], [[AND6]]
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX9-NEXT: [[IS_FPCLASS1:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV1]](f32), 24
+ ; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[FCMP6]], [[C11]]
+ ; GFX9-NEXT: [[AND7:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS1]], [[XOR1]]
+ ; GFX9-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C12]], [[BITCAST5]]
+ ; GFX9-NEXT: [[FABS2:%[0-9]+]]:_(f32) = G_FABS [[UV2]]
+ ; GFX9-NEXT: [[FCMP8:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](f32), [[C]]
+ ; GFX9-NEXT: [[SELECT12:%[0-9]+]]:_(f32) = G_SELECT [[FCMP8]](s1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[FMUL6:%[0-9]+]]:_(f32) = G_FMUL [[FABS2]], [[SELECT12]]
+ ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL6]](f32)
+ ; GFX9-NEXT: [[SELECT13:%[0-9]+]]:_(f32) = G_SELECT [[FCMP8]](s1), [[C3]], [[C4]]
+ ; GFX9-NEXT: [[FSUB2:%[0-9]+]]:_(f32) = G_FSUB [[INT6]], [[SELECT13]]
+ ; GFX9-NEXT: [[INT7:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[UV5]](f32), [[FSUB2]](f32)
+ ; GFX9-NEXT: [[FCMP9:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT7]](f32), [[C5]]
+ ; GFX9-NEXT: [[SELECT14:%[0-9]+]]:_(f32) = G_SELECT [[FCMP9]](s1), [[C6]], [[C4]]
+ ; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[INT7]], [[SELECT14]]
; GFX9-NEXT: [[INT8:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
- ; GFX9-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C7]], [[C2]]
- ; GFX9-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[INT8]], [[SELECT11]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FMUL1]](f32), [[FMUL3]](f32), [[FMUL5]](f32)
+ ; GFX9-NEXT: [[SELECT15:%[0-9]+]]:_(f32) = G_SELECT [[FCMP9]](s1), [[C7]], [[C2]]
+ ; GFX9-NEXT: [[FMUL7:%[0-9]+]]:_(f32) = G_FMUL [[INT8]], [[SELECT15]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC4:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV5]]
+ ; GFX9-NEXT: [[FCMP10:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC4]](f32), [[UV5]]
+ ; GFX9-NEXT: [[FMUL8:%[0-9]+]]:_(f32) = G_FMUL [[UV5]], [[C8]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC5:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL8]]
+ ; GFX9-NEXT: [[FCMP11:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC5]](f32), [[FMUL8]]
+ ; GFX9-NEXT: [[AND8:%[0-9]+]]:_(s1) = G_AND [[FCMP10]], [[FCMP11]]
+ ; GFX9-NEXT: [[SELECT16:%[0-9]+]]:_(f32) = G_SELECT [[AND8]](s1), [[UV2]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL7]](f32)
+ ; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT16]](f32)
+ ; GFX9-NEXT: [[AND9:%[0-9]+]]:_(i32) = G_AND [[BITCAST6]], [[C10]]
+ ; GFX9-NEXT: [[AND10:%[0-9]+]]:_(i32) = G_AND [[BITCAST7]], [[C9]]
+ ; GFX9-NEXT: [[OR2:%[0-9]+]]:_(i32) = disjoint G_OR [[AND9]], [[AND10]]
+ ; GFX9-NEXT: [[BITCAST8:%[0-9]+]]:_(f32) = G_BITCAST [[OR2]](i32)
+ ; GFX9-NEXT: [[IS_FPCLASS2:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV2]](f32), 24
+ ; GFX9-NEXT: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[FCMP10]], [[C11]]
+ ; GFX9-NEXT: [[AND11:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS2]], [[XOR2]]
+ ; GFX9-NEXT: [[SELECT17:%[0-9]+]]:_(f32) = G_SELECT [[AND11]](s1), [[C12]], [[BITCAST8]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[SELECT5]](f32), [[SELECT11]](f32), [[SELECT17]](f32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
%0:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
@@ -306,18 +552,19 @@ body: |
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f32) = nnan nsz G_FABS [[COPY]]
; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[COPY]], [[SELECT]]
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[FABS]], [[SELECT]]
; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan nsz G_FSUB [[INT]], [[SELECT1]]
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[COPY1]](f32)
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[COPY1]](f32), [[FSUB]](f32)
; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan nsz G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
@@ -327,25 +574,42 @@ body: |
; GFX6-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[INT2]], [[SELECT3]]
- ; GFX6-NEXT: $vgpr0 = COPY [[FMUL1]](f32)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[COPY1]]
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[COPY1]]
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[COPY1]], [[C8]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[COPY]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
;
; GFX9-LABEL: name: test_fpow_f32_flags
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f32) = nnan nsz G_FABS [[COPY]]
; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[COPY]], [[SELECT]]
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[FABS]], [[SELECT]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan nsz G_FSUB [[INT]], [[SELECT1]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[COPY1]](f32)
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[COPY1]](f32), [[FSUB]](f32)
; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan nsz G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
@@ -355,7 +619,23 @@ body: |
; GFX9-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[INT2]], [[SELECT3]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMUL1]](f32)
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[COPY1]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[COPY1]]
+ ; GFX9-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[COPY1]], [[C8]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[COPY]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
%0:_(f32) = COPY $vgpr0
%1:_(f32) = COPY $vgpr1
%2:_(f32) = nnan nsz G_FPOW %0, %1
@@ -377,20 +657,51 @@ body: |
; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
- ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](f32)
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT]](f32), [[FPEXT1]](f32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[FPEXT]]
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INT1]], [[SELECT]]
- ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FABS]], [[SELECT]]
+ ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT1]](f32), [[FSUB]](f32)
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
+ ; GFX6-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INT1]], [[SELECT2]]
+ ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT1]]
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[FPEXT1]]
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C8]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[FPEXT]](f32), 24
+ ; GFX6-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
+ ; GFX6-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[SELECT5]](f32)
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
@@ -401,13 +712,54 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
- ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(f16) = G_FLOG2 [[TRUNC]]
- ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[FLOG2_]](f16)
+ ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT]](f32), [[FPEXT1]](f32)
- ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT]](f32)
- ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(f16) = G_FEXP2 [[FPTRUNC]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FEXP2_]](f16)
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[FPEXT]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FABS]], [[SELECT]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT1]](f32), [[FSUB]](f32)
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
+ ; GFX9-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INT1]], [[SELECT2]]
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT1]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[FPEXT1]]
+ ; GFX9-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C8]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[FPEXT]](f32), 24
+ ; GFX9-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
+ ; GFX9-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[SELECT5]](f32)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
%0:_(i32) = COPY $vgpr0
%1:_(i32) = COPY $vgpr1
@@ -440,37 +792,91 @@ body: |
; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
- ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](f32)
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT]](f32), [[FPEXT1]](f32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C1]]
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[FPEXT]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C1]]
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INT1]], [[SELECT]]
- ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
- ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FABS]], [[SELECT]]
+ ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C4]], [[C5]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT1]](f32), [[FSUB]](f32)
+ ; GFX6-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C6]]
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C5]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INT1]], [[SELECT2]]
+ ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C8]], [[C3]]
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT1]]
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[FPEXT1]]
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C9]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C3]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX6-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST2]], [[C11]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[FPEXT]](f32), 24
+ ; GFX6-NEXT: [[C12:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C12]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
+ ; GFX6-NEXT: [[C13:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C13]], [[BITCAST4]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[SELECT5]](f32)
; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
- ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT2]](f32)
- ; GFX6-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT3]](f32), [[FPEXT3]](f32)
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT4]](f32), [[C1]]
- ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C2]], [[C3]]
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INT4]], [[SELECT2]]
+ ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[FPEXT2]]
+ ; GFX6-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C1]]
+ ; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[FABS1]], [[SELECT6]]
+ ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL3]](f32)
+ ; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C4]], [[C5]]
+ ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[INT3]], [[SELECT7]]
+ ; GFX6-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT3]](f32), [[FSUB1]](f32)
+ ; GFX6-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT4]](f32), [[C6]]
+ ; GFX6-NEXT: [[SELECT8:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C7]], [[C5]]
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INT4]], [[SELECT8]]
; GFX6-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
- ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C4]], [[C5]]
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT5]], [[SELECT3]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL1]](f32)
+ ; GFX6-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C8]], [[C3]]
+ ; GFX6-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[INT5]], [[SELECT9]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT3]]
+ ; GFX6-NEXT: [[FCMP6:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC2]](f32), [[FPEXT3]]
+ ; GFX6-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT3]], [[C9]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
+ ; GFX6-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
+ ; GFX6-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[FPEXT2]], [[C3]]
+ ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
+ ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT10]](f32)
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST5]], [[C11]]
+ ; GFX6-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[BITCAST6]], [[C10]]
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND5]], [[AND6]]
+ ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX6-NEXT: [[IS_FPCLASS1:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[FPEXT2]](f32), 24
+ ; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[FCMP6]], [[C12]]
+ ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS1]], [[XOR1]]
+ ; GFX6-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C13]], [[BITCAST7]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[SELECT11]](f32)
; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x f16>)
+ ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
+ ; GFX6-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR2]](i32)
+ ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST8]](<2 x f16>)
;
; GFX9-LABEL: name: test_fpow_v2f16
; GFX9: liveins: $vgpr0, $vgpr1
@@ -486,19 +892,88 @@ body: |
; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
- ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(f16) = G_FLOG2 [[TRUNC]]
- ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[FLOG2_]](f16)
+ ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT]](f32), [[FPEXT1]](f32)
- ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT]](f32)
- ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(f16) = G_FEXP2 [[FPTRUNC]]
- ; GFX9-NEXT: [[FLOG2_1:%[0-9]+]]:_(f16) = G_FLOG2 [[TRUNC1]]
- ; GFX9-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[FLOG2_1]](f16)
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[FPEXT]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C1]]
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FABS]], [[SELECT]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C4]], [[C5]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT1]](f32), [[FSUB]](f32)
+ ; GFX9-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C6]]
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C5]]
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INT1]], [[SELECT2]]
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C8]], [[C3]]
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT1]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[FPEXT1]]
+ ; GFX9-NEXT: [[C9:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C9]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C3]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX9-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST2]], [[C11]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[FPEXT]](f32), 24
+ ; GFX9-NEXT: [[C12:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C12]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
+ ; GFX9-NEXT: [[C13:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C13]], [[BITCAST4]]
+ ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[SELECT5]](f32)
+ ; GFX9-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
; GFX9-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT2]](f32), [[FPEXT3]](f32)
- ; GFX9-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT1]](f32)
- ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(f16) = G_FEXP2 [[FPTRUNC1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FEXP2_]](f16), [[FEXP2_1]](f16)
+ ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[FPEXT2]]
+ ; GFX9-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C1]]
+ ; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[FABS1]], [[SELECT6]]
+ ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL3]](f32)
+ ; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C4]], [[C5]]
+ ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[INT3]], [[SELECT7]]
+ ; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT3]](f32), [[FSUB1]](f32)
+ ; GFX9-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT4]](f32), [[C6]]
+ ; GFX9-NEXT: [[SELECT8:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C7]], [[C5]]
+ ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INT4]], [[SELECT8]]
+ ; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
+ ; GFX9-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C8]], [[C3]]
+ ; GFX9-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[INT5]], [[SELECT9]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT3]]
+ ; GFX9-NEXT: [[FCMP6:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC2]](f32), [[FPEXT3]]
+ ; GFX9-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT3]], [[C9]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
+ ; GFX9-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
+ ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
+ ; GFX9-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[FPEXT2]], [[C3]]
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT10]](f32)
+ ; GFX9-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST5]], [[C11]]
+ ; GFX9-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[BITCAST6]], [[C10]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND5]], [[AND6]]
+ ; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX9-NEXT: [[IS_FPCLASS1:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[FPEXT2]](f32), 24
+ ; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[FCMP6]], [[C12]]
+ ; GFX9-NEXT: [[AND7:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS1]], [[XOR1]]
+ ; GFX9-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C13]], [[BITCAST7]]
+ ; GFX9-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[SELECT11]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FPTRUNC]](f16), [[FPTRUNC1]](f16)
; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
%0:_(<2 x f16>) = COPY $vgpr0
%1:_(<2 x f16>) = COPY $vgpr1
@@ -528,37 +1003,81 @@ body: |
; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[TRUNC]](f16)
; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[TRUNC2]](f16)
- ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](f32)
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT]](f32), [[FPEXT1]](f32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = nnan nsz G_FCMP floatpred(olt), [[INT1]](f32), [[C1]]
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f32) = nnan nsz G_FABS [[FPEXT]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C1]]
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan nsz G_FADD [[INT1]], [[SELECT]]
- ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
- ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[FABS]], [[SELECT]]
+ ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP]](s1), [[C4]], [[C5]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[INT2]], [[SELECT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan nsz G_FSUB [[INT]], [[SELECT1]]
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT1]](f32), [[FSUB]](f32)
+ ; GFX6-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan nsz G_FCMP floatpred(olt), [[INT1]](f32), [[C6]]
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP1]](s1), [[C7]], [[C5]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan nsz G_FADD [[INT1]], [[SELECT2]]
+ ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP1]](s1), [[C8]], [[C3]]
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT1]]
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[FPEXT1]]
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C9]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C3]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX6-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST2]], [[C11]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[BITCAST4]](f32)
; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[TRUNC1]](f16)
; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[TRUNC3]](f16)
- ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT2]](f32)
- ; GFX6-NEXT: [[INT4:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT3]](f32), [[FPEXT3]](f32)
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan nsz G_FCMP floatpred(olt), [[INT4]](f32), [[C1]]
- ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP1]](s1), [[C2]], [[C3]]
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = nnan nsz G_FADD [[INT4]], [[SELECT2]]
+ ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(f32) = nnan nsz G_FABS [[FPEXT2]]
+ ; GFX6-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C1]]
+ ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP4]](s1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[FABS1]], [[SELECT5]]
+ ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL3]](f32)
+ ; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP4]](s1), [[C4]], [[C5]]
+ ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = nnan nsz G_FSUB [[INT3]], [[SELECT6]]
+ ; GFX6-NEXT: [[INT4:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT3]](f32), [[FSUB1]](f32)
+ ; GFX6-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = nnan nsz G_FCMP floatpred(olt), [[INT4]](f32), [[C6]]
+ ; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP5]](s1), [[C7]], [[C5]]
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = nnan nsz G_FADD [[INT4]], [[SELECT7]]
; GFX6-NEXT: [[INT5:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
- ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP1]](s1), [[C4]], [[C5]]
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[INT5]], [[SELECT3]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[FMUL1]](f32)
+ ; GFX6-NEXT: [[SELECT8:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP5]](s1), [[C8]], [[C3]]
+ ; GFX6-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[INT5]], [[SELECT8]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT3]]
+ ; GFX6-NEXT: [[FCMP6:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC2]](f32), [[FPEXT3]]
+ ; GFX6-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT3]], [[C9]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
+ ; GFX6-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
+ ; GFX6-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[FPEXT2]], [[C3]]
+ ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
+ ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT9]](f32)
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[BITCAST5]], [[C11]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST6]], [[C10]]
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND4]], [[AND5]]
+ ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[BITCAST7]](f32)
; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x f16>)
+ ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
+ ; GFX6-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR2]](i32)
+ ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST8]](<2 x f16>)
;
; GFX9-LABEL: name: test_fpow_v2f16_flags
; GFX9: liveins: $vgpr0, $vgpr1
@@ -574,19 +1093,78 @@ body: |
; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
- ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(f16) = nnan nsz G_FLOG2 [[TRUNC]]
- ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[FLOG2_]](f16)
+ ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[TRUNC]](f16)
; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[TRUNC2]](f16)
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT]](f32), [[FPEXT1]](f32)
- ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[INT]](f32)
- ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(f16) = nnan nsz G_FEXP2 [[FPTRUNC]]
- ; GFX9-NEXT: [[FLOG2_1:%[0-9]+]]:_(f16) = nnan nsz G_FLOG2 [[TRUNC1]]
- ; GFX9-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[FLOG2_1]](f16)
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f32) = nnan nsz G_FABS [[FPEXT]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C1]]
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[FABS]], [[SELECT]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP]](s1), [[C4]], [[C5]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan nsz G_FSUB [[INT]], [[SELECT1]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT1]](f32), [[FSUB]](f32)
+ ; GFX9-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan nsz G_FCMP floatpred(olt), [[INT1]](f32), [[C6]]
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP1]](s1), [[C7]], [[C5]]
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan nsz G_FADD [[INT1]], [[SELECT2]]
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP1]](s1), [[C8]], [[C3]]
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT1]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[FPEXT1]]
+ ; GFX9-NEXT: [[C9:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C9]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C3]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX9-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST2]], [[C11]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[BITCAST4]](f32)
+ ; GFX9-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[TRUNC1]](f16)
; GFX9-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[TRUNC3]](f16)
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT2]](f32), [[FPEXT3]](f32)
- ; GFX9-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[INT1]](f32)
- ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(f16) = nnan nsz G_FEXP2 [[FPTRUNC1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FEXP2_]](f16), [[FEXP2_1]](f16)
+ ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(f32) = nnan nsz G_FABS [[FPEXT2]]
+ ; GFX9-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C1]]
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP4]](s1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[FABS1]], [[SELECT5]]
+ ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL3]](f32)
+ ; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP4]](s1), [[C4]], [[C5]]
+ ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = nnan nsz G_FSUB [[INT3]], [[SELECT6]]
+ ; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT3]](f32), [[FSUB1]](f32)
+ ; GFX9-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = nnan nsz G_FCMP floatpred(olt), [[INT4]](f32), [[C6]]
+ ; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP5]](s1), [[C7]], [[C5]]
+ ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f32) = nnan nsz G_FADD [[INT4]], [[SELECT7]]
+ ; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
+ ; GFX9-NEXT: [[SELECT8:%[0-9]+]]:_(f32) = nnan nsz G_SELECT [[FCMP5]](s1), [[C8]], [[C3]]
+ ; GFX9-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = nnan nsz G_FMUL [[INT5]], [[SELECT8]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT3]]
+ ; GFX9-NEXT: [[FCMP6:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC2]](f32), [[FPEXT3]]
+ ; GFX9-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT3]], [[C9]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
+ ; GFX9-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
+ ; GFX9-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[FPEXT2]], [[C3]]
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT9]](f32)
+ ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[BITCAST5]], [[C11]]
+ ; GFX9-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST6]], [[C10]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND4]], [[AND5]]
+ ; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX9-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[BITCAST7]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FPTRUNC]](f16), [[FPTRUNC1]](f16)
; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
%0:_(<2 x f16>) = COPY $vgpr0
%1:_(<2 x f16>) = COPY $vgpr1
@@ -609,20 +1187,45 @@ body: |
; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = nnan ninf G_FPEXT [[TRUNC]](f16)
; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = nnan ninf G_FPEXT [[TRUNC1]](f16)
- ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](f32)
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT]](f32), [[FPEXT1]](f32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = nnan ninf G_FCMP floatpred(olt), [[INT1]](f32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f32) = nnan ninf G_FABS [[FPEXT]]
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan ninf G_FADD [[INT1]], [[SELECT]]
- ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan ninf G_FMUL [[FABS]], [[SELECT]]
+ ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan ninf G_FMUL [[INT2]], [[SELECT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan ninf G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan ninf G_FSUB [[INT]], [[SELECT1]]
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT1]](f32), [[FSUB]](f32)
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan ninf G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
+ ; GFX6-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan ninf G_FADD [[INT1]], [[SELECT2]]
+ ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan ninf G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT1]]
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[FPEXT1]]
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C8]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan ninf G_FPTRUNC [[BITCAST2]](f32)
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
@@ -633,13 +1236,48 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
- ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(f16) = nnan ninf G_FLOG2 [[TRUNC]]
- ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = nnan ninf G_FPEXT [[FLOG2_]](f16)
+ ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = nnan ninf G_FPEXT [[TRUNC]](f16)
; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = nnan ninf G_FPEXT [[TRUNC1]](f16)
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT]](f32), [[FPEXT1]](f32)
- ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[INT]](f32)
- ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(f16) = nnan G_FEXP2 [[FPTRUNC]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FEXP2_]](f16)
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f32) = nnan ninf G_FABS [[FPEXT]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan ninf G_FMUL [[FABS]], [[SELECT]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan ninf G_FSUB [[INT]], [[SELECT1]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT1]](f32), [[FSUB]](f32)
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan ninf G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
+ ; GFX9-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan ninf G_FADD [[INT1]], [[SELECT2]]
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan ninf G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT1]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[FPEXT1]]
+ ; GFX9-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C8]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan ninf G_FPTRUNC [[BITCAST2]](f32)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
%0:_(i32) = COPY $vgpr0
%1:_(i32) = COPY $vgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
index a7da86f5c4e28..51bbf22b94ce9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
@@ -18,20 +18,45 @@ body: |
; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC]](f16)
; GFX6-NEXT: [[SITOFP:%[0-9]+]]:_(f32) = G_SITOFP [[COPY1]](i32)
- ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](f32)
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT]](f32), [[SITOFP]](f32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[INT1]](f32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f32) = nnan G_FABS [[FPEXT]]
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[INT1]], [[SELECT]]
- ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[FABS]], [[SELECT]]
+ ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[INT2]], [[SELECT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan G_FSUB [[INT]], [[SELECT1]]
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[SITOFP]](f32), [[FSUB]](f32)
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
+ ; GFX6-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[INT1]], [[SELECT2]]
+ ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[SITOFP]]
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[SITOFP]]
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[SITOFP]], [[C8]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[BITCAST2]](f32)
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
@@ -41,15 +66,48 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC]](f16)
; GFX9-NEXT: [[SITOFP:%[0-9]+]]:_(f32) = G_SITOFP [[COPY1]](i32)
- ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[SITOFP]](f32)
- ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(f16) = nnan G_FLOG2 [[TRUNC]]
- ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = nnan G_FPEXT [[FLOG2_]](f16)
- ; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = nnan G_FPEXT [[FPTRUNC]](f16)
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT]](f32), [[FPEXT1]](f32)
- ; GFX9-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[INT]](f32)
- ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(f16) = nnan G_FEXP2 [[FPTRUNC1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FEXP2_]](f16)
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f32) = nnan G_FABS [[FPEXT]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[FABS]], [[SELECT]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan G_FSUB [[INT]], [[SELECT1]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[SITOFP]](f32), [[FSUB]](f32)
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
+ ; GFX9-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[INT1]], [[SELECT2]]
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[SITOFP]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[SITOFP]]
+ ; GFX9-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[SITOFP]], [[C8]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[BITCAST2]](f32)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
%0:_(i32) = COPY $vgpr0
%1:_(i32) = COPY $vgpr1
@@ -71,18 +129,19 @@ body: |
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
; GFX6-NEXT: [[SITOFP:%[0-9]+]]:_(f32) = G_SITOFP [[COPY1]](i32)
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f32) = nnan G_FABS [[COPY]]
; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[SELECT]]
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[FABS]], [[SELECT]]
; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan G_FSUB [[INT]], [[SELECT1]]
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[SITOFP]](f32)
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[SITOFP]](f32), [[FSUB]](f32)
; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
@@ -92,7 +151,23 @@ body: |
; GFX6-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan G_FMUL [[INT2]], [[SELECT3]]
- ; GFX6-NEXT: $vgpr0 = COPY [[FMUL1]](f32)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[SITOFP]]
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[SITOFP]]
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[SITOFP]], [[C8]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[COPY]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
;
; GFX9-LABEL: name: test_fpowi_f32_i32_flags
; GFX9: liveins: $vgpr0, $vgpr1
@@ -100,18 +175,19 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
; GFX9-NEXT: [[SITOFP:%[0-9]+]]:_(f32) = G_SITOFP [[COPY1]](i32)
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f32) = nnan G_FABS [[COPY]]
; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[SELECT]]
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[FABS]], [[SELECT]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan G_FSUB [[INT]], [[SELECT1]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[SITOFP]](f32)
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[SITOFP]](f32), [[FSUB]](f32)
; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
@@ -121,7 +197,23 @@ body: |
; GFX9-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan G_FMUL [[INT2]], [[SELECT3]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMUL1]](f32)
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[SITOFP]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[SITOFP]]
+ ; GFX9-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[SITOFP]], [[C8]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
+ ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[COPY]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
%0:_(f32) = COPY $vgpr0
%1:_(i32) = COPY $vgpr1
%2:_(f32) = nnan G_FPOWI %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
index 6ac395372ddae..757c261488ed1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
@@ -9,64 +9,174 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX7-NEXT: v_mov_b32_e32 v2, 0x800000
; GFX7-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX7-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
-; GFX7-NEXT: v_mov_b32_e32 v3, 0x42800000
-; GFX7-NEXT: v_log_f32_e32 v0, v0
-; GFX7-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX7-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
-; GFX7-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX7-NEXT: v_exp_f32_e32 v0, v0
-; GFX7-NEXT: v_not_b32_e32 v1, 63
-; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX7-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX7-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX7-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX7-NEXT: v_log_f32_e32 v2, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX7-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX7-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX7-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX7-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX7-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX7-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX7-NEXT: v_exp_f32_e32 v2, v2
+; GFX7-NEXT: v_not_b32_e32 v3, 63
+; GFX7-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX7-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX7-NEXT: v_trunc_f32_e32 v3, v1
+; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX7-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX7-NEXT: v_trunc_f32_e32 v3, v1
+; GFX7-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX7-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX7-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX7-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX7-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX7-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX7-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX7-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX7-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_powi_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX8-NEXT: v_log_f16_e32 v0, v0
-; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_exp_f16_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_powi_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, s1
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT: v_exp_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_powi_f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_log_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v2, v2
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, s1
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_exp_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%l.cast = bitcast i16 %l to half
%res = call half @llvm.powi.f16.i32(half %l.cast, i32 %r)
@@ -79,76 +189,122 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX7-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX7-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; GFX7-NEXT: v_log_f32_e32 v0, v0
+; GFX7-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX7-NEXT: v_log_f32_e32 v2, v2
; GFX7-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX7-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX7-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX7-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX7-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX7-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX7-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX7-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX7-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX7-NEXT: v_exp_f32_e32 v0, v0
-; GFX7-NEXT: v_not_b32_e32 v1, 63
-; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX7-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX7-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX7-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX7-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX7-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX7-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX7-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX7-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX7-NEXT: v_exp_f32_e32 v2, v2
+; GFX7-NEXT: v_not_b32_e32 v3, 63
+; GFX7-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX7-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX7-NEXT: v_trunc_f32_e32 v3, v1
+; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX7-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX7-NEXT: v_trunc_f32_e32 v3, v1
+; GFX7-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX7-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX7-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX7-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX7-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX7-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX7-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX7-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX7-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_powi_f32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_not_b32_e32 v1, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-NEXT: v_trunc_f32_e32 v5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX11-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_and_b32 vcc_lo, s0, s1
+; GFX11-NEXT: v_cmp_class_f32_e64 s1, v0, 24
+; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX11-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_and_b32 s0, s1, s0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 %r)
ret float %res
diff --git a/llvm/test/CodeGen/AMDGPU/fpow.ll b/llvm/test/CodeGen/AMDGPU/fpow.ll
index b12bd73c8287a..21d5cbd612572 100644
--- a/llvm/test/CodeGen/AMDGPU/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/fpow.ll
@@ -11,51 +11,217 @@ define float @v_pow_f32(float %x, float %y) {
; GFX6-LABEL: v_pow_f32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: s_mov_b32 s4, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v3, |v0|, v3
+; GFX6-NEXT: v_log_f32_e32 v3, v3
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v4, v3
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX6-NEXT: s_brev_b32 s4, -2
+; GFX6-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: s_mov_b32 s4, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX8-NEXT: v_log_f32_e32 v3, v3
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v4, v3
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX8-NEXT: s_brev_b32 s4, -2
+; GFX8-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s4, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX9-NEXT: v_log_f32_e32 v3, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX9-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v4, v3
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX9-NEXT: s_brev_b32 s4, -2
+; GFX9-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_f32:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_log_f32_e32 v0, v0
-; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
-; GFX90A-NEXT: v_exp_f32_e32 v0, v0
+; GFX90A-NEXT: s_mov_b32 s4, 0x800000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX90A-NEXT: v_log_f32_e32 v3, v3
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX90A-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX90A-NEXT: v_mul_legacy_f32 v2, v1, v2
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX90A-NEXT: v_exp_f32_e32 v2, v2
+; GFX90A-NEXT: v_not_b32_e32 v3, 63
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX90A-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX90A-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v3
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX90A-NEXT: v_trunc_f32_e32 v3, v1
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX90A-NEXT: s_brev_b32 s4, -2
+; GFX90A-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e32 v4, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v4, v1
+; GFX10-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX10-NEXT: v_log_f32_e32 v3, v3
+; GFX10-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX10-NEXT: v_exp_f32_e32 v2, v2
+; GFX10-NEXT: v_trunc_f32_e32 v5, v3
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v4, v1
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
+; GFX10-NEXT: s_and_b32 s4, s4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: v_trunc_f32_e32 v4, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v4, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX11-NEXT: v_log_f32_e32 v3, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v5, v3
+; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX11-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX11-NEXT: v_cmp_neq_f32_e32 vcc_lo, v4, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
+; GFX11-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow
@@ -65,68 +231,366 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX6-LABEL: v_pow_v2f32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_log_f32_e32 v1, v1
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v2, v0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v3, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_exp_f32_e32 v1, v1
+; GFX6-NEXT: s_mov_b32 s6, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s6
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v6, |v0|, v6
+; GFX6-NEXT: v_log_f32_e32 v6, v6
+; GFX6-NEXT: v_mov_b32_e32 v4, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
+; GFX6-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v5, v6, v5
+; GFX6-NEXT: v_mul_legacy_f32_e32 v5, v2, v5
+; GFX6-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s8, v5
+; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX6-NEXT: v_add_f32_e32 v5, v5, v7
+; GFX6-NEXT: v_exp_f32_e32 v5, v5
+; GFX6-NEXT: v_not_b32_e32 v7, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX6-NEXT: s_brev_b32 s9, -2
+; GFX6-NEXT: v_ldexp_f32_e32 v5, v5, v8
+; GFX6-NEXT: v_mul_f32_e32 v8, 0.5, v2
+; GFX6-NEXT: v_trunc_f32_e32 v9, v8
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v9, v8
+; GFX6-NEXT: v_trunc_f32_e32 v8, v2
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v8, v2
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v9, 1.0, v0, vcc
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s6
+; GFX6-NEXT: v_bfi_b32 v5, s9, v5, v9
+; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v9, |v1|, v9
+; GFX6-NEXT: v_log_f32_e32 v9, v9
+; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v0, 24
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v8, v2
+; GFX6-NEXT: v_sub_f32_e32 v0, v9, v4
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v3, v0
+; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v0
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[4:5]
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX6-NEXT: v_exp_f32_e32 v4, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v5
+; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v3
+; GFX6-NEXT: v_trunc_f32_e32 v6, v5
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX6-NEXT: v_trunc_f32_e32 v5, v3
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v3
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v5, v3
+; GFX6-NEXT: v_bfi_b32 v4, s9, v4, v6
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_v2f32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_log_f32_e32 v1, v1
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v2, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v3, v1
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_exp_f32_e32 v1, v1
+; GFX8-NEXT: s_mov_b32 s6, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s6
+; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v6, |v0|, v6
+; GFX8-NEXT: v_log_f32_e32 v6, v6
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
+; GFX8-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v5, v6, v5
+; GFX8-NEXT: v_mul_legacy_f32_e32 v5, v2, v5
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s8, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX8-NEXT: v_add_f32_e32 v5, v5, v7
+; GFX8-NEXT: v_exp_f32_e32 v5, v5
+; GFX8-NEXT: v_not_b32_e32 v7, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX8-NEXT: s_brev_b32 s9, -2
+; GFX8-NEXT: v_ldexp_f32 v5, v5, v8
+; GFX8-NEXT: v_mul_f32_e32 v8, 0.5, v2
+; GFX8-NEXT: v_trunc_f32_e32 v9, v8
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v9, v8
+; GFX8-NEXT: v_trunc_f32_e32 v8, v2
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v8, v2
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v9, 1.0, v0, vcc
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s6
+; GFX8-NEXT: v_bfi_b32 v5, s9, v5, v9
+; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v9, |v1|, v9
+; GFX8-NEXT: v_log_f32_e32 v9, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v0, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v8, v2
+; GFX8-NEXT: v_sub_f32_e32 v0, v9, v4
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v3, v0
+; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v0
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[4:5]
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX8-NEXT: v_exp_f32_e32 v4, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v3
+; GFX8-NEXT: v_trunc_f32_e32 v6, v5
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX8-NEXT: v_trunc_f32_e32 v5, v3
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v3
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v5, v3
+; GFX8-NEXT: v_bfi_b32 v4, s9, v4, v6
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_v2f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_log_f32_e32 v1, v1
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v2, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v3, v1
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_exp_f32_e32 v1, v1
+; GFX9-NEXT: s_mov_b32 s6, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s6
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v6, |v0|, v6
+; GFX9-NEXT: v_log_f32_e32 v6, v6
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
+; GFX9-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v5, v6, v5
+; GFX9-NEXT: v_mul_legacy_f32_e32 v5, v2, v5
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s8, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX9-NEXT: v_add_f32_e32 v5, v5, v7
+; GFX9-NEXT: v_exp_f32_e32 v5, v5
+; GFX9-NEXT: v_not_b32_e32 v7, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX9-NEXT: s_brev_b32 s9, -2
+; GFX9-NEXT: v_ldexp_f32 v5, v5, v8
+; GFX9-NEXT: v_mul_f32_e32 v8, 0.5, v2
+; GFX9-NEXT: v_trunc_f32_e32 v9, v8
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v9, v8
+; GFX9-NEXT: v_trunc_f32_e32 v8, v2
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v8, v2
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v9, 1.0, v0, vcc
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s6
+; GFX9-NEXT: v_bfi_b32 v5, s9, v5, v9
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v9, |v1|, v9
+; GFX9-NEXT: v_log_f32_e32 v9, v9
+; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v0, 24
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v8, v2
+; GFX9-NEXT: v_sub_f32_e32 v0, v9, v4
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v3, v0
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[4:5]
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX9-NEXT: v_exp_f32_e32 v4, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v3
+; GFX9-NEXT: v_trunc_f32_e32 v6, v5
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v3
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v3
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v5, v3
+; GFX9-NEXT: v_bfi_b32 v4, s9, v4, v6
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_v2f32:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_log_f32_e32 v0, v0
-; GFX90A-NEXT: v_log_f32_e32 v1, v1
-; GFX90A-NEXT: v_mul_legacy_f32 v0, v2, v0
-; GFX90A-NEXT: v_mul_legacy_f32 v1, v3, v1
-; GFX90A-NEXT: v_exp_f32_e32 v0, v0
-; GFX90A-NEXT: v_exp_f32_e32 v1, v1
+; GFX90A-NEXT: s_mov_b32 s6, 0x800000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s6
+; GFX90A-NEXT: v_cndmask_b32_e64 v6, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v6, |v0|, v6
+; GFX90A-NEXT: v_log_f32_e32 v6, v6
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
+; GFX90A-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX90A-NEXT: v_sub_f32_e32 v5, v6, v5
+; GFX90A-NEXT: v_mul_legacy_f32 v5, v2, v5
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s8, v5
+; GFX90A-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX90A-NEXT: v_add_f32_e32 v5, v5, v7
+; GFX90A-NEXT: v_exp_f32_e32 v5, v5
+; GFX90A-NEXT: v_not_b32_e32 v7, 63
+; GFX90A-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX90A-NEXT: s_brev_b32 s9, -2
+; GFX90A-NEXT: v_ldexp_f32 v5, v5, v8
+; GFX90A-NEXT: v_mul_f32_e32 v8, 0.5, v2
+; GFX90A-NEXT: v_trunc_f32_e32 v9, v8
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v9, v8
+; GFX90A-NEXT: v_trunc_f32_e32 v8, v2
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v8, v2
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v9, 1.0, v0, vcc
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s6
+; GFX90A-NEXT: v_bfi_b32 v5, s9, v5, v9
+; GFX90A-NEXT: v_cndmask_b32_e64 v9, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v9, |v1|, v9
+; GFX90A-NEXT: v_log_f32_e32 v9, v9
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v0, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v8, v2
+; GFX90A-NEXT: v_sub_f32_e32 v0, v9, v4
+; GFX90A-NEXT: v_mul_legacy_f32 v0, v3, v0
+; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v0
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[4:5]
+; GFX90A-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX90A-NEXT: v_exp_f32_e32 v4, v0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
+; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX90A-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX90A-NEXT: v_mul_f32_e32 v5, 0.5, v3
+; GFX90A-NEXT: v_trunc_f32_e32 v6, v5
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX90A-NEXT: v_trunc_f32_e32 v5, v3
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v3
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v5, v3
+; GFX90A-NEXT: v_bfi_b32 v4, s9, v4, v6
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_log_f32_e32 v1, v1
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v2, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v3, v1
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
-; GFX10-NEXT: v_exp_f32_e32 v1, v1
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v1|
+; GFX10-NEXT: v_mul_f32_e32 v10, 0.5, v3
+; GFX10-NEXT: v_cmp_class_f32_e64 s8, v0, 24
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 32, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s5
+; GFX10-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX10-NEXT: v_ldexp_f32 v7, |v1|, v7
+; GFX10-NEXT: v_log_f32_e32 v5, v5
+; GFX10-NEXT: v_log_f32_e32 v7, v7
+; GFX10-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_sub_f32_e32 v5, v7, v6
+; GFX10-NEXT: v_mul_f32_e32 v6, 0.5, v2
+; GFX10-NEXT: v_trunc_f32_e32 v7, v2
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v2, v4
+; GFX10-NEXT: v_mul_legacy_f32_e32 v5, v3, v5
+; GFX10-NEXT: v_trunc_f32_e32 v11, v6
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v7, v2
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v5
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v11, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v8
+; GFX10-NEXT: v_add_f32_e32 v5, v5, v9
+; GFX10-NEXT: v_trunc_f32_e32 v8, v3
+; GFX10-NEXT: v_trunc_f32_e32 v9, v10
+; GFX10-NEXT: v_exp_f32_e32 v4, v4
+; GFX10-NEXT: v_exp_f32_e32 v5, v5
+; GFX10-NEXT: v_cmp_eq_f32_e64 s7, v8, v3
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v9, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0xffffffc0, s4
+; GFX10-NEXT: s_and_b32 s4, s5, s6
+; GFX10-NEXT: v_cmp_class_f32_e64 s5, v1, 24
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 1.0, v0, s4
+; GFX10-NEXT: s_and_b32 vcc_lo, s7, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f32_e64 s4, v8, v3
+; GFX10-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc_lo
+; GFX10-NEXT: v_ldexp_f32 v5, v5, v9
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v7, v2
+; GFX10-NEXT: s_and_b32 s4, s5, s4
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
+; GFX10-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v6
+; GFX10-NEXT: s_and_b32 s6, s8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_v2f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: v_log_f32_e32 v1, v1
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v1|
+; GFX11-NEXT: v_mul_f32_e32 v10, 0.5, v3
+; GFX11-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 32, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX11-NEXT: v_ldexp_f32 v7, |v1|, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v5, v5
+; GFX11-NEXT: v_log_f32_e32 v7, v7
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_dual_mul_dx9_zero_f32 v0, v2, v0 :: v_dual_mul_dx9_zero_f32 v1, v3, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-NEXT: v_dual_sub_f32 v4, v5, v4 :: v_dual_sub_f32 v5, v7, v6
+; GFX11-NEXT: v_trunc_f32_e32 v7, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mul_dx9_zero_f32 v4, v2, v4 :: v_dual_mul_dx9_zero_f32 v5, v3, v5
+; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v7, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v5
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s0
+; GFX11-NEXT: v_mul_f32_e32 v6, 0.5, v2
+; GFX11-NEXT: v_dual_add_f32 v4, v4, v8 :: v_dual_add_f32 v5, v5, v9
+; GFX11-NEXT: v_trunc_f32_e32 v8, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_trunc_f32_e32 v11, v6
+; GFX11-NEXT: v_trunc_f32_e32 v9, v10
+; GFX11-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-NEXT: v_exp_f32_e32 v5, v5
+; GFX11-NEXT: v_cmp_eq_f32_e64 s3, v8, v3
+; GFX11-NEXT: v_cmp_lg_f32_e64 s2, v11, v6
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v9, v10
+; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, 0xffffffc0, s0
+; GFX11-NEXT: s_and_b32 s0, s1, s2
+; GFX11-NEXT: v_cmp_class_f32_e64 s1, v1, 24
+; GFX11-NEXT: s_and_b32 vcc_lo, s3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 1.0, v0, s0
+; GFX11-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc_lo
+; GFX11-NEXT: v_ldexp_f32 v5, v5, v9
+; GFX11-NEXT: v_cmp_neq_f32_e32 vcc_lo, v7, v2
+; GFX11-NEXT: v_cmp_neq_f32_e64 s0, v8, v3
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v6
+; GFX11-NEXT: s_and_b32 s2, s4, vcc_lo
+; GFX11-NEXT: s_and_b32 s0, s1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y)
ret <2 x float> %pow
@@ -137,10 +601,39 @@ define half @v_pow_f16(half %x, half %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX6-NEXT: s_mov_b32 s4, 0x800000
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v3, |v0|, v3
+; GFX6-NEXT: v_log_f32_e32 v3, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v4, v3
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX6-NEXT: s_brev_b32 s4, -2
+; GFX6-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
@@ -148,10 +641,39 @@ define half @v_pow_f16(half %x, half %y) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX8-NEXT: s_mov_b32 s4, 0x800000
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX8-NEXT: v_log_f32_e32 v3, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v4, v3
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX8-NEXT: s_brev_b32 s4, -2
+; GFX8-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -159,10 +681,39 @@ define half @v_pow_f16(half %x, half %y) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s4, 0x800000
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX9-NEXT: v_log_f32_e32 v3, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX9-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v4, v3
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX9-NEXT: s_brev_b32 s4, -2
+; GFX9-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -170,10 +721,40 @@ define half @v_pow_f16(half %x, half %y) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX90A-NEXT: v_log_f32_e32 v0, v0
-; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
-; GFX90A-NEXT: v_exp_f32_e32 v0, v0
+; GFX90A-NEXT: s_mov_b32 s4, 0x800000
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v4, v1
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX90A-NEXT: v_log_f32_e32 v3, v3
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX90A-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX90A-NEXT: v_mul_legacy_f32 v2, v4, v2
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX90A-NEXT: v_exp_f32_e32 v2, v2
+; GFX90A-NEXT: v_not_b32_e32 v3, 63
+; GFX90A-NEXT: s_mov_b32 s4, 0.5
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX90A-NEXT: v_fma_mix_f32 v1, v1, s4, neg(0) op_sel_hi:[1,0,0]
+; GFX90A-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX90A-NEXT: v_trunc_f32_e32 v3, v1
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v1, v4
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v4
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc
+; GFX90A-NEXT: s_brev_b32 s4, -2
+; GFX90A-NEXT: v_bfi_b32 v2, s4, v2, v3
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v4
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -181,24 +762,78 @@ define half @v_pow_f16(half %x, half %y) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v1
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e32 v5, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: s_mov_b32 s4, 0.5
+; GFX10-NEXT: v_fma_mix_f32 v1, v1, s4, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX10-NEXT: v_log_f32_e32 v3, v3
+; GFX10-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v4, v2
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_trunc_f32_e32 v3, v1
+; GFX10-NEXT: v_exp_f32_e32 v2, v2
+; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v3, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX10-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v5, v4
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: s_and_b32 s4, s4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_pow_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 32, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0.5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, |v2|, v0
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, s0, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v4, v3
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v0
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v0, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v4, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v4, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v0
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v3, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v2, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v5, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -206,13 +841,44 @@ define half @v_pow_f16(half %x, half %y) {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0.5
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, s0, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v4, v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v3, v1
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v3, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v0, 24
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v5, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v2
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%pow = call half @llvm.pow.f16(half %x, half %y)
@@ -223,76 +889,281 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX6-LABEL: v_pow_v2f16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX6-NEXT: s_mov_b32 s8, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
+; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e64 v7, |v3|, v7
+; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v2
+; GFX6-NEXT: v_log_f32_e32 v7, v7
+; GFX6-NEXT: v_trunc_f32_e32 v6, v5
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX6-NEXT: v_trunc_f32_e32 v4, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX6-NEXT: s_mov_b32 s9, 0xc2fc0000
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
+; GFX6-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
+; GFX6-NEXT: v_not_b32_e32 v9, 63
+; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
+; GFX6-NEXT: v_add_f32_e32 v6, v6, v8
+; GFX6-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e64 v4, |v0|, v4
+; GFX6-NEXT: v_log_f32_e32 v4, v4
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
+; GFX6-NEXT: v_exp_f32_e32 v6, v6
+; GFX6-NEXT: v_sub_f32_e32 v2, v4, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v4
; GFX6-NEXT: v_exp_f32_e32 v2, v2
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX6-NEXT: v_ldexp_f32_e32 v6, v6, v10
+; GFX6-NEXT: s_brev_b32 s10, -2
+; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
+; GFX6-NEXT: v_bfi_b32 v6, s10, v6, v8
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
+; GFX6-NEXT: v_trunc_f32_e32 v6, v5
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX6-NEXT: v_trunc_f32_e32 v5, v1
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
+; GFX6-NEXT: v_bfi_b32 v2, s10, v2, v6
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_v2f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: s_mov_b32 s8, 0x800000
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
+; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v2
+; GFX8-NEXT: v_log_f32_e32 v7, v7
+; GFX8-NEXT: v_trunc_f32_e32 v6, v5
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
+; GFX8-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX8-NEXT: v_trunc_f32_e32 v4, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX8-NEXT: s_mov_b32 s9, 0xc2fc0000
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
+; GFX8-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
+; GFX8-NEXT: v_not_b32_e32 v9, 63
+; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX8-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
+; GFX8-NEXT: v_add_f32_e32 v6, v6, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX8-NEXT: v_log_f32_e32 v4, v4
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX8-NEXT: v_log_f32_e32 v2, v2
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX8-NEXT: v_exp_f32_e32 v1, v2
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
+; GFX8-NEXT: v_exp_f32_e32 v6, v6
+; GFX8-NEXT: v_sub_f32_e32 v2, v4, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_ldexp_f32 v6, v6, v10
+; GFX8-NEXT: s_brev_b32 s10, -2
+; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
+; GFX8-NEXT: v_bfi_b32 v6, s10, v6, v8
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
+; GFX8-NEXT: v_trunc_f32_e32 v6, v5
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
+; GFX8-NEXT: v_bfi_b32 v2, s10, v2, v6
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; GFX8-NEXT: v_cvt_f16_f32_sdwa v4, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_v2f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: s_mov_b32 s8, 0x800000
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v2
+; GFX9-NEXT: v_log_f32_e32 v7, v7
+; GFX9-NEXT: v_trunc_f32_e32 v6, v5
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
+; GFX9-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX9-NEXT: v_trunc_f32_e32 v4, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX9-NEXT: s_mov_b32 s9, 0xc2fc0000
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
+; GFX9-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
+; GFX9-NEXT: v_not_b32_e32 v9, 63
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX9-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
+; GFX9-NEXT: v_add_f32_e32 v6, v6, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX9-NEXT: v_log_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-NEXT: v_log_f32_e32 v2, v2
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX9-NEXT: v_exp_f32_e32 v1, v2
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
+; GFX9-NEXT: v_exp_f32_e32 v6, v6
+; GFX9-NEXT: v_sub_f32_e32 v2, v4, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_ldexp_f32 v6, v6, v10
+; GFX9-NEXT: s_brev_b32 s10, -2
+; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
+; GFX9-NEXT: v_bfi_b32 v6, s10, v6, v8
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
+; GFX9-NEXT: v_trunc_f32_e32 v6, v5
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
+; GFX9-NEXT: v_bfi_b32 v2, s10, v2, v6
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX9-NEXT: v_pack_b32_f16 v0, v0, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_v2f16:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: s_mov_b32 s8, 0.5
+; GFX90A-NEXT: v_fma_mix_f32 v2, v1, s8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX90A-NEXT: s_mov_b32 s9, 0x800000
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v2
+; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v5|, s9
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v2
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
+; GFX90A-NEXT: v_ldexp_f32 v4, |v5|, v4
+; GFX90A-NEXT: v_log_f32_e32 v4, v4
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX90A-NEXT: v_log_f32_e32 v2, v2
-; GFX90A-NEXT: v_log_f32_e32 v0, v0
-; GFX90A-NEXT: v_mul_legacy_f32 v2, v3, v2
-; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
-; GFX90A-NEXT: v_exp_f32_e32 v1, v2
-; GFX90A-NEXT: v_exp_f32_e32 v0, v0
-; GFX90A-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[4:5]
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX90A-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX90A-NEXT: v_trunc_f32_e32 v2, v3
+; GFX90A-NEXT: v_mul_legacy_f32 v4, v3, v4
+; GFX90A-NEXT: s_mov_b32 s10, 0xc2fc0000
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[6:7], v2, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v4
+; GFX90A-NEXT: v_not_b32_e32 v9, 63
+; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX90A-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s9
+; GFX90A-NEXT: v_add_f32_e32 v4, v4, v8
+; GFX90A-NEXT: v_cndmask_b32_e32 v8, 1.0, v5, vcc
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v2, v3
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, s[4:5]
+; GFX90A-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX90A-NEXT: v_log_f32_e32 v3, v3
+; GFX90A-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v6, v1
+; GFX90A-NEXT: v_exp_f32_e32 v4, v4
+; GFX90A-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX90A-NEXT: s_brev_b32 s11, -2
+; GFX90A-NEXT: v_mul_legacy_f32 v2, v6, v2
+; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v2
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[4:5]
+; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX90A-NEXT: v_exp_f32_e32 v2, v2
+; GFX90A-NEXT: v_ldexp_f32 v4, v4, v10
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v5, 24
+; GFX90A-NEXT: v_bfi_b32 v4, s11, v4, v8
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0x7fc00000
+; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v9, s[4:5]
+; GFX90A-NEXT: v_fma_mix_f32 v1, v1, s8, neg(0) op_sel_hi:[1,0,0]
+; GFX90A-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v1
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v1, v6
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v6
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v6
+; GFX90A-NEXT: v_bfi_b32 v2, s11, v2, v4
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
+; GFX90A-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v3
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f16:
@@ -300,14 +1171,59 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX10-NEXT: v_log_f32_e32 v2, v2
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX10-NEXT: v_exp_f32_e32 v1, v2
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e32 v10, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 32, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s5
+; GFX10-NEXT: s_mov_b32 s4, 0.5
+; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX10-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX10-NEXT: v_fma_mix_f32 v8, v1, s4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v10, v7
+; GFX10-NEXT: v_log_f32_e32 v3, v3
+; GFX10-NEXT: v_log_f32_e32 v5, v5
+; GFX10-NEXT: v_trunc_f32_e32 v9, v8
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v9, v8
+; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v1
+; GFX10-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_fma_mix_f32 v1, v1, s4, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: s_and_b32 s5, s6, s5
+; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v7, v3
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_trunc_f32_e32 v11, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v11, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, v2, s5
+; GFX10-NEXT: v_cmp_class_f32_e64 s5, v2, 24
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, s4
+; GFX10-NEXT: v_exp_f32_e32 v3, v3
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v5
+; GFX10-NEXT: v_trunc_f32_e32 v5, v6
+; GFX10-NEXT: v_exp_f32_e32 v4, v4
+; GFX10-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v6
+; GFX10-NEXT: v_bfi_b32 v1, 0x7fffffff, v3, v1
+; GFX10-NEXT: v_ldexp_f32 v3, v4, v8
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f32_e64 s4, v5, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v10, v7
+; GFX10-NEXT: s_and_b32 s4, s6, s4
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v4
+; GFX10-NEXT: s_and_b32 s5, s5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -318,22 +1234,76 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0.5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v0
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v7
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, s0, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v5
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v1
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s4, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v3, v1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, v5
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -342,24 +1312,77 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v6
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0.5
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v7
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v1
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, s0, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v5
+; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s4, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v4, v5
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y)
@@ -371,76 +1394,281 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX6-NEXT: s_mov_b32 s8, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
+; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e64 v7, |v3|, v7
+; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v2
+; GFX6-NEXT: v_log_f32_e32 v7, v7
+; GFX6-NEXT: v_trunc_f32_e32 v6, v5
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX6-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX6-NEXT: v_trunc_f32_e32 v4, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX6-NEXT: s_mov_b32 s9, 0xc2fc0000
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
+; GFX6-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
+; GFX6-NEXT: v_not_b32_e32 v9, 63
+; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
+; GFX6-NEXT: v_add_f32_e32 v6, v6, v8
+; GFX6-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 32, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
; GFX6-NEXT: v_log_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
+; GFX6-NEXT: v_exp_f32_e32 v6, v6
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v4
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v4
; GFX6-NEXT: v_exp_f32_e32 v2, v2
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX6-NEXT: v_ldexp_f32_e32 v6, v6, v10
+; GFX6-NEXT: s_brev_b32 s10, -2
+; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
+; GFX6-NEXT: v_bfi_b32 v6, s10, v6, v8
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
+; GFX6-NEXT: v_trunc_f32_e32 v6, v5
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX6-NEXT: v_trunc_f32_e32 v5, v1
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: v_bfi_b32 v2, s10, v2, v6
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_v2f16_fneg_lhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: s_mov_b32 s8, 0x800000
; GFX8-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
+; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v2
+; GFX8-NEXT: v_log_f32_e32 v7, v7
+; GFX8-NEXT: v_trunc_f32_e32 v6, v5
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
+; GFX8-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX8-NEXT: v_trunc_f32_e32 v4, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX8-NEXT: s_mov_b32 s9, 0xc2fc0000
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
+; GFX8-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
+; GFX8-NEXT: v_not_b32_e32 v9, 63
+; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX8-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
+; GFX8-NEXT: v_add_f32_e32 v6, v6, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX8-NEXT: v_log_f32_e32 v4, v4
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX8-NEXT: v_log_f32_e32 v2, v2
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX8-NEXT: v_exp_f32_e32 v1, v2
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
+; GFX8-NEXT: v_exp_f32_e32 v6, v6
+; GFX8-NEXT: v_sub_f32_e32 v2, v4, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_ldexp_f32 v6, v6, v10
+; GFX8-NEXT: s_brev_b32 s10, -2
+; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
+; GFX8-NEXT: v_bfi_b32 v6, s10, v6, v8
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
+; GFX8-NEXT: v_trunc_f32_e32 v6, v5
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
+; GFX8-NEXT: v_bfi_b32 v2, s10, v2, v6
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; GFX8-NEXT: v_cvt_f16_f32_sdwa v4, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_v2f16_fneg_lhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: s_mov_b32 s8, 0x800000
; GFX9-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v2
+; GFX9-NEXT: v_log_f32_e32 v7, v7
+; GFX9-NEXT: v_trunc_f32_e32 v6, v5
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
+; GFX9-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX9-NEXT: v_trunc_f32_e32 v4, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX9-NEXT: s_mov_b32 s9, 0xc2fc0000
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
+; GFX9-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
+; GFX9-NEXT: v_not_b32_e32 v9, 63
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX9-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
+; GFX9-NEXT: v_add_f32_e32 v6, v6, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX9-NEXT: v_log_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-NEXT: v_log_f32_e32 v2, v2
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX9-NEXT: v_exp_f32_e32 v1, v2
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
+; GFX9-NEXT: v_exp_f32_e32 v6, v6
+; GFX9-NEXT: v_sub_f32_e32 v2, v4, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_ldexp_f32 v6, v6, v10
+; GFX9-NEXT: s_brev_b32 s10, -2
+; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
+; GFX9-NEXT: v_bfi_b32 v6, s10, v6, v8
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
+; GFX9-NEXT: v_trunc_f32_e32 v6, v5
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
+; GFX9-NEXT: v_bfi_b32 v2, s10, v2, v6
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX9-NEXT: v_pack_b32_f16 v0, v0, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_v2f16_fneg_lhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v5, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: s_mov_b32 s8, 0.5
+; GFX90A-NEXT: v_fma_mix_f32 v2, v1, s8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX90A-NEXT: s_mov_b32 s9, 0x800000
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v2
+; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v5|, s9
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v2
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
+; GFX90A-NEXT: v_ldexp_f32 v4, |v5|, v4
+; GFX90A-NEXT: v_log_f32_e32 v4, v4
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX90A-NEXT: v_log_f32_e32 v2, v2
-; GFX90A-NEXT: v_log_f32_e32 v0, v0
-; GFX90A-NEXT: v_mul_legacy_f32 v2, v3, v2
-; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
-; GFX90A-NEXT: v_exp_f32_e32 v1, v2
-; GFX90A-NEXT: v_exp_f32_e32 v0, v0
-; GFX90A-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[4:5]
+; GFX90A-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; GFX90A-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX90A-NEXT: v_trunc_f32_e32 v2, v3
+; GFX90A-NEXT: v_mul_legacy_f32 v4, v3, v4
+; GFX90A-NEXT: s_mov_b32 s10, 0xc2fc0000
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[6:7], v2, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v4
+; GFX90A-NEXT: v_not_b32_e32 v9, 63
+; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX90A-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s9
+; GFX90A-NEXT: v_add_f32_e32 v4, v4, v8
+; GFX90A-NEXT: v_cndmask_b32_e32 v8, 1.0, v5, vcc
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v2, v3
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, s[4:5]
+; GFX90A-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX90A-NEXT: v_log_f32_e32 v3, v3
+; GFX90A-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v6, v1
+; GFX90A-NEXT: v_exp_f32_e32 v4, v4
+; GFX90A-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX90A-NEXT: s_brev_b32 s11, -2
+; GFX90A-NEXT: v_mul_legacy_f32 v2, v6, v2
+; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v2
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[4:5]
+; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX90A-NEXT: v_exp_f32_e32 v2, v2
+; GFX90A-NEXT: v_ldexp_f32 v4, v4, v10
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v5, 24
+; GFX90A-NEXT: v_bfi_b32 v4, s11, v4, v8
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0x7fc00000
+; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v9, s[4:5]
+; GFX90A-NEXT: v_fma_mix_f32 v1, v1, s8, neg(0) op_sel_hi:[1,0,0]
+; GFX90A-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v1
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v1, v6
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v6
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v6
+; GFX90A-NEXT: v_bfi_b32 v2, s11, v2, v4
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
+; GFX90A-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v3
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f16_fneg_lhs:
@@ -448,14 +1676,59 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX10-NEXT: v_log_f32_e32 v2, v2
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX10-NEXT: v_exp_f32_e32 v1, v2
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e32 v10, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 32, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s5
+; GFX10-NEXT: s_mov_b32 s4, 0.5
+; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX10-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX10-NEXT: v_fma_mix_f32 v8, v1, s4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v10, v7
+; GFX10-NEXT: v_log_f32_e32 v3, v3
+; GFX10-NEXT: v_log_f32_e32 v5, v5
+; GFX10-NEXT: v_trunc_f32_e32 v9, v8
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v9, v8
+; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v1
+; GFX10-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_fma_mix_f32 v1, v1, s4, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: s_and_b32 s5, s6, s5
+; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v7, v3
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_trunc_f32_e32 v11, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v11, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, v2, s5
+; GFX10-NEXT: v_cmp_class_f32_e64 s5, v2, 24
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, s4
+; GFX10-NEXT: v_exp_f32_e32 v3, v3
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v5
+; GFX10-NEXT: v_trunc_f32_e32 v5, v6
+; GFX10-NEXT: v_exp_f32_e32 v4, v4
+; GFX10-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v6
+; GFX10-NEXT: v_bfi_b32 v1, 0x7fffffff, v3, v1
+; GFX10-NEXT: v_ldexp_f32 v3, v4, v8
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f32_e64 s4, v5, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v10, v7
+; GFX10-NEXT: s_and_b32 s4, s6, s4
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v4
+; GFX10-NEXT: s_and_b32 s5, s5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -466,22 +1739,76 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, -v2.l
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0.5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v0
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v7
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, s0, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v5
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v1
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s4, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v3, v1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, v5
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -490,24 +1817,77 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v6
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0.5
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v7
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v1
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, s0, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v5
+; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s4, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v4, v5
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%x.fneg = fneg <2 x half> %x
@@ -519,77 +1899,282 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6-LABEL: v_pow_v2f16_fneg_rhs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX6-NEXT: s_mov_b32 s8, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
+; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e64 v7, |v3|, v7
+; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v2
+; GFX6-NEXT: v_log_f32_e32 v7, v7
+; GFX6-NEXT: v_trunc_f32_e32 v6, v5
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
+; GFX6-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX6-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX6-NEXT: s_mov_b32 s9, 0xc2fc0000
+; GFX6-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
+; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX6-NEXT: v_add_f32_e32 v6, v6, v8
+; GFX6-NEXT: v_exp_f32_e32 v6, v6
+; GFX6-NEXT: v_trunc_f32_e32 v4, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX6-NEXT: v_log_f32_e32 v2, v2
-; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
+; GFX6-NEXT: v_not_b32_e32 v9, 63
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v6, v6, v10
+; GFX6-NEXT: s_brev_b32 s10, -2
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v3, 24
+; GFX6-NEXT: v_bfi_b32 v6, s10, v6, v8
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v6, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 32, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e64 v6, |v0|, v6
+; GFX6-NEXT: v_log_f32_e32 v6, v6
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX6-NEXT: v_exp_f32_e32 v2, v2
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
+; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX6-NEXT: v_sub_f32_e32 v5, v6, v5
+; GFX6-NEXT: v_mul_legacy_f32_e32 v5, v1, v5
+; GFX6-NEXT: v_cmp_gt_f32_e64 s[6:7], s9, v5
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[6:7]
+; GFX6-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX6-NEXT: v_mul_f32_e32 v8, 0.5, v1
+; GFX6-NEXT: v_exp_f32_e32 v5, v5
+; GFX6-NEXT: v_trunc_f32_e32 v4, v1
+; GFX6-NEXT: v_trunc_f32_e32 v10, v8
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v1
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v8
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, v9, s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v5, v5, v7
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: v_bfi_b32 v5, s10, v5, v6
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_v2f16_fneg_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: s_mov_b32 s8, 0x800000
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
+; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v2
+; GFX8-NEXT: v_log_f32_e32 v7, v7
+; GFX8-NEXT: v_trunc_f32_e32 v6, v5
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
+; GFX8-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX8-NEXT: v_trunc_f32_e32 v4, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX8-NEXT: s_mov_b32 s9, 0xc2fc0000
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
+; GFX8-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
+; GFX8-NEXT: v_not_b32_e32 v9, 63
+; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX8-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
+; GFX8-NEXT: v_add_f32_e32 v6, v6, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX8-NEXT: v_log_f32_e32 v4, v4
; GFX8-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX8-NEXT: v_log_f32_e32 v2, v2
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX8-NEXT: v_exp_f32_e32 v1, v2
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
+; GFX8-NEXT: v_exp_f32_e32 v6, v6
+; GFX8-NEXT: v_sub_f32_e32 v2, v4, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_ldexp_f32 v6, v6, v10
+; GFX8-NEXT: s_brev_b32 s10, -2
+; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
+; GFX8-NEXT: v_bfi_b32 v6, s10, v6, v8
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
+; GFX8-NEXT: v_trunc_f32_e32 v6, v5
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
+; GFX8-NEXT: v_bfi_b32 v2, s10, v2, v6
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; GFX8-NEXT: v_cvt_f16_f32_sdwa v4, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_v2f16_fneg_rhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: s_mov_b32 s8, 0x800000
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v2
+; GFX9-NEXT: v_log_f32_e32 v7, v7
+; GFX9-NEXT: v_trunc_f32_e32 v6, v5
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
+; GFX9-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX9-NEXT: v_trunc_f32_e32 v4, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX9-NEXT: s_mov_b32 s9, 0xc2fc0000
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
+; GFX9-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
+; GFX9-NEXT: v_not_b32_e32 v9, 63
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX9-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
+; GFX9-NEXT: v_add_f32_e32 v6, v6, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX9-NEXT: v_log_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX9-NEXT: v_log_f32_e32 v2, v2
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX9-NEXT: v_exp_f32_e32 v1, v2
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
+; GFX9-NEXT: v_exp_f32_e32 v6, v6
+; GFX9-NEXT: v_sub_f32_e32 v2, v4, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_ldexp_f32 v6, v6, v10
+; GFX9-NEXT: s_brev_b32 s10, -2
+; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
+; GFX9-NEXT: v_bfi_b32 v6, s10, v6, v8
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
+; GFX9-NEXT: v_trunc_f32_e32 v6, v5
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
+; GFX9-NEXT: v_bfi_b32 v2, s10, v2, v6
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX9-NEXT: v_pack_b32_f16 v0, v0, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_v2f16_fneg_rhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: s_mov_b32 s8, 0.5
+; GFX90A-NEXT: v_fma_mix_f32 v2, -v1, s8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX90A-NEXT: s_mov_b32 s9, 0x800000
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v2
+; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v5|, s9
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v2
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
+; GFX90A-NEXT: v_ldexp_f32 v4, |v5|, v4
+; GFX90A-NEXT: v_log_f32_e32 v4, v4
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX90A-NEXT: v_log_f32_e32 v2, v2
-; GFX90A-NEXT: v_log_f32_e32 v0, v0
-; GFX90A-NEXT: v_mul_legacy_f32 v2, v3, v2
-; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
-; GFX90A-NEXT: v_exp_f32_e32 v1, v2
-; GFX90A-NEXT: v_exp_f32_e32 v0, v0
-; GFX90A-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[4:5]
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX90A-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX90A-NEXT: v_trunc_f32_e32 v2, v3
+; GFX90A-NEXT: v_mul_legacy_f32 v4, v3, v4
+; GFX90A-NEXT: s_mov_b32 s10, 0xc2fc0000
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[6:7], v2, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v4
+; GFX90A-NEXT: v_not_b32_e32 v9, 63
+; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX90A-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s9
+; GFX90A-NEXT: v_add_f32_e32 v4, v4, v8
+; GFX90A-NEXT: v_cndmask_b32_e32 v8, 1.0, v5, vcc
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v2, v3
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, s[4:5]
+; GFX90A-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX90A-NEXT: v_log_f32_e32 v3, v3
+; GFX90A-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX90A-NEXT: v_cvt_f32_f16_e64 v6, -v1
+; GFX90A-NEXT: v_exp_f32_e32 v4, v4
+; GFX90A-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX90A-NEXT: s_brev_b32 s11, -2
+; GFX90A-NEXT: v_mul_legacy_f32 v2, v6, v2
+; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v2
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[4:5]
+; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX90A-NEXT: v_exp_f32_e32 v2, v2
+; GFX90A-NEXT: v_ldexp_f32 v4, v4, v10
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v5, 24
+; GFX90A-NEXT: v_bfi_b32 v4, s11, v4, v8
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0x7fc00000
+; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v9, s[4:5]
+; GFX90A-NEXT: v_fma_mix_f32 v1, -v1, s8, neg(0) op_sel_hi:[1,0,0]
+; GFX90A-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v1
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v1, v6
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v6
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v6
+; GFX90A-NEXT: v_bfi_b32 v2, s11, v2, v4
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
+; GFX90A-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v3
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f16_fneg_rhs:
@@ -597,14 +2182,59 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX10-NEXT: v_log_f32_e32 v2, v2
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX10-NEXT: v_exp_f32_e32 v1, v2
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v7, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e32 v10, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 32, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s5
+; GFX10-NEXT: s_mov_b32 s4, 0.5
+; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX10-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX10-NEXT: v_fma_mix_f32 v8, -v1, s4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v10, v7
+; GFX10-NEXT: v_log_f32_e32 v3, v3
+; GFX10-NEXT: v_log_f32_e32 v5, v5
+; GFX10-NEXT: v_trunc_f32_e32 v9, v8
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v9, v8
+; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX10-NEXT: v_cvt_f32_f16_e64 v6, -v1
+; GFX10-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_fma_mix_f32 v1, -v1, s4, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: s_and_b32 s5, s6, s5
+; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v7, v3
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_trunc_f32_e32 v11, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v11, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, v2, s5
+; GFX10-NEXT: v_cmp_class_f32_e64 s5, v2, 24
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, s4
+; GFX10-NEXT: v_exp_f32_e32 v3, v3
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v5
+; GFX10-NEXT: v_trunc_f32_e32 v5, v6
+; GFX10-NEXT: v_exp_f32_e32 v4, v4
+; GFX10-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v6
+; GFX10-NEXT: v_bfi_b32 v1, 0x7fffffff, v3, v1
+; GFX10-NEXT: v_ldexp_f32 v3, v4, v8
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f32_e64 s4, v5, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v10, v7
+; GFX10-NEXT: s_and_b32 s4, s6, s4
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v4
+; GFX10-NEXT: s_and_b32 s5, s5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -615,22 +2245,76 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, -v3.l
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, -v6.l
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0.5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v0
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v7
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v7, -v1.l
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, s0, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v5
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v1
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s4, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v3, v1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, v5
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -639,24 +2323,77 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, -v3
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v6, -v6
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0.5
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v7
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v7, -v1
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, s0, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v5
+; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s4, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v4, v5
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%y.fneg = fneg <2 x half> %y
@@ -669,77 +2406,282 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX6-NEXT: s_mov_b32 s8, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
+; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e64 v7, |v3|, v7
+; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v2
+; GFX6-NEXT: v_log_f32_e32 v7, v7
+; GFX6-NEXT: v_trunc_f32_e32 v6, v5
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
+; GFX6-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX6-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX6-NEXT: s_mov_b32 s9, 0xc2fc0000
+; GFX6-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
+; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX6-NEXT: v_add_f32_e32 v6, v6, v8
+; GFX6-NEXT: v_trunc_f32_e32 v4, v2
+; GFX6-NEXT: v_exp_f32_e32 v6, v6
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX6-NEXT: v_not_b32_e32 v9, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v3, 24
+; GFX6-NEXT: v_ldexp_f32_e32 v6, v6, v10
+; GFX6-NEXT: s_brev_b32 s10, -2
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
+; GFX6-NEXT: v_bfi_b32 v6, s10, v6, v8
+; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, 32, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e64 v8, |v0|, v8
+; GFX6-NEXT: v_log_f32_e32 v8, v8
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX6-NEXT: v_exp_f32_e32 v2, v2
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX6-NEXT: v_sub_f32_e32 v5, v8, v5
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v6, v2, vcc
+; GFX6-NEXT: v_mul_f32_e32 v6, 0.5, v1
+; GFX6-NEXT: v_mul_legacy_f32_e32 v5, v1, v5
+; GFX6-NEXT: v_trunc_f32_e32 v10, v6
+; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v5
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[6:7], v10, v6
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[4:5]
+; GFX6-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX6-NEXT: v_exp_f32_e32 v5, v5
+; GFX6-NEXT: v_trunc_f32_e32 v4, v1
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v1
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, v9, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v5, v5, v7
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: v_bfi_b32 v5, s10, v5, v6
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: s_mov_b32 s8, 0x800000
; GFX8-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
+; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v2
+; GFX8-NEXT: v_log_f32_e32 v7, v7
+; GFX8-NEXT: v_trunc_f32_e32 v6, v5
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
+; GFX8-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX8-NEXT: v_trunc_f32_e32 v4, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX8-NEXT: s_mov_b32 s9, 0xc2fc0000
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
+; GFX8-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
+; GFX8-NEXT: v_not_b32_e32 v9, 63
+; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX8-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
+; GFX8-NEXT: v_add_f32_e32 v6, v6, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX8-NEXT: v_log_f32_e32 v4, v4
; GFX8-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX8-NEXT: v_log_f32_e32 v2, v2
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX8-NEXT: v_exp_f32_e32 v1, v2
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
+; GFX8-NEXT: v_exp_f32_e32 v6, v6
+; GFX8-NEXT: v_sub_f32_e32 v2, v4, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_ldexp_f32 v6, v6, v10
+; GFX8-NEXT: s_brev_b32 s10, -2
+; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
+; GFX8-NEXT: v_bfi_b32 v6, s10, v6, v8
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
+; GFX8-NEXT: v_trunc_f32_e32 v6, v5
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
+; GFX8-NEXT: v_bfi_b32 v2, s10, v2, v6
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; GFX8-NEXT: v_cvt_f16_f32_sdwa v4, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: s_mov_b32 s8, 0x800000
; GFX9-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v2
+; GFX9-NEXT: v_log_f32_e32 v7, v7
+; GFX9-NEXT: v_trunc_f32_e32 v6, v5
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
+; GFX9-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX9-NEXT: v_trunc_f32_e32 v4, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX9-NEXT: s_mov_b32 s9, 0xc2fc0000
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
+; GFX9-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
+; GFX9-NEXT: v_not_b32_e32 v9, 63
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX9-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
+; GFX9-NEXT: v_add_f32_e32 v6, v6, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX9-NEXT: v_log_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX9-NEXT: v_log_f32_e32 v2, v2
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX9-NEXT: v_exp_f32_e32 v1, v2
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
+; GFX9-NEXT: v_exp_f32_e32 v6, v6
+; GFX9-NEXT: v_sub_f32_e32 v2, v4, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_ldexp_f32 v6, v6, v10
+; GFX9-NEXT: s_brev_b32 s10, -2
+; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
+; GFX9-NEXT: v_bfi_b32 v6, s10, v6, v8
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
+; GFX9-NEXT: v_trunc_f32_e32 v6, v5
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
+; GFX9-NEXT: v_bfi_b32 v2, s10, v2, v6
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX9-NEXT: v_pack_b32_f16 v0, v0, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v5, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: s_mov_b32 s8, 0.5
+; GFX90A-NEXT: v_fma_mix_f32 v2, -v1, s8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX90A-NEXT: s_mov_b32 s9, 0x800000
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v2
+; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v5|, s9
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v2
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
+; GFX90A-NEXT: v_ldexp_f32 v4, |v5|, v4
+; GFX90A-NEXT: v_log_f32_e32 v4, v4
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX90A-NEXT: v_log_f32_e32 v2, v2
-; GFX90A-NEXT: v_log_f32_e32 v0, v0
-; GFX90A-NEXT: v_mul_legacy_f32 v2, v3, v2
-; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
-; GFX90A-NEXT: v_exp_f32_e32 v1, v2
-; GFX90A-NEXT: v_exp_f32_e32 v0, v0
-; GFX90A-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[4:5]
+; GFX90A-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; GFX90A-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX90A-NEXT: v_trunc_f32_e32 v2, v3
+; GFX90A-NEXT: v_mul_legacy_f32 v4, v3, v4
+; GFX90A-NEXT: s_mov_b32 s10, 0xc2fc0000
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[6:7], v2, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v4
+; GFX90A-NEXT: v_not_b32_e32 v9, 63
+; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
+; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX90A-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s9
+; GFX90A-NEXT: v_add_f32_e32 v4, v4, v8
+; GFX90A-NEXT: v_cndmask_b32_e32 v8, 1.0, v5, vcc
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v2, v3
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, s[4:5]
+; GFX90A-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX90A-NEXT: v_log_f32_e32 v3, v3
+; GFX90A-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX90A-NEXT: v_cvt_f32_f16_e64 v6, -v1
+; GFX90A-NEXT: v_exp_f32_e32 v4, v4
+; GFX90A-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX90A-NEXT: s_brev_b32 s11, -2
+; GFX90A-NEXT: v_mul_legacy_f32 v2, v6, v2
+; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v2
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[4:5]
+; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX90A-NEXT: v_exp_f32_e32 v2, v2
+; GFX90A-NEXT: v_ldexp_f32 v4, v4, v10
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v5, 24
+; GFX90A-NEXT: v_bfi_b32 v4, s11, v4, v8
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0x7fc00000
+; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v9, s[4:5]
+; GFX90A-NEXT: v_fma_mix_f32 v1, -v1, s8, neg(0) op_sel_hi:[1,0,0]
+; GFX90A-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v1
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v1, v6
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v6
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v6
+; GFX90A-NEXT: v_bfi_b32 v2, s11, v2, v4
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
+; GFX90A-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v3
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f16_fneg_lhs_rhs:
@@ -747,14 +2689,59 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX10-NEXT: v_log_f32_e32 v2, v2
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v3, v2
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX10-NEXT: v_exp_f32_e32 v1, v2
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v7, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e32 v10, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 32, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s5
+; GFX10-NEXT: s_mov_b32 s4, 0.5
+; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX10-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX10-NEXT: v_fma_mix_f32 v8, -v1, s4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v10, v7
+; GFX10-NEXT: v_log_f32_e32 v3, v3
+; GFX10-NEXT: v_log_f32_e32 v5, v5
+; GFX10-NEXT: v_trunc_f32_e32 v9, v8
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v9, v8
+; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX10-NEXT: v_cvt_f32_f16_e64 v6, -v1
+; GFX10-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_fma_mix_f32 v1, -v1, s4, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: s_and_b32 s5, s6, s5
+; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v7, v3
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_trunc_f32_e32 v11, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v11, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, v2, s5
+; GFX10-NEXT: v_cmp_class_f32_e64 s5, v2, 24
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, s4
+; GFX10-NEXT: v_exp_f32_e32 v3, v3
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v5
+; GFX10-NEXT: v_trunc_f32_e32 v5, v6
+; GFX10-NEXT: v_exp_f32_e32 v4, v4
+; GFX10-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v6
+; GFX10-NEXT: v_bfi_b32 v1, 0x7fffffff, v3, v1
+; GFX10-NEXT: v_ldexp_f32 v3, v4, v8
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f32_e64 s4, v5, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v10, v7
+; GFX10-NEXT: s_and_b32 s4, s6, s4
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v4
+; GFX10-NEXT: s_and_b32 s5, s5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -765,22 +2752,76 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, -v2.l
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, -v3.l
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, -v6.l
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0.5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v0
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v7
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v7, -v1.l
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, s0, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v5
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v1
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s4, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v3, v1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, v5
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -789,24 +2830,77 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, -v3
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v6, -v6
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0.5
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v0|, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v2
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v7
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v7, -v1
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, s0, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v5
+; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s4, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v4, v5
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%x.fneg = fneg <2 x half> %x
@@ -825,51 +2919,141 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX6-LABEL: v_pow_f32_fabs_lhs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_log_f32_e64 v0, |v0|
+; GFX6-NEXT: s_mov_b32 s4, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v3
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fabs_lhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_log_f32_e64 v0, |v0|
+; GFX8-NEXT: s_mov_b32 s4, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v3
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fabs_lhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_log_f32_e64 v0, |v0|
+; GFX9-NEXT: s_mov_b32 s4, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v3
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_f32_fabs_lhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_log_f32_e64 v0, |v0|
+; GFX90A-NEXT: s_mov_b32 s4, 0x800000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v0, |v0|, v3
+; GFX90A-NEXT: v_log_f32_e32 v0, v0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX90A-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX90A-NEXT: v_add_f32_e32 v0, v0, v1
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
+; GFX90A-NEXT: v_not_b32_e32 v1, 63
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX90A-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX90A-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_lhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_log_f32_e64 v0, |v0|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v3
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_lhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_log_f32_e64 v0, |v0|
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
%pow = call float @llvm.pow.f32(float %fabs.x, float %y)
@@ -880,51 +3064,217 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX6-LABEL: v_pow_f32_fabs_rhs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: s_mov_b32 s4, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v3, |v0|, v3
+; GFX6-NEXT: v_log_f32_e32 v3, v3
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX6-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
+; GFX6-NEXT: v_trunc_f32_e32 v4, v3
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX6-NEXT: v_trunc_f32_e64 v3, |v1|
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, |v1|
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX6-NEXT: s_brev_b32 s4, -2
+; GFX6-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: v_cmp_neq_f32_e64 s[6:7], v3, |v1|
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fabs_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: s_mov_b32 s4, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX8-NEXT: v_log_f32_e32 v3, v3
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX8-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
+; GFX8-NEXT: v_trunc_f32_e32 v4, v3
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX8-NEXT: v_trunc_f32_e64 v3, |v1|
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, |v1|
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX8-NEXT: s_brev_b32 s4, -2
+; GFX8-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cmp_neq_f32_e64 s[6:7], v3, |v1|
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fabs_rhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s4, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX9-NEXT: v_log_f32_e32 v3, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX9-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX9-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
+; GFX9-NEXT: v_trunc_f32_e32 v4, v3
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX9-NEXT: v_trunc_f32_e64 v3, |v1|
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, |v1|
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX9-NEXT: s_brev_b32 s4, -2
+; GFX9-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: v_cmp_neq_f32_e64 s[6:7], v3, |v1|
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_f32_fabs_rhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_log_f32_e32 v0, v0
-; GFX90A-NEXT: v_mul_legacy_f32 v0, |v1|, v0
-; GFX90A-NEXT: v_exp_f32_e32 v0, v0
+; GFX90A-NEXT: s_mov_b32 s4, 0x800000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX90A-NEXT: v_log_f32_e32 v3, v3
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX90A-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX90A-NEXT: v_mul_legacy_f32 v2, |v1|, v2
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX90A-NEXT: v_exp_f32_e32 v2, v2
+; GFX90A-NEXT: v_not_b32_e32 v3, 63
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX90A-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX90A-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v3
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX90A-NEXT: v_trunc_f32_e64 v3, |v1|
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, |v1|
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX90A-NEXT: s_brev_b32 s4, -2
+; GFX90A-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e64 s[6:7], v3, |v1|
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_rhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e64 v4, |v1|
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v4, |v1|
+; GFX10-NEXT: v_cmp_neq_f32_e64 s5, v4, |v1|
+; GFX10-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX10-NEXT: v_log_f32_e32 v3, v3
+; GFX10-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX10-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
+; GFX10-NEXT: v_exp_f32_e32 v2, v2
+; GFX10-NEXT: v_trunc_f32_e32 v5, v3
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX10-NEXT: s_and_b32 s4, s4, s5
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_rhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: v_trunc_f32_e64 v4, |v1|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v4, |v1|
+; GFX11-NEXT: v_cmp_neq_f32_e64 s1, v4, |v1|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX11-NEXT: v_log_f32_e32 v3, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, |v1|, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v2, |v1|, v2
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
+; GFX11-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v5, v3
+; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX11-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX11-NEXT: s_and_b32 s0, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call float @llvm.fabs.f32(float %y)
%pow = call float @llvm.pow.f32(float %x, float %fabs.y)
@@ -935,51 +3285,141 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX6-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_log_f32_e64 v0, |v0|
+; GFX6-NEXT: s_mov_b32 s4, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v3
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX6-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_log_f32_e64 v0, |v0|
+; GFX8-NEXT: s_mov_b32 s4, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v3
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX8-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_log_f32_e64 v0, |v0|
+; GFX9-NEXT: s_mov_b32 s4, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v3
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX9-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_log_f32_e64 v0, |v0|
+; GFX90A-NEXT: s_mov_b32 s4, 0x800000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v0, |v0|, v3
+; GFX90A-NEXT: v_log_f32_e32 v0, v0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX90A-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX90A-NEXT: v_mul_legacy_f32 v0, |v1|, v0
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX90A-NEXT: v_add_f32_e32 v0, v0, v1
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
+; GFX90A-NEXT: v_not_b32_e32 v1, 63
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX90A-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX90A-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_log_f32_e64 v0, |v0|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v3
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX10-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_log_f32_e64 v0, |v0|
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, |v1|, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
%fabs.y = call float @llvm.fabs.f32(float %y)
@@ -990,46 +3430,226 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX6-LABEL: v_pow_f32_sgpr_vgpr:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_log_f32_e32 v1, s0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v1
+; GFX6-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: s_cselect_b32 s1, 32, 0
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |s0|, v2
+; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: s_mov_b32 s1, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v0, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s1, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_exp_f32_e32 v1, v1
+; GFX6-NEXT: v_not_b32_e32 v2, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: s_brev_b32 s1, -2
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_mul_f32_e32 v2, 0.5, v0
+; GFX6-NEXT: v_trunc_f32_e32 v3, v2
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v0
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[2:3], v2, v0
+; GFX6-NEXT: v_mov_b32_e32 v3, s0
+; GFX6-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
+; GFX6-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX6-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v2, v0
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[0:1], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: v_pow_f32_sgpr_vgpr:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_log_f32_e32 v1, s0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v1
+; GFX8-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: s_cselect_b32 s1, 32, 0
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: v_ldexp_f32 v2, |s0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: s_mov_b32 s1, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v0, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s1, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX8-NEXT: v_exp_f32_e32 v1, v1
+; GFX8-NEXT: v_not_b32_e32 v2, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: s_brev_b32 s1, -2
+; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX8-NEXT: v_mul_f32_e32 v2, 0.5, v0
+; GFX8-NEXT: v_trunc_f32_e32 v3, v2
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX8-NEXT: v_trunc_f32_e32 v2, v0
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[2:3], v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
+; GFX8-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX8-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[0:1], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: v_pow_f32_sgpr_vgpr:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_log_f32_e32 v1, s0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v1
+; GFX9-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: s_cselect_b32 s1, 32, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: v_ldexp_f32 v2, |s0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: s_mov_b32 s1, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX9-NEXT: v_exp_f32_e32 v1, v1
+; GFX9-NEXT: v_not_b32_e32 v2, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: s_brev_b32 s1, -2
+; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX9-NEXT: v_mul_f32_e32 v2, 0.5, v0
+; GFX9-NEXT: v_trunc_f32_e32 v3, v2
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX9-NEXT: v_trunc_f32_e32 v2, v0
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], v2, v0
+; GFX9-NEXT: v_mov_b32_e32 v3, s0
+; GFX9-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
+; GFX9-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX9-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v2, v0
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[0:1], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX90A-LABEL: v_pow_f32_sgpr_vgpr:
; GFX90A: ; %bb.0:
-; GFX90A-NEXT: v_log_f32_e32 v1, s0
-; GFX90A-NEXT: v_mul_legacy_f32 v0, v0, v1
-; GFX90A-NEXT: v_exp_f32_e32 v0, v0
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v1
+; GFX90A-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX90A-NEXT: s_cselect_b32 s1, 32, 0
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX90A-NEXT: v_mov_b32_e32 v2, s1
+; GFX90A-NEXT: v_ldexp_f32 v2, |s0|, v2
+; GFX90A-NEXT: v_log_f32_e32 v2, v2
+; GFX90A-NEXT: s_mov_b32 s1, 0xc2fc0000
+; GFX90A-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX90A-NEXT: v_mul_legacy_f32 v1, v0, v1
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s1, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX90A-NEXT: v_exp_f32_e32 v1, v1
+; GFX90A-NEXT: v_not_b32_e32 v2, 63
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: s_brev_b32 s1, -2
+; GFX90A-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX90A-NEXT: v_mul_f32_e32 v2, 0.5, v0
+; GFX90A-NEXT: v_trunc_f32_e32 v3, v2
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX90A-NEXT: v_trunc_f32_e32 v2, v0
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[2:3], v2, v0
+; GFX90A-NEXT: v_mov_b32_e32 v3, s0
+; GFX90A-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
+; GFX90A-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v2, v0
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX90A-NEXT: s_and_b64 vcc, s[0:1], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX90A-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: v_pow_f32_sgpr_vgpr:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_log_f32_e32 v1, s0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0|
+; GFX10-NEXT: v_trunc_f32_e32 v3, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s1
+; GFX10-NEXT: s_and_b32 s1, s1, exec_lo
+; GFX10-NEXT: s_cselect_b32 s1, 32, 0
+; GFX10-NEXT: v_ldexp_f32 v2, |s0|, s1
+; GFX10-NEXT: v_cmp_eq_f32_e64 s1, v3, v0
+; GFX10-NEXT: v_log_f32_e32 v2, v2
+; GFX10-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v0, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_mul_f32_e32 v2, 0.5, v0
+; GFX10-NEXT: v_exp_f32_e32 v1, v1
+; GFX10-NEXT: v_trunc_f32_e32 v4, v2
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v4, v2
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX10-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v3, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, s0, s1
+; GFX10-NEXT: v_cmp_class_f32_e64 s0, s0, 24
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_pow_f32_sgpr_vgpr:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_log_f32_e32 v1, s0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0|
+; GFX11-NEXT: v_trunc_f32_e32 v3, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s1
+; GFX11-NEXT: s_and_b32 s1, s1, exec_lo
+; GFX11-NEXT: s_cselect_b32 s1, 32, 0
+; GFX11-NEXT: v_ldexp_f32 v2, |s0|, s1
+; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v3, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mul_f32 v2, 0.5, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-NEXT: v_trunc_f32_e32 v4, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v4, v2
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX11-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-NEXT: v_cmp_neq_f32_e32 vcc_lo, v3, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, s0, s1
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, s0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v2
+; GFX11-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow
@@ -1038,46 +3658,213 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX6-LABEL: v_pow_f32_vgpr_sgpr:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: s_mov_b32 s1, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s1
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: s_mov_b32 s1, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX6-NEXT: v_mul_legacy_f32_e32 v1, s0, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s1, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_exp_f32_e32 v1, v1
+; GFX6-NEXT: v_not_b32_e32 v2, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: s_brev_b32 s1, -2
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_mul_f32_e64 v2, s0, 0.5
+; GFX6-NEXT: v_trunc_f32_e32 v3, v2
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, s0
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, v2
+; GFX6-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc
+; GFX6-NEXT: v_cmp_class_f32_e64 s[2:3], v0, 24
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, s0, v2
+; GFX6-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: v_pow_f32_vgpr_sgpr:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: s_mov_b32 s1, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s1
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: s_mov_b32 s1, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX8-NEXT: v_mul_legacy_f32_e32 v1, s0, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s1, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX8-NEXT: v_exp_f32_e32 v1, v1
+; GFX8-NEXT: v_not_b32_e32 v2, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: s_brev_b32 s1, -2
+; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX8-NEXT: v_mul_f32_e64 v2, s0, 0.5
+; GFX8-NEXT: v_trunc_f32_e32 v3, v2
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX8-NEXT: v_trunc_f32_e32 v2, s0
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, v2
+; GFX8-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[2:3], v0, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, s0, v2
+; GFX8-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: v_pow_f32_vgpr_sgpr:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s1, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s1
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: s_mov_b32 s1, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX9-NEXT: v_mul_legacy_f32_e32 v1, s0, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX9-NEXT: v_exp_f32_e32 v1, v1
+; GFX9-NEXT: v_not_b32_e32 v2, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: s_brev_b32 s1, -2
+; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX9-NEXT: v_mul_f32_e64 v2, s0, 0.5
+; GFX9-NEXT: v_trunc_f32_e32 v3, v2
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX9-NEXT: v_trunc_f32_e32 v2, s0
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, v2
+; GFX9-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[2:3], v0, 24
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, s0, v2
+; GFX9-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX90A-LABEL: v_pow_f32_vgpr_sgpr:
; GFX90A: ; %bb.0:
-; GFX90A-NEXT: v_log_f32_e32 v0, v0
-; GFX90A-NEXT: v_mul_legacy_f32 v0, s0, v0
-; GFX90A-NEXT: v_exp_f32_e32 v0, v0
+; GFX90A-NEXT: s_mov_b32 s1, 0x800000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s1
+; GFX90A-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX90A-NEXT: v_log_f32_e32 v2, v2
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX90A-NEXT: s_mov_b32 s1, 0xc2fc0000
+; GFX90A-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX90A-NEXT: v_mul_legacy_f32 v1, s0, v1
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s1, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX90A-NEXT: v_exp_f32_e32 v1, v1
+; GFX90A-NEXT: v_not_b32_e32 v2, 63
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: s_brev_b32 s1, -2
+; GFX90A-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX90A-NEXT: v_mul_f32_e64 v2, s0, 0.5
+; GFX90A-NEXT: v_trunc_f32_e32 v3, v2
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX90A-NEXT: v_trunc_f32_e32 v2, s0
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, v2
+; GFX90A-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[2:3], v0, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, s0, v2
+; GFX90A-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX90A-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX90A-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: v_pow_f32_vgpr_sgpr:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e32 v3, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 32, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s1
+; GFX10-NEXT: v_cmp_eq_f32_e64 s1, s0, v3
+; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX10-NEXT: v_log_f32_e32 v2, v2
+; GFX10-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v1, s0, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_mul_f32_e64 v2, s0, 0.5
+; GFX10-NEXT: v_exp_f32_e32 v1, v1
+; GFX10-NEXT: v_trunc_f32_e32 v4, v2
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v4, v2
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX10-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
+; GFX10-NEXT: v_cmp_class_f32_e64 s1, v0, 24
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, s0, v3
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: s_and_b32 s0, s1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_pow_f32_vgpr_sgpr:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-NEXT: v_trunc_f32_e32 v3, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 32, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s1
+; GFX11-NEXT: v_cmp_eq_f32_e64 s1, s0, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, s0, v1
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_mul_f32_e64 v2, s0, 0.5
+; GFX11-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v4, v2
+; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v4, v2
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX11-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
+; GFX11-NEXT: v_cmp_class_f32_e64 s1, v0, 24
+; GFX11-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc_lo
+; GFX11-NEXT: v_cmp_neq_f32_e32 vcc_lo, s0, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v2
+; GFX11-NEXT: s_and_b32 s0, s1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow
@@ -1086,51 +3873,1013 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX6-LABEL: v_pow_f32_sgpr_sgpr:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_log_f32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v0
+; GFX6-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX6-NEXT: s_cselect_b32 s2, 32, 0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX6-NEXT: v_mov_b32_e32 v1, s2
+; GFX6-NEXT: v_ldexp_f32_e64 v1, |s0|, v1
+; GFX6-NEXT: v_log_f32_e32 v1, v1
+; GFX6-NEXT: s_mov_b32 s2, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_f32_e64 v1, s1, 0.5
+; GFX6-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX6-NEXT: v_trunc_f32_e32 v2, v1
+; GFX6-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v2, v1
+; GFX6-NEXT: v_trunc_f32_e32 v1, s1
+; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s2
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, s0
+; GFX6-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GFX6-NEXT: s_brev_b32 s2, -2
+; GFX6-NEXT: v_bfi_b32 v0, s2, v0, v2
+; GFX6-NEXT: v_cmp_class_f32_e64 s[2:3], s0, 24
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, s1, v1
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: v_pow_f32_sgpr_sgpr:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_log_f32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v0
+; GFX8-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX8-NEXT: s_cselect_b32 s2, 32, 0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX8-NEXT: v_mov_b32_e32 v1, s2
+; GFX8-NEXT: v_ldexp_f32 v1, |s0|, v1
+; GFX8-NEXT: v_log_f32_e32 v1, v1
+; GFX8-NEXT: s_mov_b32 s2, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_f32_e64 v1, s1, 0.5
+; GFX8-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX8-NEXT: v_trunc_f32_e32 v2, v1
+; GFX8-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v2, v1
+; GFX8-NEXT: v_trunc_f32_e32 v1, s1
+; GFX8-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GFX8-NEXT: s_brev_b32 s2, -2
+; GFX8-NEXT: v_bfi_b32 v0, s2, v0, v2
+; GFX8-NEXT: v_cmp_class_f32_e64 s[2:3], s0, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, s1, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: v_pow_f32_sgpr_sgpr:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_log_f32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v0
+; GFX9-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX9-NEXT: s_cselect_b32 s2, 32, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: v_mov_b32_e32 v1, s2
+; GFX9-NEXT: v_ldexp_f32 v1, |s0|, v1
+; GFX9-NEXT: v_log_f32_e32 v1, v1
+; GFX9-NEXT: s_mov_b32 s2, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e64 v1, s1, 0.5
+; GFX9-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX9-NEXT: v_trunc_f32_e32 v2, v1
+; GFX9-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v2, v1
+; GFX9-NEXT: v_trunc_f32_e32 v1, s1
+; GFX9-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GFX9-NEXT: s_brev_b32 s2, -2
+; GFX9-NEXT: v_bfi_b32 v0, s2, v0, v2
+; GFX9-NEXT: v_cmp_class_f32_e64 s[2:3], s0, 24
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, s1, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX90A-LABEL: v_pow_f32_sgpr_sgpr:
; GFX90A: ; %bb.0:
-; GFX90A-NEXT: v_log_f32_e32 v0, s0
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v0
+; GFX90A-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX90A-NEXT: s_cselect_b32 s2, 32, 0
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX90A-NEXT: v_mov_b32_e32 v1, s2
+; GFX90A-NEXT: v_ldexp_f32 v1, |s0|, v1
+; GFX90A-NEXT: v_log_f32_e32 v1, v1
+; GFX90A-NEXT: s_mov_b32 s2, 0xc2fc0000
+; GFX90A-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX90A-NEXT: v_mul_legacy_f32 v0, s1, v0
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX90A-NEXT: v_add_f32_e32 v0, v0, v1
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
+; GFX90A-NEXT: v_mul_f32_e64 v1, s1, 0.5
+; GFX90A-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX90A-NEXT: v_trunc_f32_e32 v2, v1
+; GFX90A-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v2, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v1, s1
+; GFX90A-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, v1
+; GFX90A-NEXT: v_mov_b32_e32 v2, s0
+; GFX90A-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GFX90A-NEXT: s_brev_b32 s2, -2
+; GFX90A-NEXT: v_bfi_b32 v0, s2, v0, v2
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[2:3], s0, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, s1, v1
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; GFX90A-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX90A-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: v_pow_f32_sgpr_sgpr:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_log_f32_e32 v0, s0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0|
+; GFX10-NEXT: v_trunc_f32_e32 v2, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s2
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 32, 0
+; GFX10-NEXT: v_ldexp_f32 v1, |s0|, s2
+; GFX10-NEXT: v_cmp_eq_f32_e64 s2, s1, v2
+; GFX10-NEXT: v_log_f32_e32 v1, v1
+; GFX10-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: s_and_b32 s4, vcc_lo, exec_lo
+; GFX10-NEXT: s_cselect_b32 s4, 0xffffffc0, 0
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, s1, v2
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_mul_f32_e64 v1, s1, 0.5
; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_trunc_f32_e32 v3, v1
+; GFX10-NEXT: v_cmp_lg_f32_e64 s3, v3, v1
+; GFX10-NEXT: v_ldexp_f32 v0, v0, s4
+; GFX10-NEXT: s_and_b32 s2, s2, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, s0, s2
+; GFX10-NEXT: v_cmp_class_f32_e64 s0, s0, 24
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1
+; GFX10-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_pow_f32_sgpr_sgpr:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_log_f32_e32 v0, s0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0|
+; GFX11-NEXT: v_trunc_f32_e32 v2, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s2
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 32, 0
+; GFX11-NEXT: v_ldexp_f32 v1, |s0|, s2
+; GFX11-NEXT: v_cmp_eq_f32_e64 s2, s1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v1, v1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_and_b32 s4, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s4, 0xffffffc0, 0
+; GFX11-NEXT: v_cmp_neq_f32_e32 vcc_lo, s1, v2
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_mul_f32_e64 v1, s1, 0.5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_trunc_f32_e32 v3, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cmp_lg_f32_e64 s3, v3, v1
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, s4
+; GFX11-NEXT: s_and_b32 s2, s2, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, s0, s2
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, s0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1
+; GFX11-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow
}
+define float @v_pow_f32_afn(float %x, float %y) {
+; GFX6-LABEL: v_pow_f32_afn:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f32_afn:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f32_afn:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX90A-LABEL: v_pow_f32_afn:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_log_f32_e32 v0, v0
+; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
+; GFX90A-NEXT: v_exp_f32_e32 v0, v0
+; GFX90A-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f32_afn:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_pow_f32_afn:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %pow = call afn float @llvm.pow.f32(float %x, float %y)
+ ret float %pow
+}
+
+define half @v_pow_f16_afn(half %x, half %y) {
+; GFX6-LABEL: v_pow_f16_afn:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f16_afn:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f16_afn:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX90A-LABEL: v_pow_f16_afn:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX90A-NEXT: v_log_f32_e32 v0, v0
+; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
+; GFX90A-NEXT: v_exp_f32_e32 v0, v0
+; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX90A-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f16_afn:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_pow_f16_afn:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_pow_f16_afn:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+ %pow = call afn half @llvm.pow.f16(half %x, half %y)
+ ret half %pow
+}
+
+define float @v_pow_f32_const_even_int(float %x) {
+; GFX6-LABEL: v_pow_f32_const_even_int:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f32_const_even_int:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s4, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f32_const_even_int:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s4, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX90A-LABEL: v_pow_f32_const_even_int:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: s_mov_b32 s4, 0x800000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX90A-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX90A-NEXT: v_log_f32_e32 v0, v0
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX90A-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX90A-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX90A-NEXT: v_mul_legacy_f32 v0, 2.0, v0
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX90A-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX90A-NEXT: v_exp_f32_e32 v0, v0
+; GFX90A-NEXT: v_not_b32_e32 v1, 63
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX90A-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX90A-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX90A-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f32_const_even_int:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s4
+; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_pow_f32_const_even_int:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 32, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
+; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, 2.0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %pow = call float @llvm.pow.f32(float %x, float 2.0)
+ ret float %pow
+}
+
+define float @v_pow_f32_const_odd_int(float %x) {
+; GFX6-LABEL: v_pow_f32_const_odd_int:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX6-NEXT: v_mul_legacy_f32_e32 v1, 0x40400000, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_exp_f32_e32 v1, v1
+; GFX6-NEXT: v_not_b32_e32 v2, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: s_brev_b32 s4, -2
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_bfi_b32 v0, s4, v1, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f32_const_odd_int:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s4, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX8-NEXT: v_mul_legacy_f32_e32 v1, 0x40400000, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX8-NEXT: v_exp_f32_e32 v1, v1
+; GFX8-NEXT: v_not_b32_e32 v2, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: s_brev_b32 s4, -2
+; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX8-NEXT: v_bfi_b32 v0, s4, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f32_const_odd_int:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s4, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX9-NEXT: v_mul_legacy_f32_e32 v1, 0x40400000, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX9-NEXT: v_exp_f32_e32 v1, v1
+; GFX9-NEXT: v_not_b32_e32 v2, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: s_brev_b32 s4, -2
+; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX9-NEXT: v_bfi_b32 v0, s4, v1, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX90A-LABEL: v_pow_f32_const_odd_int:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: s_mov_b32 s4, 0x800000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX90A-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX90A-NEXT: v_log_f32_e32 v2, v2
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX90A-NEXT: s_mov_b32 s4, 0x40400000
+; GFX90A-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX90A-NEXT: v_mul_legacy_f32 v1, s4, v1
+; GFX90A-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX90A-NEXT: v_exp_f32_e32 v1, v1
+; GFX90A-NEXT: v_not_b32_e32 v2, 63
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: s_brev_b32 s4, -2
+; GFX90A-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX90A-NEXT: v_bfi_b32 v0, s4, v1, v0
+; GFX90A-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f32_const_odd_int:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s4
+; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX10-NEXT: v_log_f32_e32 v2, v2
+; GFX10-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v1, 0x40400000, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_exp_f32_e32 v1, v1
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_pow_f32_const_odd_int:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 32, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
+; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v2, v2
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, 0x40400000, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %pow = call float @llvm.pow.f32(float %x, float 3.0)
+ ret float %pow
+}
+
+define float @v_pow_f32_const_non_int(float %x) {
+; GFX6-LABEL: v_pow_f32_const_non_int:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v2, v2
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX6-NEXT: v_mul_legacy_f32_e32 v1, 0.5, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_exp_f32_e32 v1, v1
+; GFX6-NEXT: v_not_b32_e32 v2, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX6-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, s[4:5]
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f32_const_non_int:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s4, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v2, v2
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX8-NEXT: v_mul_legacy_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX8-NEXT: v_exp_f32_e32 v1, v1
+; GFX8-NEXT: v_not_b32_e32 v2, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX8-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, s[4:5]
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f32_const_non_int:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s4, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v2, v2
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX9-NEXT: v_mul_legacy_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX9-NEXT: v_exp_f32_e32 v1, v1
+; GFX9-NEXT: v_not_b32_e32 v2, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX9-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX90A-LABEL: v_pow_f32_const_non_int:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: s_mov_b32 s4, 0x800000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX90A-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX90A-NEXT: v_log_f32_e32 v2, v2
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX90A-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX90A-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX90A-NEXT: v_mul_legacy_f32 v1, 0.5, v1
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX90A-NEXT: v_exp_f32_e32 v1, v1
+; GFX90A-NEXT: v_not_b32_e32 v2, 63
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX90A-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX90A-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, s[4:5]
+; GFX90A-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f32_const_non_int:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s4
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX10-NEXT: v_log_f32_e32 v2, v2
+; GFX10-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v1, 0.5, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_exp_f32_e32 v1, v1
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v0, |v1|, 0x7fc00000, s4
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_pow_f32_const_non_int:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 32, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v2, v2
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v0, |v1|, 0x7fc00000, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %pow = call float @llvm.pow.f32(float %x, float 5.000000e-01)
+ ret float %pow
+}
+
+define float @v_pow_f32_nnan(float %x, float %y) {
+; GFX6-LABEL: v_pow_f32_nnan:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v3, |v0|, v3
+; GFX6-NEXT: v_log_f32_e32 v3, v3
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX6-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v4, v3
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; GFX6-NEXT: s_brev_b32 s4, -2
+; GFX6-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f32_nnan:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s4, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX8-NEXT: v_log_f32_e32 v3, v3
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v4, v3
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; GFX8-NEXT: s_brev_b32 s4, -2
+; GFX8-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f32_nnan:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s4, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX9-NEXT: v_log_f32_e32 v3, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX9-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v4, v3
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; GFX9-NEXT: s_brev_b32 s4, -2
+; GFX9-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX90A-LABEL: v_pow_f32_nnan:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: s_mov_b32 s4, 0x800000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX90A-NEXT: v_log_f32_e32 v3, v3
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX90A-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX90A-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX90A-NEXT: v_mul_legacy_f32 v2, v1, v2
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX90A-NEXT: v_exp_f32_e32 v2, v2
+; GFX90A-NEXT: v_not_b32_e32 v3, 63
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX90A-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX90A-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v3
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX90A-NEXT: v_trunc_f32_e32 v3, v1
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; GFX90A-NEXT: s_brev_b32 s4, -2
+; GFX90A-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX90A-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f32_nnan:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_trunc_f32_e32 v4, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v4, v1
+; GFX10-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX10-NEXT: v_log_f32_e32 v3, v3
+; GFX10-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_exp_f32_e32 v2, v2
+; GFX10-NEXT: v_trunc_f32_e32 v5, v3
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
+; GFX10-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_pow_f32_nnan:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: v_trunc_f32_e32 v4, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v4, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX11-NEXT: v_log_f32_e32 v3, v3
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v5, v3
+; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX11-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %pow = call nnan float @llvm.pow.f32(float %x, float %y)
+ ret float %pow
+}
+
declare half @llvm.pow.f16(half, half)
declare float @llvm.pow.f32(float, float)
declare double @llvm.pow.f64(double, double)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
index 9d4f22e5ea022..865399ef7e15a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
@@ -5,28 +5,126 @@
; RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
define i16 @v_powi_f16(i16 %l, i32 %r) {
-; GFX78-LABEL: v_powi_f16:
-; GFX78: ; %bb.0:
-; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX78-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX78-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX78-NEXT: v_log_f32_e32 v0, v0
-; GFX78-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX78-NEXT: v_exp_f32_e32 v0, v0
-; GFX78-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX78-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: v_powi_f16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX7-NEXT: s_mov_b32 s4, 0x800000
+; GFX7-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX7-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX7-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX7-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX7-NEXT: v_ldexp_f32_e64 v3, |v0|, v3
+; GFX7-NEXT: v_log_f32_e32 v3, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX7-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX7-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX7-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX7-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX7-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX7-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX7-NEXT: v_exp_f32_e32 v2, v2
+; GFX7-NEXT: v_not_b32_e32 v3, 63
+; GFX7-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX7-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX7-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX7-NEXT: v_trunc_f32_e32 v4, v3
+; GFX7-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX7-NEXT: v_trunc_f32_e32 v3, v1
+; GFX7-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX7-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX7-NEXT: s_brev_b32 s4, -2
+; GFX7-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX7-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX7-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX7-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX7-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_powi_f16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX8-NEXT: s_mov_b32 s4, 0x800000
+; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX8-NEXT: v_log_f32_e32 v3, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v4, v3
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX8-NEXT: s_brev_b32 s4, -2
+; GFX8-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_powi_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v4, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v4, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v3
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v4, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -35,12 +133,41 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v4, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v4, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v3
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v4, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%l.cast = bitcast i16 %l to half
@@ -50,24 +177,120 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
}
define float @v_powi_f32(float %l, i32 %r) {
-; GFX78-LABEL: v_powi_f32:
-; GFX78: ; %bb.0:
-; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX78-NEXT: v_log_f32_e32 v0, v0
-; GFX78-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX78-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX78-NEXT: v_exp_f32_e32 v0, v0
-; GFX78-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: v_powi_f32:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: s_mov_b32 s4, 0x800000
+; GFX7-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX7-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX7-NEXT: v_ldexp_f32_e64 v3, |v0|, v3
+; GFX7-NEXT: v_log_f32_e32 v3, v3
+; GFX7-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX7-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX7-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX7-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX7-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX7-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX7-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX7-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX7-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX7-NEXT: v_exp_f32_e32 v2, v2
+; GFX7-NEXT: v_not_b32_e32 v3, 63
+; GFX7-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX7-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; GFX7-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX7-NEXT: v_trunc_f32_e32 v4, v3
+; GFX7-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX7-NEXT: v_trunc_f32_e32 v3, v1
+; GFX7-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX7-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX7-NEXT: s_brev_b32 s4, -2
+; GFX7-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX7-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX7-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX7-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX7-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_powi_f32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s4, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX8-NEXT: v_log_f32_e32 v3, v3
+; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v4, v3
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX8-NEXT: s_brev_b32 s4, -2
+; GFX8-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT: v_trunc_f32_e32 v4, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v4, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v3, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-NEXT: v_trunc_f32_e32 v5, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX11-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
+; GFX11-NEXT: v_cmp_neq_f32_e32 vcc_lo, v4, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
+; GFX11-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 %r)
ret float %res
>From c253f03a88a084fb257e8902e350fbb96d9e54bd Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Wed, 9 Sep 2026 14:30:50 +0200
Subject: [PATCH 2/3] Address comments
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 42 +-
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 51 +-
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 2 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll | 3439 ++++++------
.../AMDGPU/GlobalISel/legalize-fpow.mir | 204 +-
.../AMDGPU/GlobalISel/legalize-fpowi.mir | 24 +-
.../CodeGen/AMDGPU/GlobalISel/llvm.powi.ll | 172 +-
llvm/test/CodeGen/AMDGPU/fpow.ll | 4687 +++++++++--------
llvm/test/CodeGen/AMDGPU/llvm.powi.ll | 258 +-
9 files changed, 4536 insertions(+), 4343 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 97a13012305e4..2cfa3e7afb9fb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -3324,20 +3324,29 @@ SDValue AMDGPUTargetLowering::lowerFPOW(SDValue Op, SelectionDAG &DAG) const {
SDValue Y = Op.getOperand(1);
SDNodeFlags Flags = Op->getFlags();
+ // log2(0) is -inf, which exp2 turns back into a finite result, so the core
+ // goes infinite for inputs a ninf fpow still asserts about, like pow(0, 2).
+ SDNodeFlags CoreFlags = Flags;
+ CoreFlags.setNoInfs(false);
+
// Fast expansion: ignores denormals, NaN for a negative base.
if (allowApproxFunc(DAG, Flags)) {
- SDValue Log = DAG.getNode(AMDGPUISD::LOG, SL, VT, X, Flags);
- SDValue Mul = DAG.getNode(AMDGPUISD::FMUL_LEGACY, SL, VT, Y, Log, Flags);
- return DAG.getNode(AMDGPUISD::EXP, SL, VT, Mul, Flags);
+ SDValue Log = DAG.getNode(AMDGPUISD::LOG, SL, VT, X, CoreFlags);
+ SDValue Mul =
+ DAG.getNode(AMDGPUISD::FMUL_LEGACY, SL, VT, Y, Log, CoreFlags);
+ return DAG.getNode(AMDGPUISD::EXP, SL, VT, Mul, CoreFlags);
}
SDValue Abs = DAG.getNode(ISD::FABS, SL, VT, X, Flags);
- SDValue Log = DAG.getNode(ISD::FLOG2, SL, VT, Abs, Flags);
- SDValue Mul = DAG.getNode(AMDGPUISD::FMUL_LEGACY, SL, VT, Y, Log, Flags);
- SDValue R = DAG.getNode(ISD::FEXP2, SL, VT, Mul, Flags);
+ SDValue Log = DAG.getNode(ISD::FLOG2, SL, VT, Abs, CoreFlags);
+ SDValue Mul = DAG.getNode(AMDGPUISD::FMUL_LEGACY, SL, VT, Y, Log, CoreFlags);
+ SDValue R = DAG.getNode(ISD::FEXP2, SL, VT, Mul, CoreFlags);
+
+ // A base that is never negative needs neither the sign fixup nor the NaN.
+ if (DAG.computeKnownFPClass(X, fcNegative).signBitIsZeroOrNaN())
+ return R;
EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
- SDValue One = DAG.getConstantFP(1.0, SL, VT);
// Infinities count as integers, and every f32 >= 2^24 in magnitude is even.
SDValue YTrunc = DAG.getNode(ISD::FTRUNC, SL, VT, Y);
@@ -3349,18 +3358,23 @@ SDValue AMDGPUTargetLowering::lowerFPOW(SDValue Op, SelectionDAG &DAG) const {
DAG.getNode(ISD::AND, SL, SetCCVT, YIsInt,
DAG.getSetCC(SL, SetCCVT, YHalfTrunc, YHalf, ISD::SETONE));
- // pow(-x, odd y) = -pow(x, y).
- R = DAG.getNode(ISD::FCOPYSIGN, SL, VT, R,
- DAG.getNode(ISD::SELECT, SL, VT, YIsOdd, X, One));
+ // pow(-x, odd y) = -pow(x, y). Selecting the copysign lets even y fold it.
+ R = DAG.getNode(ISD::SELECT, SL, VT, YIsOdd,
+ DAG.getNode(ISD::FCOPYSIGN, SL, VT, R, X), R);
if (Flags.hasNoNaNs())
return R;
// A negative finite base to a non-integral power is NaN. -inf is excluded:
- // the core already gives pow(+inf, y).
- SDValue XNegFinite = DAG.getNode(
- ISD::IS_FPCLASS, SL, SetCCVT, X,
- DAG.getTargetConstant(fcNegNormal | fcNegSubnormal, SL, MVT::i32));
+ // the core already gives pow(+inf, y). So are subnormals when flushed.
+ FPClassTest NegFiniteMask = fcNegNormal;
+ if (!DAG.getMachineFunction()
+ .getDenormalMode(APFloat::IEEEsingle())
+ .inputsAreZero())
+ NegFiniteMask |= fcNegSubnormal;
+ SDValue XNegFinite =
+ DAG.getNode(ISD::IS_FPCLASS, SL, SetCCVT, X,
+ DAG.getTargetConstant(NegFiniteMask, SL, MVT::i32));
// Not a SETONE compare: pow(-1, NaN) needs the NaN-true behavior of !SETOEQ.
SDValue NegNonInt = DAG.getNode(ISD::AND, SL, SetCCVT, XNegFinite,
DAG.getNOT(SL, YIsInt, SetCCVT));
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 36fbec46c2014..76038030cf162 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2383,7 +2383,7 @@ bool AMDGPULegalizerInfo::legalizeCustom(
case TargetOpcode::G_FEXP10:
return legalizeFExp(MI, B);
case TargetOpcode::G_FPOW:
- return legalizeFPow(MI, B);
+ return legalizeFPow(Helper, MI);
case TargetOpcode::G_FFLOOR:
return legalizeFFloor(MI, MRI, B);
case TargetOpcode::G_BUILD_VECTOR:
@@ -4276,37 +4276,50 @@ bool AMDGPULegalizerInfo::legalizeFExp(MachineInstr &MI,
}
// Keep in sync with AMDGPUTargetLowering::lowerFPOW, which documents this.
-bool AMDGPULegalizerInfo::legalizeFPow(MachineInstr &MI,
- MachineIRBuilder &B) const {
+bool AMDGPULegalizerInfo::legalizeFPow(LegalizerHelper &Helper,
+ MachineInstr &MI) const {
+ MachineIRBuilder &B = Helper.MIRBuilder;
Register Dst = MI.getOperand(0).getReg();
Register X = MI.getOperand(1).getReg();
Register Y = MI.getOperand(2).getReg();
unsigned Flags = MI.getFlags();
assert(B.getMRI()->getType(Dst) == F32);
+ // log2(0) is -inf, which exp2 turns back into a finite result, so the core
+ // goes infinite for inputs a ninf fpow still asserts about, like pow(0, 2).
+ unsigned CoreFlags = Flags & ~MachineInstr::FmNoInfs;
+
// Fast expansion: ignores denormals, NaN for a negative base.
if (allowApproxFunc(B.getMF(), Flags)) {
auto Log = B.buildIntrinsic(Intrinsic::amdgcn_log, {F32})
.addUse(X)
- .setMIFlags(Flags);
+ .setMIFlags(CoreFlags);
auto Mul = B.buildIntrinsic(Intrinsic::amdgcn_fmul_legacy, {F32})
.addUse(Y)
.addUse(Log.getReg(0))
- .setMIFlags(Flags);
- buildExp(B, Dst, Mul.getReg(0), Flags);
+ .setMIFlags(CoreFlags);
+ buildExp(B, Dst, Mul.getReg(0), CoreFlags);
MI.eraseFromParent();
return true;
}
auto Abs = B.buildFAbs(F32, X, Flags);
- auto Log = B.buildFLog2(F32, Abs, Flags);
+ auto Log = B.buildFLog2(F32, Abs, CoreFlags);
auto Mul = B.buildIntrinsic(Intrinsic::amdgcn_fmul_legacy, {F32})
.addUse(Y)
.addUse(Log.getReg(0))
- .setMIFlags(Flags);
- Register R = B.buildFExp2(F32, Mul, Flags).getReg(0);
+ .setMIFlags(CoreFlags);
- auto One = B.buildFConstant(F32, 1.0);
+ // A base that is never negative needs neither the sign fixup nor the NaN.
+ if (Helper.getValueTracking()
+ ->computeKnownFPClass(X, Flags, fcNegative, 0)
+ .signBitIsZeroOrNaN()) {
+ B.buildFExp2(Dst, Mul, CoreFlags);
+ MI.eraseFromParent();
+ return true;
+ }
+
+ Register R = B.buildFExp2(F32, Mul, CoreFlags).getReg(0);
auto YTrunc = B.buildIntrinsicTrunc(F32, Y);
auto YIsInt = B.buildFCmp(CmpInst::FCMP_OEQ, S1, YTrunc, Y);
@@ -4315,18 +4328,22 @@ bool AMDGPULegalizerInfo::legalizeFPow(MachineInstr &MI,
auto YIsOdd = B.buildAnd(
S1, YIsInt, B.buildFCmp(CmpInst::FCMP_ONE, S1, YHalfTrunc, YHalf));
- // pow(-x, odd y) = -pow(x, y).
- auto Sign = B.buildSelect(F32, YIsOdd, X, One);
+ // pow(-x, odd y) = -pow(x, y). Selecting the copysign lets even y fold it.
+ auto Neg = B.buildFCopysign(F32, R, X);
if (Flags & MachineInstr::FmNoNans) {
- B.buildFCopysign(Dst, R, Sign);
+ B.buildSelect(Dst, YIsOdd, Neg, R);
MI.eraseFromParent();
return true;
}
- R = B.buildFCopysign(F32, R, Sign).getReg(0);
+ R = B.buildSelect(F32, YIsOdd, Neg, R).getReg(0);
- // A negative finite base to a non-integral power is NaN. Not an ONE compare:
- // pow(-1, NaN) needs the NaN-true behavior of !OEQ.
- auto XNegFinite = B.buildIsFPClass(S1, X, fcNegNormal | fcNegSubnormal);
+ // A negative finite base to a non-integral power is NaN. -inf is excluded:
+ // the core already gives pow(+inf, y). So are subnormals when flushed.
+ FPClassTest NegFiniteMask = fcNegNormal;
+ if (!B.getMF().getDenormalMode(APFloat::IEEEsingle()).inputsAreZero())
+ NegFiniteMask |= fcNegSubnormal;
+ auto XNegFinite = B.buildIsFPClass(S1, X, NegFiniteMask);
+ // Not an ONE compare: pow(-1, NaN) needs the NaN-true behavior of !OEQ.
auto NegNonInt = B.buildAnd(S1, XNegFinite, B.buildNot(S1, YIsInt));
auto NaN = B.buildFConstant(F32, APFloat::getQNaN(APFloat::IEEEsingle()));
B.buildSelect(Dst, NegNonInt, NaN, R);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
index 89819fe990f5a..26caaa3ced802 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -103,7 +103,7 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
bool legalizeFEXPF64(MachineInstr &MI, MachineIRBuilder &B) const;
bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const;
- bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const;
+ bool legalizeFPow(LegalizerHelper &Helper, MachineInstr &MI) const;
bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
index 6a48a4b2a219f..c62344f055d7a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
@@ -34,13 +34,13 @@ define float @v_pow_f32(float %x, float %y) {
; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX6-NEXT: v_trunc_f32_e32 v3, v1
; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -73,13 +73,13 @@ define float @v_pow_f32(float %x, float %y) {
; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX8-NEXT: v_trunc_f32_e32 v3, v1
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -112,13 +112,13 @@ define float @v_pow_f32(float %x, float %y) {
; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX9-NEXT: v_trunc_f32_e32 v3, v1
; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX9-NEXT: v_bfrev_b32_e32 v1, -2
+; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX9-NEXT: v_and_or_b32 v1, v2, v1, v3
; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
-; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -129,30 +129,30 @@ define float @v_pow_f32(float %x, float %y) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
; GFX10-NEXT: v_trunc_f32_e32 v5, v1
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX10-NEXT: v_log_f32_e32 v2, v2
; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX10-NEXT: v_trunc_f32_e32 v6, v3
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v6, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX10-NEXT: v_exp_f32_e32 v1, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: s_and_b32 vcc_lo, s4, s5
-; GFX10-NEXT: v_cmp_class_f32_e64 s5, v0, 24
-; GFX10-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX10-NEXT: s_xor_b32 s4, s4, exec_lo
-; GFX10-NEXT: s_and_b32 s4, s5, s4
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX10-NEXT: v_exp_f32_e32 v2, v2
+; GFX10-NEXT: v_trunc_f32_e32 v6, v3
+; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v6, v3
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v1, s4
+; GFX10-NEXT: s_xor_b32 s4, vcc_lo, exec_lo
+; GFX10-NEXT: s_and_b32 s4, s6, s4
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -161,39 +161,39 @@ define float @v_pow_f32(float %x, float %y) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX11-NEXT: v_trunc_f32_e32 v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
-; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_trunc_f32_e32 v6, v3
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
-; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_and_b32 vcc_lo, s0, s1
-; GFX11-NEXT: v_cmp_class_f32_e64 s1, v0, 24
-; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX11-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT: s_and_b32 s0, s1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v6, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0
+; GFX11-NEXT: s_xor_b32 s0, vcc_lo, exec_lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s0, s2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call float @llvm.pow.f32(float %x, float %y)
@@ -229,25 +229,25 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX6-NEXT: v_mul_f32_e32 v2, 0.5, v2
; GFX6-NEXT: v_trunc_f32_e32 v10, v2
; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v5
+; GFX6-NEXT: v_and_b32_e32 v10, 0x80000000, v0
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v10
; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v2, 1.0, v0, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5]
; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 5, v0
; GFX6-NEXT: v_ldexp_f32_e64 v0, |v1|, v0
; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_and_b32_e32 v5, 0x7fffffff, v5
-; GFX6-NEXT: v_and_b32_e32 v2, 0x80000000, v2
-; GFX6-NEXT: v_or_b32_e32 v2, v5, v2
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX6-NEXT: s_xor_b64 s[10:11], vcc, exec
+; GFX6-NEXT: v_mov_b32_e32 v4, 0x7fc00000
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v5
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v3, v0
-; GFX6-NEXT: s_xor_b64 s[10:11], vcc, exec
; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v7
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
; GFX6-NEXT: v_add_f32_e32 v0, v0, v5
; GFX6-NEXT: v_exp_f32_e32 v5, v0
-; GFX6-NEXT: v_mov_b32_e32 v4, 0x7fc00000
; GFX6-NEXT: s_and_b64 s[4:5], s[8:9], s[10:11]
; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v9, vcc
@@ -257,13 +257,13 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX6-NEXT: v_mul_f32_e32 v3, 0.5, v3
; GFX6-NEXT: v_trunc_f32_e32 v5, v3
; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v3
+; GFX6-NEXT: v_and_b32_e32 v3, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; GFX6-NEXT: v_or_b32_e32 v3, v3, v5
; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v3, 1.0, v1, s[4:5]
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[4:5]
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -296,25 +296,25 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX8-NEXT: v_mul_f32_e32 v2, 0.5, v2
; GFX8-NEXT: v_trunc_f32_e32 v10, v2
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v5
+; GFX8-NEXT: v_and_b32_e32 v10, 0x80000000, v0
+; GFX8-NEXT: v_or_b32_e32 v2, v2, v10
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 1.0, v0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5]
; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 5, v0
; GFX8-NEXT: v_ldexp_f32 v0, |v1|, v0
; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_and_b32_e32 v5, 0x7fffffff, v5
-; GFX8-NEXT: v_and_b32_e32 v2, 0x80000000, v2
-; GFX8-NEXT: v_or_b32_e32 v2, v5, v2
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX8-NEXT: s_xor_b64 s[10:11], vcc, exec
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x7fc00000
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v5
; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v3, v0
-; GFX8-NEXT: s_xor_b64 s[10:11], vcc, exec
; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v7
; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
; GFX8-NEXT: v_add_f32_e32 v0, v0, v5
; GFX8-NEXT: v_exp_f32_e32 v5, v0
-; GFX8-NEXT: v_mov_b32_e32 v4, 0x7fc00000
; GFX8-NEXT: s_and_b64 s[4:5], s[8:9], s[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v9, vcc
@@ -324,13 +324,13 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v3
; GFX8-NEXT: v_trunc_f32_e32 v5, v3
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v3
+; GFX8-NEXT: v_and_b32_e32 v3, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; GFX8-NEXT: v_or_b32_e32 v3, v3, v5
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, 1.0, v1, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v3
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -363,40 +363,40 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX9-NEXT: v_mul_f32_e32 v2, 0.5, v2
; GFX9-NEXT: v_trunc_f32_e32 v10, v2
; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v2
+; GFX9-NEXT: v_bfrev_b32_e32 v2, -2
+; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v0
+; GFX9-NEXT: v_and_or_b32 v10, v5, v2, v10
; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 1.0, v0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v10, s[4:5]
; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 5, v0
; GFX9-NEXT: v_ldexp_f32 v0, |v1|, v0
; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_bfrev_b32_e32 v10, -2
-; GFX9-NEXT: v_and_b32_e32 v2, 0x80000000, v2
-; GFX9-NEXT: v_and_or_b32 v2, v5, v10, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
-; GFX9-NEXT: v_sub_f32_e32 v0, v0, v5
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v3, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[4:5]
; GFX9-NEXT: s_xor_b64 s[10:11], vcc, exec
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
-; GFX9-NEXT: v_add_f32_e32 v0, v0, v5
-; GFX9-NEXT: v_exp_f32_e32 v5, v0
; GFX9-NEXT: v_mov_b32_e32 v4, 0x7fc00000
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v6
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v3, v0
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v6
+; GFX9-NEXT: v_exp_f32_e32 v6, v0
; GFX9-NEXT: s_and_b64 s[4:5], s[8:9], s[10:11]
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v9, vcc
-; GFX9-NEXT: v_ldexp_f32 v2, v5, v2
-; GFX9-NEXT: v_trunc_f32_e32 v5, v3
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v5, v4, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX9-NEXT: v_ldexp_f32 v5, v6, v5
+; GFX9-NEXT: v_trunc_f32_e32 v6, v3
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v3
; GFX9-NEXT: v_mul_f32_e32 v3, 0.5, v3
-; GFX9-NEXT: v_trunc_f32_e32 v5, v3
-; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v3
+; GFX9-NEXT: v_trunc_f32_e32 v6, v3
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v6, v3
+; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v1
+; GFX9-NEXT: v_and_or_b32 v2, v5, v2, v3
; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v3, 1.0, v1, s[4:5]
-; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5]
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX9-NEXT: v_and_or_b32 v2, v2, v10, v3
; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -406,57 +406,57 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v1|
+; GFX10-NEXT: v_cmp_class_f32_e64 s8, v0, 24
+; GFX10-NEXT: v_trunc_f32_e32 v8, v2
; GFX10-NEXT: v_mul_f32_e32 v9, 0.5, v3
-; GFX10-NEXT: v_trunc_f32_e32 v8, v3
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s5
-; GFX10-NEXT: v_cmp_eq_f32_e64 s7, v8, v3
+; GFX10-NEXT: v_and_b32_e32 v10, 0x80000000, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 5, v5
+; GFX10-NEXT: v_cmp_class_f32_e64 s9, v1, 24
; GFX10-NEXT: v_ldexp_f32 v4, |v0|, v4
; GFX10-NEXT: v_ldexp_f32 v5, |v1|, v5
; GFX10-NEXT: v_log_f32_e32 v4, v4
; GFX10-NEXT: v_log_f32_e32 v5, v5
; GFX10-NEXT: v_sub_f32_e32 v4, v4, v6
; GFX10-NEXT: v_sub_f32_e32 v5, v5, v7
-; GFX10-NEXT: v_mul_f32_e32 v7, 0.5, v2
-; GFX10-NEXT: v_trunc_f32_e32 v6, v2
; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v2, v4
; GFX10-NEXT: v_mul_legacy_f32_e32 v5, v3, v5
-; GFX10-NEXT: v_trunc_f32_e32 v12, v7
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v6, v2
-; GFX10-NEXT: v_trunc_f32_e32 v2, v9
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v5
-; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v12, v7
-; GFX10-NEXT: v_cmp_lg_f32_e64 s8, v2, v9
-; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s4
-; GFX10-NEXT: s_and_b32 s6, s5, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s4
-; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX10-NEXT: v_add_f32_e32 v4, v4, v10
-; GFX10-NEXT: v_add_f32_e32 v5, v5, v11
-; GFX10-NEXT: s_xor_b32 s5, s5, exec_lo
-; GFX10-NEXT: s_and_b32 s4, s4, s5
-; GFX10-NEXT: v_exp_f32_e32 v2, v4
-; GFX10-NEXT: v_exp_f32_e32 v3, v5
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 1.0, v0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: s_and_b32 vcc_lo, s7, s8
-; GFX10-NEXT: v_cmp_class_f32_e64 s6, v1, 24
-; GFX10-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v4
-; GFX10-NEXT: s_xor_b32 s7, s7, exec_lo
-; GFX10-NEXT: v_ldexp_f32 v2, v2, v5
-; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v6
-; GFX10-NEXT: v_ldexp_f32 v3, v3, v7
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v2, v4
-; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
-; GFX10-NEXT: s_and_b32 s4, s6, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v2
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v6
+; GFX10-NEXT: v_add_f32_e32 v5, v5, v7
+; GFX10-NEXT: v_and_b32_e32 v7, 0x80000000, v0
+; GFX10-NEXT: v_mul_f32_e32 v6, 0.5, v2
+; GFX10-NEXT: v_trunc_f32_e32 v8, v9
+; GFX10-NEXT: v_exp_f32_e32 v0, v4
+; GFX10-NEXT: v_exp_f32_e32 v5, v5
+; GFX10-NEXT: v_trunc_f32_e32 v4, v3
+; GFX10-NEXT: v_trunc_f32_e32 v2, v6
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v8, v9
+; GFX10-NEXT: s_xor_b32 s10, vcc_lo, exec_lo
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v4, v3
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v2, v6
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v11
+; GFX10-NEXT: v_ldexp_f32 v1, v5, v1
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s5
+; GFX10-NEXT: s_and_b32 s5, s8, s10
+; GFX10-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v7
+; GFX10-NEXT: v_and_or_b32 v3, 0x7fffffff, v1, v10
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, s6
+; GFX10-NEXT: s_xor_b32 s4, s4, exec_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX10-NEXT: s_and_b32 s4, s9, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s5
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -465,69 +465,67 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v1|
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-NEXT: v_mul_f32_e32 v9, 0.5, v3
-; GFX11-NEXT: v_trunc_f32_e32 v8, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cmp_class_f32_e64 s4, v0, 24
+; GFX11-NEXT: v_trunc_f32_e32 v8, v2
+; GFX11-NEXT: v_dual_mul_f32 v9, 0.5, v3 :: v_dual_and_b32 v10, 0x80000000, v1
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, s1
; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
-; GFX11-NEXT: v_cmp_eq_f32_e64 s3, v8, v3
+; GFX11-NEXT: v_cmp_class_f32_e64 s5, v1, 24
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 5, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v5, |v1|, v5
; GFX11-NEXT: v_log_f32_e32 v5, v5
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_sub_f32 v5, v5, v7 :: v_dual_lshlrev_b32 v4, 5, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_ldexp_f32 v4, |v0|, v4
-; GFX11-NEXT: v_mul_f32_e32 v7, 0.5, v2
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v5, v3, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v4, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_trunc_f32_e32 v12, v7
-; GFX11-NEXT: v_cmp_lg_f32_e64 s2, v12, v7
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, s0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v4, v4, v6
-; GFX11-NEXT: v_trunc_f32_e32 v6, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, s0
+; GFX11-NEXT: v_dual_add_f32 v5, v5, v7 :: v_dual_mul_dx9_zero_f32 v4, v2, v4
+; GFX11-NEXT: v_and_b32_e32 v7, 0x80000000, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v4, v2, v4
-; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v6, v2
-; GFX11-NEXT: v_trunc_f32_e32 v2, v9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_exp_f32_e32 v5, v5
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
-; GFX11-NEXT: s_and_b32 s2, s1, s2
-; GFX11-NEXT: v_cmp_lg_f32_e64 s4, v2, v9
-; GFX11-NEXT: s_xor_b32 s1, s1, exec_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mul_dx9_zero_f32 v5, v3, v5 :: v_dual_add_f32 v4, v4, v10
-; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v2, v4
-; GFX11-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, 1.0, v0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
-; GFX11-NEXT: v_cmp_class_f32_e64 s2, v1, 24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_add_f32 v5, v5, v11 :: v_dual_and_b32 v4, 0x80000000, v4
-; GFX11-NEXT: s_and_b32 s0, s0, s1
-; GFX11-NEXT: v_exp_f32_e32 v3, v5
-; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_and_b32 vcc_lo, s3, s4
-; GFX11-NEXT: s_xor_b32 s3, s3, exec_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_ldexp_f32 v2, v2, v5
-; GFX11-NEXT: v_and_b32_e32 v5, 0x80000000, v6
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v2
+; GFX11-NEXT: v_trunc_f32_e32 v8, v9
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v3, v3, v7
-; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v2, v4
+; GFX11-NEXT: v_ldexp_f32 v1, v5, v1
+; GFX11-NEXT: v_add_f32_e32 v4, v4, v6
+; GFX11-NEXT: v_mul_f32_e32 v6, 0.5, v2
+; GFX11-NEXT: s_xor_b32 s6, vcc_lo, exec_lo
+; GFX11-NEXT: v_cmp_lg_f32_e64 s2, v8, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_exp_f32_e32 v0, v4
+; GFX11-NEXT: v_trunc_f32_e32 v2, v6
+; GFX11-NEXT: v_trunc_f32_e32 v4, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
-; GFX11-NEXT: s_and_b32 s0, s2, s3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v2, v6
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v4, v3
+; GFX11-NEXT: v_and_or_b32 v3, 0x7fffffff, v1, v10
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v11
+; GFX11-NEXT: s_and_b32 vcc_lo, vcc_lo, s1
+; GFX11-NEXT: s_and_b32 s1, s4, s6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX11-NEXT: s_and_b32 vcc_lo, s0, s2
+; GFX11-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX11-NEXT: s_and_b32 s0, s5, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y)
@@ -564,13 +562,13 @@ define half @v_pow_f16(half %x, half %y) {
; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX6-NEXT: v_trunc_f32_e32 v3, v1
; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -606,13 +604,13 @@ define half @v_pow_f16(half %x, half %y) {
; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX8-NEXT: v_trunc_f32_e32 v3, v1
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -648,13 +646,13 @@ define half @v_pow_f16(half %x, half %y) {
; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX9-NEXT: v_trunc_f32_e32 v3, v1
; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX9-NEXT: v_bfrev_b32_e32 v1, -2
+; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX9-NEXT: v_and_or_b32 v1, v2, v1, v3
; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
-; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -668,31 +666,31 @@ define half @v_pow_f16(half %x, half %y) {
; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v1
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
; GFX10-NEXT: v_trunc_f32_e32 v5, v4
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX10-NEXT: v_log_f32_e32 v2, v2
; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_mov_b32_e32 v3, 0.5
; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v4, v2
-; GFX10-NEXT: v_fma_mix_f32 v1, v1, v3, neg(0) op_sel_hi:[1,0,0]
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX10-NEXT: v_trunc_f32_e32 v6, v1
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v6, v1
; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_exp_f32_e32 v1, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: s_and_b32 vcc_lo, s4, s5
-; GFX10-NEXT: v_cmp_class_f32_e64 s5, v0, 24
-; GFX10-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX10-NEXT: s_xor_b32 s4, s4, exec_lo
-; GFX10-NEXT: s_and_b32 s4, s5, s4
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_mov_b32_e32 v3, 0.5
+; GFX10-NEXT: v_exp_f32_e32 v2, v2
+; GFX10-NEXT: v_fma_mix_f32 v1, v1, v3, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
+; GFX10-NEXT: v_trunc_f32_e32 v6, v1
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX10-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v6, v1
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v3
+; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v1, s4
+; GFX10-NEXT: s_xor_b32 s4, vcc_lo, exec_lo
+; GFX10-NEXT: s_and_b32 s4, s6, s4
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -705,40 +703,41 @@ define half @v_pow_f16(half %x, half %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v3
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, s1
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v6, v3
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -750,41 +749,43 @@ define half @v_pow_f16(half %x, half %y) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v2, v2
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mov_b32 v3, 0.5
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v4, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v3, neg(0) op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v6, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, s1
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mov_b32 v3, 0.5
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v3, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v1
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v6, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v3
+; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%pow = call half @llvm.pow.f16(half %x, half %y)
@@ -823,10 +824,13 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v5
; GFX6-NEXT: v_trunc_f32_e32 v10, v5
; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX6-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4
+; GFX6-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX6-NEXT: v_or_b32_e32 v5, v5, v10
; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_xor_b64 s[8:9], vcc, exec
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX6-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5]
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -834,10 +838,8 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_log_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
-; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX6-NEXT: v_or_b32_e32 v4, v4, v5
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5
; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
@@ -845,22 +847,21 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_add_f32_e32 v2, v2, v5
; GFX6-NEXT: v_exp_f32_e32 v2, v2
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5
; GFX6-NEXT: v_trunc_f32_e32 v5, v1
; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX6-NEXT: v_trunc_f32_e32 v5, v1
-; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v5
; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
@@ -902,19 +903,21 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v5
; GFX8-NEXT: v_trunc_f32_e32 v10, v5
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX8-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4
+; GFX8-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v10
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX8-NEXT: s_xor_b64 s[8:9], vcc, exec
; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX8-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX8-NEXT: v_log_f32_e32 v2, v2
-; GFX8-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX8-NEXT: v_or_b32_e32 v4, v4, v5
; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
; GFX8-NEXT: v_sub_f32_e32 v2, v2, v5
; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
@@ -922,22 +925,20 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX8-NEXT: v_add_f32_e32 v2, v2, v5
; GFX8-NEXT: v_exp_f32_e32 v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
-; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
; GFX8-NEXT: v_trunc_f32_e32 v5, v1
; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX8-NEXT: v_trunc_f32_e32 v5, v1
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v5
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
@@ -978,44 +979,44 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v5
; GFX9-NEXT: v_trunc_f32_e32 v10, v5
; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX9-NEXT: v_bfrev_b32_e32 v5, -2
+; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX9-NEXT: v_and_or_b32 v10, v4, v5, v10
; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: s_xor_b64 s[8:9], vcc, exec
; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[4:5]
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX9-NEXT: v_log_f32_e32 v2, v2
-; GFX9-NEXT: v_bfrev_b32_e32 v10, -2
-; GFX9-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX9-NEXT: v_and_or_b32 v4, v4, v10, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
-; GFX9-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v6
; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v6
; GFX9-NEXT: v_exp_f32_e32 v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
-; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
-; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
-; GFX9-NEXT: v_trunc_f32_e32 v5, v1
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
-; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
-; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX9-NEXT: v_trunc_f32_e32 v6, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v6, v1
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v6, v1
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v0
+; GFX9-NEXT: v_and_or_b32 v1, v2, v5, v1
; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX9-NEXT: v_and_or_b32 v1, v2, v10, v1
; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
-; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT: v_pack_b32_f16 v0, v4, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1025,10 +1026,12 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e32 v8, v1
-; GFX10-NEXT: v_mov_b32_e32 v7, 0.5
+; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v1
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
+; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24
+; GFX10-NEXT: v_and_b32_e32 v14, 0x80000000, v0
+; GFX10-NEXT: v_cmp_class_f32_e64 s9, v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s4
@@ -1042,45 +1045,43 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: v_sub_f32_e32 v3, v3, v5
; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_sub_f32_e32 v4, v4, v6
-; GFX10-NEXT: v_fma_mix_f32 v6, v1, v7, neg(0) op_sel_hi:[1,0,0]
-; GFX10-NEXT: v_fma_mix_f32 v1, v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v8, v3
-; GFX10-NEXT: v_trunc_f32_e32 v7, v8
+; GFX10-NEXT: v_mov_b32_e32 v6, 0.5
+; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v7, v3
; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
-; GFX10-NEXT: v_trunc_f32_e32 v9, v6
-; GFX10-NEXT: v_trunc_f32_e32 v12, v5
+; GFX10-NEXT: v_fma_mix_f32 v10, v1, v6, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX10-NEXT: v_trunc_f32_e32 v13, v1
+; GFX10-NEXT: v_trunc_f32_e32 v6, v7
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v7, v8
-; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v9, v6
-; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f32_e64 s7, v12, v5
-; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s4
-; GFX10-NEXT: v_cmp_lg_f32_e64 s8, v13, v1
-; GFX10-NEXT: s_and_b32 s6, s5, s6
-; GFX10-NEXT: v_add_f32_e32 v3, v3, v10
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v4, v4, v11
-; GFX10-NEXT: s_and_b32 vcc_lo, s7, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s4
-; GFX10-NEXT: v_exp_f32_e32 v1, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_exp_f32_e32 v3, v4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s6
-; GFX10-NEXT: v_cmp_class_f32_e64 s4, v2, 24
-; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
-; GFX10-NEXT: s_xor_b32 s5, s5, exec_lo
-; GFX10-NEXT: s_xor_b32 s7, s7, exec_lo
-; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v4
-; GFX10-NEXT: s_and_b32 s4, s4, s5
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
-; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v6
-; GFX10-NEXT: v_ldexp_f32 v3, v3, v7
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
-; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
-; GFX10-NEXT: s_and_b32 s4, s6, s7
+; GFX10-NEXT: v_trunc_f32_e32 v12, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v7
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v8
+; GFX10-NEXT: v_trunc_f32_e32 v8, v10
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX10-NEXT: v_and_b32_e32 v9, 0x80000000, v2
+; GFX10-NEXT: v_trunc_f32_e32 v2, v5
+; GFX10-NEXT: v_exp_f32_e32 v3, v3
+; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v8, v10
+; GFX10-NEXT: v_exp_f32_e32 v4, v4
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v12, v1
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v2, v5
+; GFX10-NEXT: s_xor_b32 s10, vcc_lo, exec_lo
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: s_xor_b32 s4, s5, exec_lo
+; GFX10-NEXT: v_ldexp_f32 v0, v3, v11
+; GFX10-NEXT: s_and_b32 s4, s9, s4
+; GFX10-NEXT: v_ldexp_f32 v3, v4, v13
+; GFX10-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v9
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v14
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
+; GFX10-NEXT: s_and_b32 s5, s8, s10
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s5
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
@@ -1097,151 +1098,155 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v1
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, 0.5, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: v_dual_mul_f32 v9, 0.5, v1 :: v_dual_and_b32 v10, 0x80000000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, v8, v1
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v6, 0.5, v7
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v1, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v12, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v11
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v5, v7
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_mul_dx9_zero_f32 v3, v7, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0x80000000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, s2
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s4, v5, v9
-; GFX11-TRUE16-NEXT: s_xor_b32 s1, s1, exec_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s3, s4
-; GFX11-TRUE16-NEXT: s_xor_b32 s3, s3, exec_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, 1.0, v0 :: v_dual_add_f32 v3, v3, v10
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v3
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s2
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v9
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0x80000000, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, v7
-; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v4, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, 0.5, v7
+; GFX11-TRUE16-NEXT: s_xor_b32 s6, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v8, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v3
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v3, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v7, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v3, v1
+; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v0, v10
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, v11
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, s2
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_v2f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0.5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v8, v1
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, 0.5
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0x80000000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v9, v1, v8, neg(0) op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v0|, v3
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_dual_sub_f32 v3, v3, v5 :: v_dual_lshlrev_b32 v4, 5, v4
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v2|, v4
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v1, v6, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v8
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v8, v3
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v6, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v4, v9
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v5
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v7, v4
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s2, v9, v5
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v7
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v6, v3
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v1
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v12, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v7
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, s0
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v8, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0x80000000, v0
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0xc2fc0000, v4
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s0, s2
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, v4, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 1.0, v0, s2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v5, v7
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, s1
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x80000000, v4
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s3
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, 1.0, v2, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s3, v2, 24
-; GFX11-FAKE16-NEXT: s_xor_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s0
-; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v3, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0x80000000, v7
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v5
+; GFX11-FAKE16-NEXT: s_xor_b32 s4, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v7, v5
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v1, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x7fc00000, s0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s3, s2
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v10
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
+; GFX11-FAKE16-NEXT: s_xor_b32 s1, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_or_b32 v9, 0x7fffffff, v3, v11
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, v9, s0
+; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v4, v8
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, s4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1287,10 +1292,13 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v5
; GFX6-NEXT: v_trunc_f32_e32 v10, v5
; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX6-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4
+; GFX6-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX6-NEXT: v_or_b32_e32 v5, v5, v10
; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_xor_b64 s[8:9], vcc, exec
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX6-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5]
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -1298,10 +1306,8 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_log_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
-; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX6-NEXT: v_or_b32_e32 v4, v4, v5
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5
; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
@@ -1309,22 +1315,21 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_add_f32_e32 v2, v2, v5
; GFX6-NEXT: v_exp_f32_e32 v2, v2
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5
; GFX6-NEXT: v_trunc_f32_e32 v5, v1
; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX6-NEXT: v_trunc_f32_e32 v5, v1
-; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v5
; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
@@ -1367,19 +1372,21 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v5
; GFX8-NEXT: v_trunc_f32_e32 v10, v5
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX8-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4
+; GFX8-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v10
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX8-NEXT: s_xor_b64 s[8:9], vcc, exec
; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX8-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX8-NEXT: v_log_f32_e32 v2, v2
-; GFX8-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX8-NEXT: v_or_b32_e32 v4, v4, v5
; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
; GFX8-NEXT: v_sub_f32_e32 v2, v2, v5
; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
@@ -1387,22 +1394,20 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX8-NEXT: v_add_f32_e32 v2, v2, v5
; GFX8-NEXT: v_exp_f32_e32 v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
-; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
; GFX8-NEXT: v_trunc_f32_e32 v5, v1
; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX8-NEXT: v_trunc_f32_e32 v5, v1
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v5
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
@@ -1444,44 +1449,44 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v5
; GFX9-NEXT: v_trunc_f32_e32 v10, v5
; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX9-NEXT: v_bfrev_b32_e32 v5, -2
+; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX9-NEXT: v_and_or_b32 v10, v4, v5, v10
; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: s_xor_b64 s[8:9], vcc, exec
; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[4:5]
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX9-NEXT: v_log_f32_e32 v2, v2
-; GFX9-NEXT: v_bfrev_b32_e32 v10, -2
-; GFX9-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX9-NEXT: v_and_or_b32 v4, v4, v10, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
-; GFX9-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v6
; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v6
; GFX9-NEXT: v_exp_f32_e32 v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
-; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
-; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
-; GFX9-NEXT: v_trunc_f32_e32 v5, v1
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
-; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
-; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX9-NEXT: v_trunc_f32_e32 v6, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v6, v1
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v6, v1
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v0
+; GFX9-NEXT: v_and_or_b32 v1, v2, v5, v1
; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX9-NEXT: v_and_or_b32 v1, v2, v10, v1
; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
-; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT: v_pack_b32_f16 v0, v4, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1490,12 +1495,13 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX10-NEXT: v_cvt_f32_f16_e32 v8, v1
-; GFX10-NEXT: v_mov_b32_e32 v7, 0.5
+; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v1
; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
+; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24
+; GFX10-NEXT: v_cmp_class_f32_e64 s9, v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s4
@@ -1509,49 +1515,48 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: v_sub_f32_e32 v3, v3, v5
; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_sub_f32_e32 v4, v4, v6
-; GFX10-NEXT: v_fma_mix_f32 v6, v1, v7, neg(0) op_sel_hi:[1,0,0]
-; GFX10-NEXT: v_fma_mix_f32 v1, v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v8, v3
-; GFX10-NEXT: v_trunc_f32_e32 v7, v8
+; GFX10-NEXT: v_mov_b32_e32 v6, 0.5
+; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v7, v3
; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
-; GFX10-NEXT: v_trunc_f32_e32 v9, v6
-; GFX10-NEXT: v_trunc_f32_e32 v12, v5
+; GFX10-NEXT: v_fma_mix_f32 v10, v1, v6, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX10-NEXT: v_trunc_f32_e32 v13, v1
+; GFX10-NEXT: v_trunc_f32_e32 v6, v7
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v7, v8
-; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v9, v6
-; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f32_e64 s7, v12, v5
-; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s4
-; GFX10-NEXT: v_cmp_lg_f32_e64 s8, v13, v1
-; GFX10-NEXT: s_and_b32 s6, s5, s6
-; GFX10-NEXT: v_add_f32_e32 v3, v3, v10
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v4, v4, v11
-; GFX10-NEXT: s_and_b32 vcc_lo, s7, s8
+; GFX10-NEXT: v_trunc_f32_e32 v11, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v6, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s4
-; GFX10-NEXT: v_exp_f32_e32 v1, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_exp_f32_e32 v3, v4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s6
-; GFX10-NEXT: v_cmp_class_f32_e64 s4, v2, 24
-; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
-; GFX10-NEXT: s_xor_b32 s5, s5, exec_lo
-; GFX10-NEXT: s_xor_b32 s7, s7, exec_lo
-; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v4
-; GFX10-NEXT: s_and_b32 s4, s4, s5
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
-; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v6
-; GFX10-NEXT: v_ldexp_f32 v3, v3, v7
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
-; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v8
+; GFX10-NEXT: v_trunc_f32_e32 v8, v10
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX10-NEXT: v_trunc_f32_e32 v9, v5
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v11, v1
+; GFX10-NEXT: v_exp_f32_e32 v3, v3
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v8, v10
+; GFX10-NEXT: v_exp_f32_e32 v4, v4
+; GFX10-NEXT: v_and_b32_e32 v8, 0x80000000, v2
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v9, v5
+; GFX10-NEXT: s_xor_b32 s10, s5, exec_lo
+; GFX10-NEXT: s_and_b32 vcc_lo, s5, vcc_lo
+; GFX10-NEXT: s_and_b32 s5, s8, s10
+; GFX10-NEXT: v_ldexp_f32 v2, v3, v6
+; GFX10-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX10-NEXT: v_ldexp_f32 v4, v4, v7
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v8
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v4, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, s6
+; GFX10-NEXT: s_xor_b32 s4, s4, exec_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
+; GFX10-NEXT: s_and_b32 s4, s9, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s5
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
-; GFX10-NEXT: s_and_b32 s4, s6, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
-; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX10-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_lhs:
@@ -1563,72 +1568,73 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, 0.5, v1
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, v8, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v8, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0x80000000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX11-TRUE16-NEXT: s_xor_b32 s6, s1, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v6, 0.5, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v1, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v12, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v5, v7
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_mul_dx9_zero_f32 v3, v7, v3
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, s2
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s4, v5, v9
-; GFX11-TRUE16-NEXT: s_xor_b32 s1, s1, exec_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s3, s4
-; GFX11-TRUE16-NEXT: s_xor_b32 s3, s3, exec_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, 1.0, v0 :: v_dual_add_f32 v3, v3, v10
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v3
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s2
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0x80000000, v0
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v1, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, 0.5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v4, v2
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v1, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v6
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v7, v5
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0x80000000, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, v7
-; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, v10
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v3, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v3, v0, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, v1, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1640,79 +1646,84 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v8, v1
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, 0.5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0.5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v9, v1, v8, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v7
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v4, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v0|, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_dual_sub_f32 v3, v3, v5 :: v_dual_lshlrev_b32 v4, 5, v4
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v2|, v4
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v1, v6, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v8
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v8, v3
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v6, v3
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v6, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v4, v9
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v5
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v10
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v7, v4
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s2, v9, v5
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v11, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v7
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0x80000000, v2
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0xc2fc0000, v4
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s0, s2
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, v4, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 1.0, v0, s2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v5, v7
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, s1
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x80000000, v4
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s3
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, 1.0, v2, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s3, v2, 24
-; GFX11-FAKE16-NEXT: s_xor_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s0
-; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v3, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0x80000000, v7
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v1, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x7fc00000, s0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s3, s2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v8, v9
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0x80000000, v0
+; GFX11-FAKE16-NEXT: s_xor_b32 s4, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v7
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v8, v5
+; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v10
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
+; GFX11-FAKE16-NEXT: s_xor_b32 s1, s2, exec_lo
+; GFX11-FAKE16-NEXT: v_and_or_b32 v6, 0x7fffffff, v3, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, v6, s0
+; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v4, v9
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, s4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1759,10 +1770,13 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v5
; GFX6-NEXT: v_trunc_f32_e32 v10, v5
; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX6-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4
+; GFX6-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX6-NEXT: v_or_b32_e32 v5, v5, v10
; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_xor_b64 s[8:9], vcc, exec
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX6-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5]
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -1770,10 +1784,8 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_log_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
-; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX6-NEXT: v_or_b32_e32 v4, v4, v5
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5
; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
@@ -1781,22 +1793,21 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_add_f32_e32 v2, v2, v5
; GFX6-NEXT: v_exp_f32_e32 v2, v2
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5
; GFX6-NEXT: v_trunc_f32_e32 v5, v1
; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX6-NEXT: v_trunc_f32_e32 v5, v1
-; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v5
; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
@@ -1838,20 +1849,21 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v5
; GFX8-NEXT: v_trunc_f32_e32 v10, v5
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX8-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4
+; GFX8-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v10
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX8-NEXT: s_xor_b64 s[8:9], vcc, exec
; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX8-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX8-NEXT: v_log_f32_e32 v2, v2
; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX8-NEXT: v_or_b32_e32 v4, v4, v5
; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX8-NEXT: v_sub_f32_e32 v2, v2, v5
; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
@@ -1859,22 +1871,21 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX8-NEXT: v_add_f32_e32 v2, v2, v5
; GFX8-NEXT: v_exp_f32_e32 v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
; GFX8-NEXT: v_trunc_f32_e32 v5, v1
; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX8-NEXT: v_trunc_f32_e32 v5, v1
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v5
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
@@ -1915,42 +1926,42 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v5
; GFX9-NEXT: v_trunc_f32_e32 v10, v5
; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX9-NEXT: v_bfrev_b32_e32 v5, -2
+; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX9-NEXT: v_and_or_b32 v10, v4, v5, v10
; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: s_xor_b64 s[8:9], vcc, exec
; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[4:5]
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX9-NEXT: v_log_f32_e32 v2, v2
; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_bfrev_b32_e32 v10, -2
-; GFX9-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX9-NEXT: v_and_or_b32 v4, v4, v10, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
-; GFX9-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v6
; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v6
; GFX9-NEXT: v_exp_f32_e32 v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v9, vcc
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
-; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
-; GFX9-NEXT: v_trunc_f32_e32 v5, v1
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
-; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GFX9-NEXT: v_trunc_f32_e32 v5, v1
; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
-; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX9-NEXT: v_trunc_f32_e32 v6, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v6, v1
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v6, v1
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v0
+; GFX9-NEXT: v_and_or_b32 v1, v2, v5, v1
; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX9-NEXT: v_and_or_b32 v1, v2, v10, v1
; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
@@ -1964,11 +1975,11 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
-; GFX10-NEXT: v_mov_b32_e32 v8, 0.5
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
-; GFX10-NEXT: v_cvt_f32_f16_e32 v9, v5
-; GFX10-NEXT: v_fma_mix_f32 v1, -v1, v8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cvt_f32_f16_e32 v8, v5
+; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24
+; GFX10-NEXT: v_cmp_class_f32_e64 s9, v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
@@ -1982,44 +1993,44 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
; GFX10-NEXT: v_cvt_f32_f16_sdwa v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_sub_f32_e32 v4, v4, v7
-; GFX10-NEXT: v_fma_mix_f32 v5, v5, v8, neg(0) op_sel_hi:[1,0,0]
-; GFX10-NEXT: v_trunc_f32_e32 v8, v9
-; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v9, v3
-; GFX10-NEXT: v_trunc_f32_e32 v7, v1
-; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
-; GFX10-NEXT: v_trunc_f32_e32 v12, v5
+; GFX10-NEXT: v_mov_b32_e32 v7, 0.5
+; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v8, v3
; GFX10-NEXT: v_trunc_f32_e32 v13, v6
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v8, v9
+; GFX10-NEXT: v_and_b32_e32 v7, 0x80000000, v2
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
-; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v12, v5
-; GFX10-NEXT: v_cmp_lg_f32_e64 s7, v7, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f32_e64 s8, v13, v6
-; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s4
-; GFX10-NEXT: s_and_b32 s6, s5, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v3, v3, v10
-; GFX10-NEXT: s_and_b32 vcc_lo, s8, s7
-; GFX10-NEXT: v_add_f32_e32 v4, v4, v11
-; GFX10-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s4
-; GFX10-NEXT: v_exp_f32_e32 v1, v3
-; GFX10-NEXT: v_cmp_class_f32_e64 s4, v2, 24
-; GFX10-NEXT: v_exp_f32_e32 v3, v4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s6
-; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
-; GFX10-NEXT: s_xor_b32 s5, s5, exec_lo
-; GFX10-NEXT: s_xor_b32 s7, s8, exec_lo
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v13, v6
+; GFX10-NEXT: v_trunc_f32_e32 v12, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v12, v5
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v9
+; GFX10-NEXT: v_and_b32_e32 v9, 0x80000000, v0
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_trunc_f32_e32 v10, v8
+; GFX10-NEXT: v_exp_f32_e32 v2, v3
+; GFX10-NEXT: v_trunc_f32_e32 v3, v1
+; GFX10-NEXT: v_exp_f32_e32 v4, v4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v10, v8
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v3, v1
+; GFX10-NEXT: s_xor_b32 s10, s4, exec_lo
+; GFX10-NEXT: v_ldexp_f32 v0, v2, v0
; GFX10-NEXT: s_and_b32 s4, s4, s5
-; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v4
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
-; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v6
-; GFX10-NEXT: v_ldexp_f32 v3, v3, v7
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
-; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
-; GFX10-NEXT: s_and_b32 s4, s6, s7
+; GFX10-NEXT: v_ldexp_f32 v1, v4, v11
+; GFX10-NEXT: s_and_b32 vcc_lo, s6, vcc_lo
+; GFX10-NEXT: s_and_b32 s5, s8, s10
+; GFX10-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v7
+; GFX10-NEXT: v_and_or_b32 v3, 0x7fffffff, v1, v9
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4
+; GFX10-NEXT: s_xor_b32 s4, s6, exec_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX10-NEXT: s_and_b32 s4, s9, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s5
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
@@ -2038,159 +2049,157 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_mul_f32 v9, 0.5, v1 :: v_dual_lshlrev_b32 v4, 5, v4
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, v8, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, 0.5, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v6, 0.5, v7
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v1, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v12, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, s0
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v5, v7
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, s2
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s4, v5, v9
-; GFX11-TRUE16-NEXT: s_xor_b32 s1, s1, exec_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s3, s4
-; GFX11-TRUE16-NEXT: s_xor_b32 s3, s3, exec_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, 1.0, v0 :: v_dual_add_f32 v3, v3, v10
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v3
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s2
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0x80000000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v4, v6
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, 0.5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v6, v1
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v0, v3
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v3, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v7
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v3, v5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v10
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0x80000000, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, v7
-; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v0, v9
+; GFX11-TRUE16-NEXT: s_xor_b32 s6, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v3, v5
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v7, v10
+; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v2, v4
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, v8
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, s2
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_rhs:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, 0.5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v5
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v9, v5
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v7
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42000000, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v1
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s2, v11, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42000000, s1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v7, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v0|, v4
; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_dual_sub_f32 v4, v4, v10 :: v_dual_lshlrev_b32 v3, 5, v3
+; GFX11-FAKE16-NEXT: v_dual_sub_f32 v4, v4, v8 :: v_dual_lshlrev_b32 v3, 5, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v6
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v8
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v8, v9
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v1, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0xc2fc0000, v4
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s0, s2
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 1.0, v0, s2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v1, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, s1
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v9, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v6
+; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v7, v3 :: v_dual_mul_dx9_zero_f32 v4, v6, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v4
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s3
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s3, v2, 24
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, 1.0, v2, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v10
-; GFX11-FAKE16-NEXT: s_xor_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v1, v6
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v11, v7
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v8
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0.5
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v7, v6
+; GFX11-FAKE16-NEXT: s_xor_b32 s4, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v8
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v9, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v9, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0x80000000, v2
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v1
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v1
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x80000000, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v3, v5
-; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x7fc00000, s0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s3, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v10
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, s0
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v12, v5
+; GFX11-FAKE16-NEXT: v_and_or_b32 v5, 0x7fffffff, v3, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v10
+; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0x80000000, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, v5, s0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
+; GFX11-FAKE16-NEXT: s_xor_b32 s1, s2, exec_lo
+; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v4, v13
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, s4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%y.fneg = fneg <2 x half> %y
@@ -2232,10 +2241,13 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v5
; GFX6-NEXT: v_trunc_f32_e32 v10, v5
; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX6-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4
+; GFX6-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX6-NEXT: v_or_b32_e32 v5, v5, v10
; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_xor_b64 s[8:9], vcc, exec
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX6-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5]
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -2243,10 +2255,8 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_log_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
-; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX6-NEXT: v_or_b32_e32 v4, v4, v5
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5
; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
@@ -2254,22 +2264,21 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_add_f32_e32 v2, v2, v5
; GFX6-NEXT: v_exp_f32_e32 v2, v2
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5
; GFX6-NEXT: v_trunc_f32_e32 v5, v1
; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX6-NEXT: v_trunc_f32_e32 v5, v1
-; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v5
; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
@@ -2312,20 +2321,21 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v5
; GFX8-NEXT: v_trunc_f32_e32 v10, v5
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX8-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4
+; GFX8-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v10
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX8-NEXT: s_xor_b64 s[8:9], vcc, exec
; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX8-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX8-NEXT: v_log_f32_e32 v2, v2
; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_and_b32_e32 v4, 0x7fffffff, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX8-NEXT: v_or_b32_e32 v4, v4, v5
; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX8-NEXT: v_sub_f32_e32 v2, v2, v5
; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
@@ -2333,22 +2343,21 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX8-NEXT: v_add_f32_e32 v2, v2, v5
; GFX8-NEXT: v_exp_f32_e32 v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
; GFX8-NEXT: v_trunc_f32_e32 v5, v1
; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX8-NEXT: v_trunc_f32_e32 v5, v1
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v5
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
@@ -2390,42 +2399,42 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v5
; GFX9-NEXT: v_trunc_f32_e32 v10, v5
; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5
+; GFX9-NEXT: v_bfrev_b32_e32 v5, -2
+; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX9-NEXT: v_and_or_b32 v10, v4, v5, v10
; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: s_xor_b64 s[8:9], vcc, exec
; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 1.0, v2, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[4:5]
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX9-NEXT: v_log_f32_e32 v2, v2
; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_bfrev_b32_e32 v10, -2
-; GFX9-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX9-NEXT: v_and_or_b32 v4, v4, v10, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
-; GFX9-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: v_sub_f32_e32 v2, v2, v6
; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v6
; GFX9-NEXT: v_exp_f32_e32 v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v9, vcc
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
-; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
-; GFX9-NEXT: v_trunc_f32_e32 v5, v1
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1
-; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GFX9-NEXT: v_trunc_f32_e32 v5, v1
; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5]
-; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX9-NEXT: v_trunc_f32_e32 v6, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v6, v1
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v6, v1
+; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v0
+; GFX9-NEXT: v_and_or_b32 v1, v2, v5, v1
; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX9-NEXT: v_and_or_b32 v1, v2, v10, v1
; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
@@ -2438,13 +2447,14 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX10-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
-; GFX10-NEXT: v_mov_b32_e32 v8, 0.5
; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e32 v9, v5
-; GFX10-NEXT: v_fma_mix_f32 v1, -v1, v8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cvt_f32_f16_e32 v8, v5
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
+; GFX10-NEXT: v_and_b32_e32 v11, 0x80000000, v2
+; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24
+; GFX10-NEXT: v_cmp_class_f32_e64 s9, v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
@@ -2458,48 +2468,47 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
; GFX10-NEXT: v_cvt_f32_f16_sdwa v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_sub_f32_e32 v4, v4, v7
-; GFX10-NEXT: v_fma_mix_f32 v5, v5, v8, neg(0) op_sel_hi:[1,0,0]
-; GFX10-NEXT: v_trunc_f32_e32 v8, v9
-; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v9, v3
-; GFX10-NEXT: v_trunc_f32_e32 v7, v1
+; GFX10-NEXT: v_mov_b32_e32 v7, 0.5
+; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v8, v3
+; GFX10-NEXT: v_trunc_f32_e32 v12, v6
; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
-; GFX10-NEXT: v_trunc_f32_e32 v12, v5
-; GFX10-NEXT: v_trunc_f32_e32 v13, v6
+; GFX10-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v8, v9
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v12, v6
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
-; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v12, v5
-; GFX10-NEXT: v_cmp_lg_f32_e64 s7, v7, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f32_e64 s8, v13, v6
-; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s4
-; GFX10-NEXT: s_and_b32 s6, s5, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v3, v3, v10
-; GFX10-NEXT: s_and_b32 vcc_lo, s8, s7
-; GFX10-NEXT: v_add_f32_e32 v4, v4, v11
-; GFX10-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s4
-; GFX10-NEXT: v_exp_f32_e32 v1, v3
-; GFX10-NEXT: v_cmp_class_f32_e64 s4, v2, 24
-; GFX10-NEXT: v_exp_f32_e32 v3, v4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s6
-; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
-; GFX10-NEXT: s_xor_b32 s5, s5, exec_lo
-; GFX10-NEXT: s_xor_b32 s7, s8, exec_lo
+; GFX10-NEXT: v_trunc_f32_e32 v7, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v1
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v9
+; GFX10-NEXT: v_trunc_f32_e32 v9, v8
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v10
+; GFX10-NEXT: v_trunc_f32_e32 v10, v5
+; GFX10-NEXT: v_and_b32_e32 v1, 0x80000000, v0
+; GFX10-NEXT: v_exp_f32_e32 v3, v3
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v9, v8
+; GFX10-NEXT: v_exp_f32_e32 v4, v4
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v10, v5
+; GFX10-NEXT: s_and_b32 vcc_lo, s6, vcc_lo
+; GFX10-NEXT: s_xor_b32 s10, s4, exec_lo
; GFX10-NEXT: s_and_b32 s4, s4, s5
-; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v4
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
-; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v6
-; GFX10-NEXT: v_ldexp_f32 v3, v3, v7
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
-; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
+; GFX10-NEXT: s_and_b32 s5, s8, s10
+; GFX10-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX10-NEXT: v_ldexp_f32 v0, v4, v13
+; GFX10-NEXT: v_and_or_b32 v3, 0x7fffffff, v2, v11
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v3, s4
+; GFX10-NEXT: s_xor_b32 s4, s6, exec_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX10-NEXT: s_and_b32 s4, s9, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s5
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
-; GFX10-NEXT: s_and_b32 s4, s6, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
-; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX10-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_lhs_rhs:
@@ -2516,74 +2525,72 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v1
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, 0.5, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: v_dual_mul_f32 v9, 0.5, v1 :: v_dual_and_b32 v10, 0x80000000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, v8, v1
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v6, 0.5, v7
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v1, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v12, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v11
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v5, v7
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_mul_dx9_zero_f32 v3, v7, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0x80000000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, s2
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s4, v5, v9
-; GFX11-TRUE16-NEXT: s_xor_b32 s1, s1, exec_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s3, s4
-; GFX11-TRUE16-NEXT: s_xor_b32 s3, s3, exec_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, 1.0, v0 :: v_dual_add_f32 v3, v3, v10
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v3
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s2
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x80000000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v9
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0x80000000, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, v7
-; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v4, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, 0.5, v7
+; GFX11-TRUE16-NEXT: s_xor_b32 s6, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v8, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v3
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v3, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v7, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v3, v1
+; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v0, v10
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, v11
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, s2
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_lhs_rhs:
@@ -2591,86 +2598,86 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, 0.5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v5
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v9, v5
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v5
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0x80000000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v1
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s2, v11, v5
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42000000, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v7, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42000000, s1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v0|, v4
; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_dual_sub_f32 v4, v4, v10 :: v_dual_lshlrev_b32 v3, 5, v3
+; GFX11-FAKE16-NEXT: v_dual_sub_f32 v4, v4, v8 :: v_dual_lshlrev_b32 v3, 5, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v6
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v8
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v8, v9
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v1, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0xc2fc0000, v4
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s0, s2
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 1.0, v0, s2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v1, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, s1
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v9, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0x80000000, v5
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v6
+; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v7, v3 :: v_dual_mul_dx9_zero_f32 v4, v6, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v4
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s3
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s3, v2, 24
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, 1.0, v2, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v10
-; GFX11-FAKE16-NEXT: s_xor_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v1, v6
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v8
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0.5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x80000000, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v3, v5
-; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x7fc00000, s0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s3, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v9, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v9, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v7
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v5
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v10
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v11, v5
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v6
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v8, v1
+; GFX11-FAKE16-NEXT: s_xor_b32 s4, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: v_and_or_b32 v10, 0x7fffffff, v3, v12
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v7
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v5, v6
+; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, v10, s0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0x80000000, v0
+; GFX11-FAKE16-NEXT: s_xor_b32 s1, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, s4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v4, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%x.fneg = fneg <2 x half> %x
@@ -2693,36 +2700,21 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
-; GFX6-NEXT: v_log_f32_e32 v2, v2
-; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000
-; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
-; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
-; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX6-NEXT: v_exp_f32_e32 v2, v2
-; GFX6-NEXT: v_not_b32_e32 v3, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
-; GFX6-NEXT: v_trunc_f32_e32 v3, v1
-; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
-; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GFX6-NEXT: v_trunc_f32_e32 v3, v1
-; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
-; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, |v0|, s[4:5]
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
-; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], |v0|, 24
-; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
-; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fabs_lhs:
@@ -2732,36 +2724,21 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX8-NEXT: v_log_f32_e32 v2, v2
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
-; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
-; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX8-NEXT: v_exp_f32_e32 v2, v2
-; GFX8-NEXT: v_not_b32_e32 v3, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX8-NEXT: v_trunc_f32_e32 v3, v1
-; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
-; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GFX8-NEXT: v_trunc_f32_e32 v3, v1
-; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
-; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, |v0|, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
-; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], |v0|, 24
-; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
-; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fabs_lhs:
@@ -2771,108 +2748,65 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX9-NEXT: v_log_f32_e32 v2, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000
-; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX9-NEXT: v_exp_f32_e32 v2, v2
-; GFX9-NEXT: v_not_b32_e32 v3, 63
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX9-NEXT: v_trunc_f32_e32 v3, v1
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
-; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GFX9-NEXT: v_trunc_f32_e32 v3, v1
-; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, |v0|, s[4:5]
-; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
-; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
-; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], |v0|, 24
-; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
-; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_lhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
-; GFX10-NEXT: v_trunc_f32_e32 v5, v1
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX10-NEXT: v_log_f32_e32 v2, v2
-; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
-; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX10-NEXT: v_trunc_f32_e32 v6, v3
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v6, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: s_and_b32 s5, s4, s5
-; GFX10-NEXT: s_xor_b32 s4, s4, exec_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 1.0, |v0|, s5
-; GFX10-NEXT: v_cmp_class_f32_e64 s5, |v0|, 24
-; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX10-NEXT: s_and_b32 s4, s5, s4
-; GFX10-NEXT: v_exp_f32_e32 v1, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
+; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_lhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-NEXT: v_trunc_f32_e32 v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
-; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_log_f32_e32 v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_trunc_f32_e32 v6, v3
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
-; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: s_and_b32 s1, s0, s1
-; GFX11-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 1.0, |v0|, s1
-; GFX11-NEXT: v_cmp_class_f32_e64 s1, |v0|, 24
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-NEXT: s_and_b32 s0, s1, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_exp_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
%pow = call float @llvm.pow.f32(float %fabs.x, float %y)
@@ -2908,12 +2842,12 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX6-NEXT: v_mul_f32_e64 v1, |v1|, 0.5
; GFX6-NEXT: v_trunc_f32_e32 v3, v1
; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
; GFX6-NEXT: s_xor_b64 s[4:5], s[6:7], exec
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -2947,12 +2881,12 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX8-NEXT: v_mul_f32_e64 v1, |v1|, 0.5
; GFX8-NEXT: v_trunc_f32_e32 v3, v1
; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
; GFX8-NEXT: s_xor_b64 s[4:5], s[6:7], exec
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -2986,12 +2920,12 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX9-NEXT: v_mul_f32_e64 v1, |v1|, 0.5
; GFX9-NEXT: v_trunc_f32_e32 v3, v1
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX9-NEXT: v_bfrev_b32_e32 v1, -2
+; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX9-NEXT: v_and_or_b32 v1, v2, v1, v3
; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
-; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
-; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], exec
-; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX9-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -3000,73 +2934,74 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX10-LABEL: v_pow_f32_fabs_rhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
; GFX10-NEXT: v_trunc_f32_e64 v5, |v1|
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v5, |v1|
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s5
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v5, |v1|
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX10-NEXT: s_xor_b32 s5, s6, exec_lo
+; GFX10-NEXT: s_xor_b32 s4, s5, exec_lo
+; GFX10-NEXT: s_and_b32 s4, s6, s4
; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX10-NEXT: v_log_f32_e32 v2, v2
; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
; GFX10-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
-; GFX10-NEXT: v_trunc_f32_e32 v6, v3
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v6, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX10-NEXT: v_exp_f32_e32 v1, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: s_and_b32 vcc_lo, s6, s4
-; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX10-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX10-NEXT: s_and_b32 s4, s4, s5
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
+; GFX10-NEXT: v_exp_f32_e32 v2, v2
+; GFX10-NEXT: v_trunc_f32_e32 v6, v3
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v3
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX10-NEXT: s_and_b32 vcc_lo, s5, vcc_lo
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_rhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
; GFX11-NEXT: v_trunc_f32_e64 v5, |v1|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
-; GFX11-NEXT: v_cmp_eq_f32_e64 s2, v5, |v1|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s1
+; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v5, |v1|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX11-NEXT: s_xor_b32 s1, s2, exec_lo
+; GFX11-NEXT: s_xor_b32 s0, s1, exec_lo
+; GFX11-NEXT: s_and_b32 s0, s2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX11-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v2, |v1|, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_trunc_f32_e32 v6, v3
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v6, v3
-; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_and_b32 vcc_lo, s2, s0
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
-; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX11-NEXT: s_and_b32 s0, s0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
+; GFX11-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX11-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call float @llvm.fabs.f32(float %y)
@@ -3082,36 +3017,21 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
-; GFX6-NEXT: v_log_f32_e32 v2, v2
-; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000
-; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX6-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
-; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
-; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
-; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
-; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX6-NEXT: v_exp_f32_e32 v2, v2
-; GFX6-NEXT: v_not_b32_e32 v3, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
-; GFX6-NEXT: v_trunc_f32_e64 v3, |v1|
-; GFX6-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, |v1|
-; GFX6-NEXT: v_mul_f32_e64 v1, |v1|, 0.5
-; GFX6-NEXT: v_trunc_f32_e32 v3, v1
-; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
-; GFX6-NEXT: s_and_b64 s[8:9], s[6:7], vcc
-; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, |v0|, s[8:9]
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
-; GFX6-NEXT: v_cmp_class_f32_e64 s[8:9], |v0|, 24
-; GFX6-NEXT: s_xor_b64 s[4:5], s[6:7], exec
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
-; GFX6-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs:
@@ -3121,36 +3041,21 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX8-NEXT: v_log_f32_e32 v2, v2
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
-; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX8-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
-; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
-; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
-; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX8-NEXT: v_exp_f32_e32 v2, v2
-; GFX8-NEXT: v_not_b32_e32 v3, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX8-NEXT: v_trunc_f32_e64 v3, |v1|
-; GFX8-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, |v1|
-; GFX8-NEXT: v_mul_f32_e64 v1, |v1|, 0.5
-; GFX8-NEXT: v_trunc_f32_e32 v3, v1
-; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
-; GFX8-NEXT: s_and_b64 s[8:9], s[6:7], vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, |v0|, s[8:9]
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
-; GFX8-NEXT: v_cmp_class_f32_e64 s[8:9], |v0|, 24
-; GFX8-NEXT: s_xor_b64 s[4:5], s[6:7], exec
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
-; GFX8-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX8-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs:
@@ -3160,109 +3065,65 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX9-NEXT: v_log_f32_e32 v2, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000
-; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX9-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000
-; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX9-NEXT: v_exp_f32_e32 v2, v2
-; GFX9-NEXT: v_not_b32_e32 v3, 63
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX9-NEXT: v_trunc_f32_e64 v3, |v1|
-; GFX9-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, |v1|
-; GFX9-NEXT: v_mul_f32_e64 v1, |v1|, 0.5
-; GFX9-NEXT: v_trunc_f32_e32 v3, v1
-; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
-; GFX9-NEXT: s_and_b64 s[8:9], s[6:7], vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, |v0|, s[8:9]
-; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
-; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
-; GFX9-NEXT: v_cmp_class_f32_e64 s[8:9], |v0|, 24
-; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], exec
-; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
-; GFX9-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
-; GFX10-NEXT: v_trunc_f32_e64 v5, |v1|
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v5, |v1|
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX10-NEXT: s_xor_b32 s5, s6, exec_lo
-; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX10-NEXT: v_log_f32_e32 v2, v2
-; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
-; GFX10-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
-; GFX10-NEXT: v_trunc_f32_e32 v6, v3
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v6, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: s_and_b32 s4, s6, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 1.0, |v0|, s4
-; GFX10-NEXT: v_cmp_class_f32_e64 s4, |v0|, 24
-; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX10-NEXT: s_and_b32 s4, s4, s5
-; GFX10-NEXT: v_exp_f32_e32 v1, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
+; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX10-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-NEXT: v_trunc_f32_e64 v5, |v1|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
-; GFX11-NEXT: v_cmp_eq_f32_e64 s2, v5, |v1|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX11-NEXT: s_xor_b32 s1, s2, exec_lo
-; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_log_f32_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX11-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
-; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v2, |v1|, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_trunc_f32_e32 v6, v3
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v6, v3
-; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: s_and_b32 s0, s2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 1.0, |v0|, s0
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, |v0|, 24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-NEXT: s_and_b32 s0, s0, s1
-; GFX11-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, |v1|, v0
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
%fabs.y = call float @llvm.fabs.f32(float %y)
@@ -3292,26 +3153,25 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
; GFX6-NEXT: v_add_f32_e32 v1, v1, v2
; GFX6-NEXT: v_exp_f32_e32 v1, v1
-; GFX6-NEXT: v_not_b32_e32 v3, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX6-NEXT: v_mov_b32_e32 v2, s0
-; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v3
-; GFX6-NEXT: v_trunc_f32_e32 v3, v0
-; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v0
+; GFX6-NEXT: v_not_b32_e32 v2, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: s_and_b32 s1, s0, 0x80000000
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v0
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v2, v0
; GFX6-NEXT: v_mul_f32_e32 v0, 0.5, v0
-; GFX6-NEXT: v_trunc_f32_e32 v3, v0
-; GFX6-NEXT: v_cmp_lg_f32_e64 s[2:3], v3, v0
+; GFX6-NEXT: v_trunc_f32_e32 v2, v0
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[2:3], v2, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0x7fffffff, v1
+; GFX6-NEXT: v_or_b32_e32 v0, s1, v0
; GFX6-NEXT: s_and_b64 s[2:3], vcc, s[2:3]
; GFX6-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
-; GFX6-NEXT: v_cndmask_b32_e64 v0, 1.0, v2, s[2:3]
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[2:3]
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_xor_b64 s[0:1], vcc, exec
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
-; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX6-NEXT: v_and_b32_e32 v0, 0x80000000, v0
; GFX6-NEXT: s_cselect_b64 s[2:3], exec, 0
-; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX6-NEXT: v_mov_b32_e32 v1, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
@@ -3338,26 +3198,25 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
; GFX8-NEXT: v_add_f32_e32 v1, v1, v2
; GFX8-NEXT: v_exp_f32_e32 v1, v1
-; GFX8-NEXT: v_not_b32_e32 v3, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX8-NEXT: v_mov_b32_e32 v2, s0
-; GFX8-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX8-NEXT: v_trunc_f32_e32 v3, v0
-; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v0
+; GFX8-NEXT: v_not_b32_e32 v2, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: s_and_b32 s1, s0, 0x80000000
+; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX8-NEXT: v_trunc_f32_e32 v2, v0
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v2, v0
; GFX8-NEXT: v_mul_f32_e32 v0, 0.5, v0
-; GFX8-NEXT: v_trunc_f32_e32 v3, v0
-; GFX8-NEXT: v_cmp_lg_f32_e64 s[2:3], v3, v0
+; GFX8-NEXT: v_trunc_f32_e32 v2, v0
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[2:3], v2, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v1
+; GFX8-NEXT: v_or_b32_e32 v0, s1, v0
; GFX8-NEXT: s_and_b64 s[2:3], vcc, s[2:3]
; GFX8-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX8-NEXT: v_cndmask_b32_e64 v0, 1.0, v2, s[2:3]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[2:3]
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_xor_b64 s[0:1], vcc, exec
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
-; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX8-NEXT: v_and_b32_e32 v0, 0x80000000, v0
; GFX8-NEXT: s_cselect_b64 s[2:3], exec, 0
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v1, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
@@ -3384,26 +3243,25 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
; GFX9-NEXT: v_add_f32_e32 v1, v1, v2
; GFX9-NEXT: v_exp_f32_e32 v1, v1
-; GFX9-NEXT: v_not_b32_e32 v3, 63
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX9-NEXT: v_mov_b32_e32 v2, s0
-; GFX9-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX9-NEXT: v_trunc_f32_e32 v3, v0
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v0
+; GFX9-NEXT: v_not_b32_e32 v2, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: s_and_b32 s1, s0, 0x80000000
+; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX9-NEXT: v_trunc_f32_e32 v2, v0
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v2, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0.5, v0
-; GFX9-NEXT: v_trunc_f32_e32 v3, v0
-; GFX9-NEXT: v_cmp_lg_f32_e64 s[2:3], v3, v0
+; GFX9-NEXT: v_trunc_f32_e32 v2, v0
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[2:3], v2, v0
+; GFX9-NEXT: v_bfrev_b32_e32 v0, -2
+; GFX9-NEXT: v_and_or_b32 v0, v1, v0, s1
; GFX9-NEXT: s_and_b64 s[2:3], vcc, s[2:3]
; GFX9-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, 1.0, v2, s[2:3]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[2:3]
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_xor_b64 s[0:1], vcc, exec
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
-; GFX9-NEXT: v_bfrev_b32_e32 v2, -2
-; GFX9-NEXT: v_and_b32_e32 v0, 0x80000000, v0
; GFX9-NEXT: s_cselect_b64 s[2:3], exec, 0
-; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7fc00000
; GFX9-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
@@ -3412,83 +3270,82 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX10-LABEL: v_pow_f32_sgpr_vgpr:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0|
-; GFX10-NEXT: v_mul_f32_e32 v2, 0.5, v0
-; GFX10-NEXT: v_trunc_f32_e32 v4, v0
+; GFX10-NEXT: v_trunc_f32_e32 v3, v0
; GFX10-NEXT: s_cmp_lg_u32 s1, 0
-; GFX10-NEXT: v_trunc_f32_e32 v5, v2
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cselect_b32 s3, 1, 0
; GFX10-NEXT: s_cselect_b32 s1, 1, 0
-; GFX10-NEXT: s_lshl_b32 s2, s2, 5
+; GFX10-NEXT: s_lshl_b32 s3, s3, 5
; GFX10-NEXT: s_cmp_lg_u32 s1, 0
-; GFX10-NEXT: v_ldexp_f32 v1, |s0|, s2
+; GFX10-NEXT: v_ldexp_f32 v1, |s0|, s3
; GFX10-NEXT: s_cselect_b32 s1, 0x42000000, 0
-; GFX10-NEXT: v_cmp_lg_f32_e64 s2, v5, v2
+; GFX10-NEXT: v_cmp_class_f32_e64 s3, s0, 24
+; GFX10-NEXT: s_and_b32 s0, s0, 0x80000000
; GFX10-NEXT: v_log_f32_e32 v1, v1
; GFX10-NEXT: v_subrev_f32_e32 v1, s1, v1
-; GFX10-NEXT: v_cmp_eq_f32_e64 s1, v4, v0
; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v0, v1
-; GFX10-NEXT: s_and_b32 s2, s1, s2
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX10-NEXT: v_exp_f32_e32 v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, s0, s2
-; GFX10-NEXT: v_cmp_class_f32_e64 s0, s0, 24
-; GFX10-NEXT: v_and_b32_e32 v1, 0x80000000, v1
-; GFX10-NEXT: s_cmp_lg_u32 s0, 0
-; GFX10-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX10-NEXT: s_xor_b32 s1, s1, exec_lo
-; GFX10-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v0
+; GFX10-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_mul_f32_e32 v2, 0.5, v0
+; GFX10-NEXT: v_exp_f32_e32 v1, v1
+; GFX10-NEXT: v_trunc_f32_e32 v5, v2
+; GFX10-NEXT: v_cmp_lg_f32_e64 s1, v5, v2
+; GFX10-NEXT: v_ldexp_f32 v0, v1, v4
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, s0
+; GFX10-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX10-NEXT: s_cmp_lg_u32 s3, 0
+; GFX10-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10-NEXT: s_xor_b32 s2, vcc_lo, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
; GFX10-NEXT: s_cselect_b32 s0, exec_lo, 0
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v0, v1
-; GFX10-NEXT: s_and_b32 s0, s0, s1
+; GFX10-NEXT: s_and_b32 s0, s0, s2
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_pow_f32_sgpr_vgpr:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0|
-; GFX11-NEXT: v_trunc_f32_e32 v4, v0
-; GFX11-NEXT: v_mul_f32_e32 v2, 0.5, v0
+; GFX11-NEXT: v_trunc_f32_e32 v3, v0
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cselect_b32 s3, 1, 0
; GFX11-NEXT: s_cselect_b32 s1, 1, 0
-; GFX11-NEXT: s_lshl_b32 s2, s2, 5
+; GFX11-NEXT: s_lshl_b32 s3, s3, 5
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
-; GFX11-NEXT: v_ldexp_f32 v1, |s0|, s2
+; GFX11-NEXT: v_ldexp_f32 v1, |s0|, s3
; GFX11-NEXT: s_cselect_b32 s1, 0x42000000, 0
-; GFX11-NEXT: v_trunc_f32_e32 v5, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_class_f32_e64 s3, s0, 24
+; GFX11-NEXT: s_and_b32 s0, s0, 0x80000000
; GFX11-NEXT: v_log_f32_e32 v1, v1
-; GFX11-NEXT: v_cmp_lg_f32_e64 s2, v5, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_subrev_f32_e32 v1, s1, v1
-; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v4, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, v0, v1
-; GFX11-NEXT: s_and_b32 s2, s1, s2
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX11-NEXT: v_exp_f32_e32 v0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, s0, s2
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, s0, 24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_and_b32_e32 v1, 0x80000000, v1
-; GFX11-NEXT: s_cmp_lg_u32 s0, 0
-; GFX11-NEXT: s_cselect_b32 s0, 1, 0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mul_f32 v2, 0.5, v0
+; GFX11-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v5, v2
+; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v5, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX11-NEXT: s_xor_b32 s1, s1, exec_lo
-; GFX11-NEXT: s_cmp_lg_u32 s0, 0
-; GFX11-NEXT: s_cselect_b32 s0, exec_lo, 0
+; GFX11-NEXT: v_ldexp_f32 v0, v1, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v0, v1
-; GFX11-NEXT: s_and_b32 s0, s0, s1
+; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, s0
+; GFX11-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX11-NEXT: s_cmp_lg_u32 s3, 0
+; GFX11-NEXT: s_cselect_b32 s1, 1, 0
+; GFX11-NEXT: s_xor_b32 s2, vcc_lo, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s1, 0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX11-NEXT: s_cselect_b32 s0, exec_lo, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s0, s0, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: ; return to shader part epilog
@@ -3531,13 +3388,13 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX6-NEXT: s_cmp_lg_u32 s0, 0
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
; GFX6-NEXT: s_xor_b32 s2, s2, 1
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v1
+; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v0
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
-; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX6-NEXT: v_and_b32_e32 v2, 0x80000000, v2
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_cmp_class_f32_e64 s[0:1], v0, 24
; GFX6-NEXT: s_cselect_b64 s[2:3], exec, 0
-; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -3577,13 +3434,13 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX8-NEXT: s_cmp_lg_u32 s0, 0
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
; GFX8-NEXT: s_xor_b32 s2, s2, 1
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v1
+; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
-; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; GFX8-NEXT: v_and_b32_e32 v2, 0x80000000, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
; GFX8-NEXT: v_cmp_class_f32_e64 s[0:1], v0, 24
; GFX8-NEXT: s_cselect_b64 s[2:3], exec, 0
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -3623,13 +3480,13 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_cselect_b64 vcc, exec, 0
; GFX9-NEXT: s_xor_b32 s2, s2, 1
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; GFX9-NEXT: v_bfrev_b32_e32 v2, -2
+; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v0
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
-; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
-; GFX9-NEXT: v_and_b32_e32 v2, 0x80000000, v2
+; GFX9-NEXT: v_and_or_b32 v2, v1, v2, v3
; GFX9-NEXT: v_cmp_class_f32_e64 s[0:1], v0, 24
; GFX9-NEXT: s_cselect_b64 s[2:3], exec, 0
-; GFX9-NEXT: v_and_or_b32 v1, v1, v3, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX9-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -3639,38 +3496,38 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
; GFX10-NEXT: v_mul_f32_e64 v3, s0, 0.5
+; GFX10-NEXT: v_cmp_class_f32_e64 s2, v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s1
; GFX10-NEXT: v_trunc_f32_e32 v4, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX10-NEXT: v_cmp_lg_f32_e64 s1, v4, v3
+; GFX10-NEXT: v_and_b32_e32 v3, 0x80000000, v0
; GFX10-NEXT: v_ldexp_f32 v1, |v0|, v1
; GFX10-NEXT: v_log_f32_e32 v1, v1
; GFX10-NEXT: v_sub_f32_e32 v1, v1, v2
-; GFX10-NEXT: v_trunc_f32_e32 v2, s0
; GFX10-NEXT: v_mul_legacy_f32_e32 v1, s0, v1
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, s0, v2
-; GFX10-NEXT: v_cmp_lg_f32_e64 s0, v4, v3
-; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0xc2fc0000, v1
-; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s0, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, s1
-; GFX10-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s1
-; GFX10-NEXT: s_and_b32 s0, s2, s0
-; GFX10-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX10-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX10-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
-; GFX10-NEXT: s_xor_b32 s1, s2, 1
-; GFX10-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX10-NEXT: v_trunc_f32_e32 v2, s0
; GFX10-NEXT: v_exp_f32_e32 v1, v1
+; GFX10-NEXT: v_cmp_eq_f32_e64 s0, s0, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-NEXT: s_cselect_b32 s0, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX10-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10-NEXT: s_and_b32 s1, s0, s1
; GFX10-NEXT: s_cmp_lg_u32 s1, 0
-; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v2
-; GFX10-NEXT: s_cselect_b32 s1, exec_lo, 0
-; GFX10-NEXT: s_and_b32 s0, s0, s1
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v3
+; GFX10-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
+; GFX10-NEXT: s_xor_b32 s0, s0, 1
+; GFX10-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10-NEXT: s_cselect_b32 s0, exec_lo, 0
+; GFX10-NEXT: s_and_b32 s0, s2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX10-NEXT: ; return to shader part epilog
;
@@ -3678,47 +3535,50 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX11: ; %bb.0:
; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
; GFX11-NEXT: v_mul_f32_e64 v3, s0, 0.5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s1
; GFX11-NEXT: v_trunc_f32_e32 v4, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v4, v3
+; GFX11-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v1, |v0|, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_log_f32_e32 v1, v1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v1, v1, v2
-; GFX11-NEXT: v_trunc_f32_e32 v2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, s0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, s0, v2
-; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v4, v3
-; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0xc2fc0000, v1
-; GFX11-NEXT: s_cmp_lg_u32 vcc_lo, 0
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s0, 0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, s1
-; GFX11-NEXT: s_cselect_b32 s0, 1, 0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s1
-; GFX11-NEXT: s_and_b32 s0, s2, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
-; GFX11-NEXT: s_xor_b32 s1, s2, 1
-; GFX11-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc_lo
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX11-NEXT: v_trunc_f32_e32 v2, s0
; GFX11-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, s0, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
-; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v2
-; GFX11-NEXT: s_cselect_b32 s1, exec_lo, 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: s_and_b32 s0, s0, s1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11-NEXT: s_cselect_b32 s1, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s1, s0, s1
+; GFX11-NEXT: s_cmp_lg_u32 s1, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v3
+; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
+; GFX11-NEXT: s_xor_b32 s0, s0, 1
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-NEXT: s_cselect_b32 s0, exec_lo, 0
+; GFX11-NEXT: s_and_b32 s0, s2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
@@ -3759,13 +3619,13 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX6-NEXT: s_cselect_b32 s5, 1, 0
; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc
; GFX6-NEXT: s_cselect_b32 s1, 1, 0
+; GFX6-NEXT: s_and_b32 s2, s4, 0x7fffffff
+; GFX6-NEXT: s_and_b32 s3, s0, 0x80000000
; GFX6-NEXT: s_and_b32 s1, s5, s1
+; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: s_cmp_lg_u32 s1, 0
-; GFX6-NEXT: s_cselect_b32 s1, s0, 1.0
-; GFX6-NEXT: s_and_b32 s2, s4, 0x7fffffff
-; GFX6-NEXT: s_and_b32 s1, s1, 0x80000000
-; GFX6-NEXT: s_or_b32 s2, s2, s1
; GFX6-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
+; GFX6-NEXT: s_cselect_b32 s2, s2, s4
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
; GFX6-NEXT: s_cselect_b32 s0, 1, 0
; GFX6-NEXT: s_xor_b32 s1, s5, 1
@@ -3808,13 +3668,13 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX8-NEXT: s_cselect_b32 s3, 1, 0
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-NEXT: s_cselect_b32 s1, 1, 0
+; GFX8-NEXT: s_and_b32 s4, s2, 0x7fffffff
+; GFX8-NEXT: s_and_b32 s5, s0, 0x80000000
; GFX8-NEXT: s_and_b32 s1, s3, s1
+; GFX8-NEXT: s_or_b32 s4, s4, s5
; GFX8-NEXT: s_cmp_lg_u32 s1, 0
-; GFX8-NEXT: s_cselect_b32 s1, s0, 1.0
-; GFX8-NEXT: s_bitset0_b32 s2, 31
-; GFX8-NEXT: s_and_b32 s1, s1, 0x80000000
-; GFX8-NEXT: s_or_b32 s2, s2, s1
; GFX8-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
+; GFX8-NEXT: s_cselect_b32 s2, s4, s2
; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: s_xor_b32 s1, s3, 1
@@ -3857,13 +3717,13 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX9-NEXT: s_cselect_b32 s3, 1, 0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-NEXT: s_and_b32 s4, s2, 0x7fffffff
+; GFX9-NEXT: s_and_b32 s5, s0, 0x80000000
; GFX9-NEXT: s_and_b32 s1, s3, s1
+; GFX9-NEXT: s_or_b32 s4, s4, s5
; GFX9-NEXT: s_cmp_lg_u32 s1, 0
-; GFX9-NEXT: s_cselect_b32 s1, s0, 1.0
-; GFX9-NEXT: s_bitset0_b32 s2, 31
-; GFX9-NEXT: s_and_b32 s1, s1, 0x80000000
-; GFX9-NEXT: s_or_b32 s2, s2, s1
; GFX9-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
+; GFX9-NEXT: s_cselect_b32 s2, s4, s2
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: s_xor_b32 s1, s3, 1
@@ -3878,6 +3738,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX10-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0|
; GFX10-NEXT: v_mul_f32_e64 v1, s1, 0.5
; GFX10-NEXT: v_trunc_f32_e32 v2, s1
+; GFX10-NEXT: v_cmp_class_f32_e64 s4, s0, 24
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
; GFX10-NEXT: v_trunc_f32_e32 v3, v1
; GFX10-NEXT: s_cselect_b32 s3, 1, 0
@@ -3897,25 +3758,24 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX10-NEXT: v_add_f32_e32 v0, s2, v0
; GFX10-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0
-; GFX10-NEXT: s_cselect_b32 s3, 1, 0
; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: s_cselect_b32 s1, 1, 0
-; GFX10-NEXT: s_and_b32 s1, s3, s1
+; GFX10-NEXT: v_readfirstlane_b32 s3, v0
+; GFX10-NEXT: s_and_b32 s0, s0, 0x80000000
+; GFX10-NEXT: s_and_b32 s1, s2, s1
+; GFX10-NEXT: s_and_b32 s5, s3, 0x7fffffff
+; GFX10-NEXT: s_or_b32 s5, s5, s0
; GFX10-NEXT: s_cmp_lg_u32 s1, 0
-; GFX10-NEXT: s_cselect_b32 s1, s0, 1.0
-; GFX10-NEXT: v_ldexp_f32 v0, v0, s2
-; GFX10-NEXT: v_cmp_class_f32_e64 s0, s0, 24
-; GFX10-NEXT: s_and_b32 s1, s1, 0x80000000
-; GFX10-NEXT: v_readfirstlane_b32 s2, v0
-; GFX10-NEXT: s_bitset0_b32 s2, 31
-; GFX10-NEXT: s_or_b32 s2, s2, s1
-; GFX10-NEXT: s_cmp_lg_u32 s0, 0
-; GFX10-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10-NEXT: s_xor_b32 s1, s3, 1
-; GFX10-NEXT: s_and_b32 s0, s0, s1
-; GFX10-NEXT: s_cmp_lg_u32 s0, 0
-; GFX10-NEXT: s_cselect_b32 s0, 0x7fc00000, s2
+; GFX10-NEXT: s_cselect_b32 s0, s5, s3
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
+; GFX10-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10-NEXT: s_xor_b32 s2, s2, 1
+; GFX10-NEXT: s_and_b32 s1, s1, s2
+; GFX10-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10-NEXT: s_cselect_b32 s0, 0x7fc00000, s0
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: ; return to shader part epilog
;
@@ -3924,8 +3784,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0|
; GFX11-NEXT: v_mul_f32_e64 v1, s1, 0.5
; GFX11-NEXT: v_trunc_f32_e32 v2, s1
+; GFX11-NEXT: v_cmp_class_f32_e64 s4, s0, 24
; GFX11-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_trunc_f32_e32 v3, v1
; GFX11-NEXT: s_cselect_b32 s3, 1, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
@@ -3947,30 +3807,29 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX11-NEXT: v_add_f32_e32 v0, s2, v0
; GFX11-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; GFX11-NEXT: s_cmp_lg_u32 vcc_lo, 0
-; GFX11-NEXT: s_cselect_b32 s3, 1, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
; GFX11-NEXT: s_cselect_b32 s1, 1, 0
-; GFX11-NEXT: s_and_b32 s1, s3, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_readfirstlane_b32 s3, v0
+; GFX11-NEXT: s_and_b32 s0, s0, 0x80000000
+; GFX11-NEXT: s_and_b32 s1, s2, s1
+; GFX11-NEXT: s_and_b32 s5, s3, 0x7fffffff
+; GFX11-NEXT: s_or_b32 s5, s5, s0
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
-; GFX11-NEXT: s_cselect_b32 s1, s0, 1.0
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, s2
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, s0, 24
-; GFX11-NEXT: s_and_b32 s1, s1, 0x80000000
-; GFX11-NEXT: v_readfirstlane_b32 s2, v0
-; GFX11-NEXT: s_bitset0_b32 s2, 31
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s2, s2, s1
-; GFX11-NEXT: s_cmp_lg_u32 s0, 0
-; GFX11-NEXT: s_cselect_b32 s0, 1, 0
-; GFX11-NEXT: s_xor_b32 s1, s3, 1
-; GFX11-NEXT: s_and_b32 s0, s0, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_cmp_lg_u32 s0, 0
-; GFX11-NEXT: s_cselect_b32 s0, 0x7fc00000, s2
+; GFX11-NEXT: s_cselect_b32 s0, s5, s3
+; GFX11-NEXT: s_cmp_lg_u32 s4, 0
+; GFX11-NEXT: s_cselect_b32 s1, 1, 0
+; GFX11-NEXT: s_xor_b32 s2, s2, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s1, s1, s2
+; GFX11-NEXT: s_cmp_lg_u32 s1, 0
+; GFX11-NEXT: s_cselect_b32 s0, 0x7fc00000, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
@@ -3997,21 +3856,22 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) {
; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
; GFX6-NEXT: v_exp_f32_e32 v2, v2
-; GFX6-NEXT: v_not_b32_e32 v3, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
-; GFX6-NEXT: v_trunc_f32_e32 v3, v1
-; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX6-NEXT: v_not_b32_e32 v4, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX6-NEXT: v_xor_b32_e32 v3, 0x80000000, v0
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v4
+; GFX6-NEXT: v_trunc_f32_e32 v4, v1
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GFX6-NEXT: v_trunc_f32_e32 v3, v1
-; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX6-NEXT: v_trunc_f32_e32 v4, v1
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v4, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v3
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v1, 1.0, -v0, s[4:5]
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], -v0, 24
; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -4036,21 +3896,22 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) {
; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
; GFX8-NEXT: v_exp_f32_e32 v2, v2
-; GFX8-NEXT: v_not_b32_e32 v3, 63
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX8-NEXT: v_trunc_f32_e32 v3, v1
-; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_not_b32_e32 v4, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX8-NEXT: v_xor_b32_e32 v3, 0x80000000, v0
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX8-NEXT: v_trunc_f32_e32 v4, v1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v4, v1
; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GFX8-NEXT: v_trunc_f32_e32 v3, v1
-; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: v_trunc_f32_e32 v4, v1
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v4, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v3
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, -v0, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], -v0, 24
; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -4075,21 +3936,22 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) {
; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
; GFX9-NEXT: v_exp_f32_e32 v2, v2
-; GFX9-NEXT: v_not_b32_e32 v3, 63
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX9-NEXT: v_trunc_f32_e32 v3, v1
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX9-NEXT: v_not_b32_e32 v4, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX9-NEXT: v_xor_b32_e32 v3, 0x80000000, v0
+; GFX9-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX9-NEXT: v_trunc_f32_e32 v4, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v1
; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GFX9-NEXT: v_trunc_f32_e32 v3, v1
-; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX9-NEXT: v_trunc_f32_e32 v4, v1
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v4, v1
+; GFX9-NEXT: v_bfrev_b32_e32 v1, -2
+; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v3
+; GFX9-NEXT: v_and_or_b32 v1, v2, v1, v3
; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, -v0, s[4:5]
-; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
-; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], -v0, 24
; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -4099,31 +3961,32 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
-; GFX10-NEXT: v_trunc_f32_e32 v5, v1
+; GFX10-NEXT: v_xor_b32_e32 v5, 0x80000000, v0
+; GFX10-NEXT: v_trunc_f32_e32 v6, v1
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, -v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX10-NEXT: v_log_f32_e32 v2, v2
; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX10-NEXT: v_trunc_f32_e32 v6, v3
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v6, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: s_and_b32 s5, s4, s5
-; GFX10-NEXT: s_xor_b32 s4, s4, exec_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 1.0, -v0, s5
-; GFX10-NEXT: v_cmp_class_f32_e64 s5, -v0, 24
-; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX10-NEXT: s_and_b32 s4, s5, s4
-; GFX10-NEXT: v_exp_f32_e32 v1, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v1
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX10-NEXT: v_exp_f32_e32 v2, v2
+; GFX10-NEXT: v_trunc_f32_e32 v7, v3
+; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v7, v3
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v5
+; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v1, s4
+; GFX10-NEXT: s_xor_b32 s4, vcc_lo, exec_lo
+; GFX10-NEXT: s_and_b32 s4, s6, s4
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -4131,39 +3994,41 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-NEXT: v_trunc_f32_e32 v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_xor_b32_e32 v5, 0x80000000, v0
+; GFX11-NEXT: v_trunc_f32_e32 v6, v1
+; GFX11-NEXT: v_cmp_class_f32_e64 s2, -v0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
-; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_trunc_f32_e32 v6, v3
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
-; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: s_and_b32 s1, s0, s1
-; GFX11-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 1.0, -v0, s1
-; GFX11-NEXT: v_cmp_class_f32_e64 s1, -v0, 24
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-NEXT: s_and_b32 s0, s1, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v7, v3
+; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v7, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v5
+; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0
+; GFX11-NEXT: s_xor_b32 s0, vcc_lo, exec_lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s0, s2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.x = fneg float %x
@@ -4200,12 +4065,12 @@ define float @v_pow_f32_fneg_rhs(float %x, float %y) {
; GFX6-NEXT: v_mul_f32_e64 v1, -v1, 0.5
; GFX6-NEXT: v_trunc_f32_e32 v3, v1
; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0x80000000, v1
; GFX6-NEXT: s_xor_b64 s[4:5], s[6:7], exec
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -4239,12 +4104,12 @@ define float @v_pow_f32_fneg_rhs(float %x, float %y) {
; GFX8-NEXT: v_mul_f32_e64 v1, -v1, 0.5
; GFX8-NEXT: v_trunc_f32_e32 v3, v1
; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
; GFX8-NEXT: s_xor_b64 s[4:5], s[6:7], exec
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -4278,12 +4143,12 @@ define float @v_pow_f32_fneg_rhs(float %x, float %y) {
; GFX9-NEXT: v_mul_f32_e64 v1, -v1, 0.5
; GFX9-NEXT: v_trunc_f32_e32 v3, v1
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
+; GFX9-NEXT: v_bfrev_b32_e32 v1, -2
+; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX9-NEXT: v_and_or_b32 v1, v2, v1, v3
; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
-; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
-; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v1
; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], exec
-; GFX9-NEXT: v_and_or_b32 v1, v2, v3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX9-NEXT: s_and_b64 vcc, s[8:9], s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -4292,73 +4157,74 @@ define float @v_pow_f32_fneg_rhs(float %x, float %y) {
; GFX10-LABEL: v_pow_f32_fneg_rhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
; GFX10-NEXT: v_trunc_f32_e64 v5, -v1
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v5, -v1
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s5
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v5, -v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX10-NEXT: s_xor_b32 s5, s6, exec_lo
+; GFX10-NEXT: s_xor_b32 s4, s5, exec_lo
+; GFX10-NEXT: s_and_b32 s4, s6, s4
; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX10-NEXT: v_log_f32_e32 v2, v2
; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_mul_f32_e64 v3, -v1, 0.5
; GFX10-NEXT: v_mul_legacy_f32_e64 v2, -v1, v2
-; GFX10-NEXT: v_trunc_f32_e32 v6, v3
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v6, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX10-NEXT: v_exp_f32_e32 v1, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: s_and_b32 vcc_lo, s6, s4
-; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX10-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX10-NEXT: s_and_b32 s4, s4, s5
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e64 v3, -v1, 0.5
+; GFX10-NEXT: v_exp_f32_e32 v2, v2
+; GFX10-NEXT: v_trunc_f32_e32 v6, v3
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v3
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX10-NEXT: s_and_b32 vcc_lo, s5, vcc_lo
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fneg_rhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
; GFX11-NEXT: v_trunc_f32_e64 v5, -v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
-; GFX11-NEXT: v_cmp_eq_f32_e64 s2, v5, -v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s1
+; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v5, -v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX11-NEXT: s_xor_b32 s1, s2, exec_lo
+; GFX11-NEXT: s_xor_b32 s0, s1, exec_lo
+; GFX11-NEXT: s_and_b32 s0, s2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX11-NEXT: v_mul_f32_e64 v3, -v1, 0.5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v2, -v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_trunc_f32_e32 v6, v3
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v6, v3
-; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_and_b32 vcc_lo, s2, s0
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
-; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX11-NEXT: s_and_b32 s0, s0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_f32_e64 v3, -v1, 0.5
+; GFX11-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX11-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.y = fneg float %y
@@ -4511,7 +4377,6 @@ define float @v_pow_f32_const_even_int(float %x) {
; GFX6-NEXT: v_not_b32_e32 v1, 63
; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_const_even_int:
@@ -4536,7 +4401,6 @@ define float @v_pow_f32_const_even_int(float %x) {
; GFX8-NEXT: v_not_b32_e32 v1, 63
; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_const_even_int:
@@ -4561,8 +4425,6 @@ define float @v_pow_f32_const_even_int(float %x) {
; GFX9-NEXT: v_not_b32_e32 v1, 63
; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX9-NEXT: v_bfrev_b32_e32 v1, -2
-; GFX9-NEXT: v_and_or_b32 v0, v0, v1, 0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_const_even_int:
@@ -4582,7 +4444,6 @@ define float @v_pow_f32_const_even_int(float %x) {
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v0, 0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_const_even_int:
@@ -4608,8 +4469,6 @@ define float @v_pow_f32_const_even_int(float %x) {
; GFX11-NEXT: v_exp_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v0, 0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call float @llvm.pow.f32(float %x, float 2.0)
ret float %pow
@@ -4773,7 +4632,6 @@ define float @v_pow_f32_const_non_int(float %x) {
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX6-NEXT: v_cmp_class_f32_e64 vcc, v0, 24
; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -4801,7 +4659,6 @@ define float @v_pow_f32_const_non_int(float %x) {
; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v0, 24
; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -4829,8 +4686,6 @@ define float @v_pow_f32_const_non_int(float %x) {
; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, 24
; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX9-NEXT: v_bfrev_b32_e32 v2, -2
-; GFX9-NEXT: v_and_or_b32 v1, v1, v2, 0
; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -4853,7 +4708,6 @@ define float @v_pow_f32_const_non_int(float %x) {
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v1, v1
; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -4881,8 +4735,7 @@ define float @v_pow_f32_const_non_int(float %x) {
; GFX11-NEXT: v_exp_f32_e32 v1, v1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v1, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call float @llvm.pow.f32(float %x, float 5.000000e-01)
@@ -4911,17 +4764,17 @@ define float @v_pow_f32_nnan(float %x, float %y) {
; GFX6-NEXT: v_exp_f32_e32 v2, v2
; GFX6-NEXT: v_not_b32_e32 v3, 63
; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_and_b32_e32 v0, 0x80000000, v0
; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
; GFX6-NEXT: v_trunc_f32_e32 v3, v1
; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX6-NEXT: v_trunc_f32_e32 v3, v1
; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
-; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v0, 0x80000000, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_nnan:
@@ -4945,17 +4798,17 @@ define float @v_pow_f32_nnan(float %x, float %y) {
; GFX8-NEXT: v_exp_f32_e32 v2, v2
; GFX8-NEXT: v_not_b32_e32 v3, 63
; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_and_b32_e32 v0, 0x80000000, v0
; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
; GFX8-NEXT: v_trunc_f32_e32 v3, v1
; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX8-NEXT: v_trunc_f32_e32 v3, v1
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
-; GFX8-NEXT: s_and_b64 vcc, vcc, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v0, 0x80000000, v0
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_nnan:
@@ -4979,17 +4832,17 @@ define float @v_pow_f32_nnan(float %x, float %y) {
; GFX9-NEXT: v_exp_f32_e32 v2, v2
; GFX9-NEXT: v_not_b32_e32 v3, 63
; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_and_b32_e32 v0, 0x80000000, v0
; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
; GFX9-NEXT: v_trunc_f32_e32 v3, v1
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX9-NEXT: v_trunc_f32_e32 v3, v1
; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
-; GFX9-NEXT: s_and_b64 vcc, vcc, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
; GFX9-NEXT: v_bfrev_b32_e32 v1, -2
-; GFX9-NEXT: v_and_b32_e32 v0, 0x80000000, v0
; GFX9-NEXT: v_and_or_b32 v0, v2, v1, v0
+; GFX9-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_nnan:
@@ -4999,25 +4852,25 @@ define float @v_pow_f32_nnan(float %x, float %y) {
; GFX10-NEXT: v_trunc_f32_e32 v5, v1
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX10-NEXT: v_and_b32_e32 v0, 0x80000000, v0
; GFX10-NEXT: v_log_f32_e32 v2, v2
; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX10-NEXT: v_trunc_f32_e32 v6, v3
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v6, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX10-NEXT: v_exp_f32_e32 v1, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: s_and_b32 vcc_lo, s4, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v0, 0x80000000, v0
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX10-NEXT: v_exp_f32_e32 v2, v2
+; GFX10-NEXT: v_trunc_f32_e32 v6, v3
+; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v6, v3
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v2, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_nnan:
@@ -5025,40 +4878,160 @@ define float @v_pow_f32_nnan(float %x, float %y) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX11-NEXT: v_trunc_f32_e32 v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
-; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_b32_e32 v0, 0x80000000, v0
; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_trunc_f32_e32 v6, v3
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
-; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_and_b32 vcc_lo, s0, s1
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
-; GFX11-NEXT: v_and_b32_e32 v0, 0x80000000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v6, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v0
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX11-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v2, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call nnan float @llvm.pow.f32(float %x, float %y)
ret float %pow
}
+define float @v_pow_f32_daz(float %x, float %y) #0 {
+; GFX6-LABEL: v_pow_f32_daz:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_log_f32_e64 v2, |v0|
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 8
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f32_daz:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_log_f32_e64 v2, |v0|
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 8
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f32_daz:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_log_f32_e64 v2, |v0|
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
+; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX9-NEXT: v_bfrev_b32_e32 v1, -2
+; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX9-NEXT: v_and_or_b32 v1, v2, v1, v3
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 8
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f32_daz:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_log_f32_e64 v2, |v0|
+; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX10-NEXT: v_trunc_f32_e32 v4, v1
+; GFX10-NEXT: v_and_b32_e32 v6, 0x80000000, v0
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 8
+; GFX10-NEXT: v_trunc_f32_e32 v5, v3
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v5, v3
+; GFX10-NEXT: v_exp_f32_e32 v2, v2
+; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v1, s4
+; GFX10-NEXT: s_xor_b32 s4, vcc_lo, exec_lo
+; GFX10-NEXT: s_and_b32 s4, s6, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_pow_f32_daz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_log_f32_e64 v2, |v0|
+; GFX11-NEXT: v_trunc_f32_e32 v4, v1
+; GFX11-NEXT: v_and_b32_e32 v6, 0x80000000, v0
+; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 8
+; GFX11-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v1
+; GFX11-NEXT: v_trunc_f32_e32 v5, v3
+; GFX11-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v5, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v6
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0
+; GFX11-NEXT: s_xor_b32 s0, vcc_lo, exec_lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s0, s2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %pow = call float @llvm.pow.f32(float %x, float %y)
+ ret float %pow
+}
+
declare half @llvm.pow.f16(half, half)
declare float @llvm.pow.f32(float, float)
declare double @llvm.pow.f64(double, double)
@@ -5068,3 +5041,5 @@ declare float @llvm.fabs.f32(float)
declare <2 x half> @llvm.pow.v2f16(<2 x half>, <2 x half>)
declare <2 x float> @llvm.pow.v2f32(<2 x float>, <2 x float>)
+
+attributes #0 = { denormal_fpenv(float:preservesign|preservesign) }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
index c33f1211a030c..8fb41b0b6f6c8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
@@ -44,21 +44,21 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[COPY]], [[C2]]
; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
; GFX6-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[COPY]](f32), 24
; GFX6-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
; GFX6-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
- ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[SELECT4]]
; GFX6-NEXT: $vgpr0 = COPY [[SELECT5]](f32)
;
; GFX9-LABEL: name: test_fpow_f32
@@ -95,21 +95,21 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[COPY]], [[C2]]
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
; GFX9-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[COPY]](f32), 24
; GFX9-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
; GFX9-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
- ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[SELECT4]]
; GFX9-NEXT: $vgpr0 = COPY [[SELECT5]](f32)
%0:_(f32) = COPY $vgpr0
%1:_(f32) = COPY $vgpr1
@@ -159,21 +159,21 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[UV]], [[C2]]
; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](f32)
; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
; GFX6-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV]](f32), 24
; GFX6-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
; GFX6-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
- ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[SELECT4]]
; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[UV1]]
; GFX6-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C]]
; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C1]], [[C2]]
@@ -194,17 +194,17 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
; GFX6-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
- ; GFX6-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[UV1]], [[C2]]
; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
- ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT10]](f32)
+ ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](f32)
; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
; GFX6-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[BITCAST4]], [[C9]]
; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND5]], [[AND6]]
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX6-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[BITCAST5]], [[FMUL4]]
; GFX6-NEXT: [[IS_FPCLASS1:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV1]](f32), 24
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[FCMP6]], [[C11]]
; GFX6-NEXT: [[AND7:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS1]], [[XOR1]]
- ; GFX6-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C12]], [[BITCAST5]]
+ ; GFX6-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C12]], [[SELECT10]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[SELECT5]](f32), [[SELECT11]](f32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
@@ -244,21 +244,21 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[UV]], [[C2]]
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](f32)
; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
; GFX9-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV]](f32), 24
; GFX9-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
; GFX9-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
- ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[SELECT4]]
; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[UV1]]
; GFX9-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C]]
; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C1]], [[C2]]
@@ -279,17 +279,17 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
; GFX9-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
- ; GFX9-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[UV1]], [[C2]]
; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
- ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT10]](f32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](f32)
; GFX9-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
; GFX9-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[BITCAST4]], [[C9]]
; GFX9-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND5]], [[AND6]]
; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX9-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[BITCAST5]], [[FMUL4]]
; GFX9-NEXT: [[IS_FPCLASS1:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV1]](f32), 24
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[FCMP6]], [[C11]]
; GFX9-NEXT: [[AND7:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS1]], [[XOR1]]
- ; GFX9-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C12]], [[BITCAST5]]
+ ; GFX9-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C12]], [[SELECT10]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[SELECT5]](f32), [[SELECT11]](f32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
%0:_(<2 x f32>) = COPY $vgpr0_vgpr1
@@ -340,21 +340,21 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[UV]], [[C2]]
; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](f32)
; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
; GFX6-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV]](f32), 24
; GFX6-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
; GFX6-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
- ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[SELECT4]]
; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[UV1]]
; GFX6-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C]]
; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C1]], [[C2]]
@@ -375,17 +375,17 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
; GFX6-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
- ; GFX6-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[UV1]], [[C2]]
; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
- ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT10]](f32)
+ ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](f32)
; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
; GFX6-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[BITCAST4]], [[C9]]
; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND5]], [[AND6]]
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX6-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[BITCAST5]], [[FMUL4]]
; GFX6-NEXT: [[IS_FPCLASS1:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV1]](f32), 24
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[FCMP6]], [[C11]]
; GFX6-NEXT: [[AND7:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS1]], [[XOR1]]
- ; GFX6-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C12]], [[BITCAST5]]
+ ; GFX6-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C12]], [[SELECT10]]
; GFX6-NEXT: [[FABS2:%[0-9]+]]:_(f32) = G_FABS [[UV2]]
; GFX6-NEXT: [[FCMP8:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](f32), [[C]]
; GFX6-NEXT: [[SELECT12:%[0-9]+]]:_(f32) = G_SELECT [[FCMP8]](s1), [[C1]], [[C2]]
@@ -406,17 +406,17 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC5:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL8]]
; GFX6-NEXT: [[FCMP11:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC5]](f32), [[FMUL8]]
; GFX6-NEXT: [[AND8:%[0-9]+]]:_(s1) = G_AND [[FCMP10]], [[FCMP11]]
- ; GFX6-NEXT: [[SELECT16:%[0-9]+]]:_(f32) = G_SELECT [[AND8]](s1), [[UV2]], [[C2]]
; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL7]](f32)
- ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT16]](f32)
+ ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](f32)
; GFX6-NEXT: [[AND9:%[0-9]+]]:_(i32) = G_AND [[BITCAST6]], [[C10]]
; GFX6-NEXT: [[AND10:%[0-9]+]]:_(i32) = G_AND [[BITCAST7]], [[C9]]
; GFX6-NEXT: [[OR2:%[0-9]+]]:_(i32) = disjoint G_OR [[AND9]], [[AND10]]
; GFX6-NEXT: [[BITCAST8:%[0-9]+]]:_(f32) = G_BITCAST [[OR2]](i32)
+ ; GFX6-NEXT: [[SELECT16:%[0-9]+]]:_(f32) = G_SELECT [[AND8]](s1), [[BITCAST8]], [[FMUL7]]
; GFX6-NEXT: [[IS_FPCLASS2:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV2]](f32), 24
; GFX6-NEXT: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[FCMP10]], [[C11]]
; GFX6-NEXT: [[AND11:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS2]], [[XOR2]]
- ; GFX6-NEXT: [[SELECT17:%[0-9]+]]:_(f32) = G_SELECT [[AND11]](s1), [[C12]], [[BITCAST8]]
+ ; GFX6-NEXT: [[SELECT17:%[0-9]+]]:_(f32) = G_SELECT [[AND11]](s1), [[C12]], [[SELECT16]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[SELECT5]](f32), [[SELECT11]](f32), [[SELECT17]](f32)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
@@ -456,21 +456,21 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[UV]], [[C2]]
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](f32)
; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
; GFX9-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV]](f32), 24
; GFX9-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
; GFX9-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
- ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[SELECT4]]
; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[UV1]]
; GFX9-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C]]
; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C1]], [[C2]]
@@ -491,17 +491,17 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
; GFX9-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
- ; GFX9-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[UV1]], [[C2]]
; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
- ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT10]](f32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](f32)
; GFX9-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
; GFX9-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[BITCAST4]], [[C9]]
; GFX9-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND5]], [[AND6]]
; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX9-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[BITCAST5]], [[FMUL4]]
; GFX9-NEXT: [[IS_FPCLASS1:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV1]](f32), 24
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[FCMP6]], [[C11]]
; GFX9-NEXT: [[AND7:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS1]], [[XOR1]]
- ; GFX9-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C12]], [[BITCAST5]]
+ ; GFX9-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C12]], [[SELECT10]]
; GFX9-NEXT: [[FABS2:%[0-9]+]]:_(f32) = G_FABS [[UV2]]
; GFX9-NEXT: [[FCMP8:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](f32), [[C]]
; GFX9-NEXT: [[SELECT12:%[0-9]+]]:_(f32) = G_SELECT [[FCMP8]](s1), [[C1]], [[C2]]
@@ -522,17 +522,17 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC5:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL8]]
; GFX9-NEXT: [[FCMP11:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC5]](f32), [[FMUL8]]
; GFX9-NEXT: [[AND8:%[0-9]+]]:_(s1) = G_AND [[FCMP10]], [[FCMP11]]
- ; GFX9-NEXT: [[SELECT16:%[0-9]+]]:_(f32) = G_SELECT [[AND8]](s1), [[UV2]], [[C2]]
; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL7]](f32)
- ; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT16]](f32)
+ ; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](f32)
; GFX9-NEXT: [[AND9:%[0-9]+]]:_(i32) = G_AND [[BITCAST6]], [[C10]]
; GFX9-NEXT: [[AND10:%[0-9]+]]:_(i32) = G_AND [[BITCAST7]], [[C9]]
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(i32) = disjoint G_OR [[AND9]], [[AND10]]
; GFX9-NEXT: [[BITCAST8:%[0-9]+]]:_(f32) = G_BITCAST [[OR2]](i32)
+ ; GFX9-NEXT: [[SELECT16:%[0-9]+]]:_(f32) = G_SELECT [[AND8]](s1), [[BITCAST8]], [[FMUL7]]
; GFX9-NEXT: [[IS_FPCLASS2:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[UV2]](f32), 24
; GFX9-NEXT: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[FCMP10]], [[C11]]
; GFX9-NEXT: [[AND11:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS2]], [[XOR2]]
- ; GFX9-NEXT: [[SELECT17:%[0-9]+]]:_(f32) = G_SELECT [[AND11]](s1), [[C12]], [[BITCAST8]]
+ ; GFX9-NEXT: [[SELECT17:%[0-9]+]]:_(f32) = G_SELECT [[AND11]](s1), [[C12]], [[SELECT16]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[SELECT5]](f32), [[SELECT11]](f32), [[SELECT17]](f32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
%0:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
@@ -581,16 +581,16 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[COPY]], [[C2]]
; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
+ ; GFX6-NEXT: $vgpr0 = COPY [[SELECT4]](f32)
;
; GFX9-LABEL: name: test_fpow_f32_flags
; GFX9: liveins: $vgpr0, $vgpr1
@@ -626,16 +626,16 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[COPY]], [[C2]]
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
- ; GFX9-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[SELECT4]](f32)
%0:_(f32) = COPY $vgpr0
%1:_(f32) = COPY $vgpr1
%2:_(f32) = nnan nsz G_FPOW %0, %1
@@ -686,21 +686,21 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C2]]
; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT]](f32)
; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
; GFX6-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[FPEXT]](f32), 24
; GFX6-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
; GFX6-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
- ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[SELECT4]]
; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[SELECT5]](f32)
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
@@ -743,21 +743,21 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C2]]
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT]](f32)
; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
; GFX9-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[FPEXT]](f32), 24
; GFX9-NEXT: [[C11:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C11]]
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
; GFX9-NEXT: [[C12:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
- ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[BITCAST2]]
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C12]], [[SELECT4]]
; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[SELECT5]](f32)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
@@ -821,21 +821,21 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C3]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT]](f32)
; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX6-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST2]], [[C11]]
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST4]], [[FMUL1]]
; GFX6-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[FPEXT]](f32), 24
; GFX6-NEXT: [[C12:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C12]]
; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
; GFX6-NEXT: [[C13:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
- ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C13]], [[BITCAST4]]
+ ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C13]], [[SELECT4]]
; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[SELECT5]](f32)
; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
@@ -859,17 +859,17 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
; GFX6-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
- ; GFX6-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[FPEXT2]], [[C3]]
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
- ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT10]](f32)
+ ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT2]](f32)
; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST5]], [[C11]]
; GFX6-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[BITCAST6]], [[C10]]
; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND5]], [[AND6]]
; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX6-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[BITCAST7]], [[FMUL4]]
; GFX6-NEXT: [[IS_FPCLASS1:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[FPEXT2]](f32), 24
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[FCMP6]], [[C12]]
; GFX6-NEXT: [[AND7:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS1]], [[XOR1]]
- ; GFX6-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C13]], [[BITCAST7]]
+ ; GFX6-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C13]], [[SELECT10]]
; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[SELECT11]](f32)
; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
@@ -923,21 +923,21 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C3]]
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT]](f32)
; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST2]], [[C11]]
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST4]], [[FMUL1]]
; GFX9-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[FPEXT]](f32), 24
; GFX9-NEXT: [[C12:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FCMP2]], [[C12]]
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS]], [[XOR]]
; GFX9-NEXT: [[C13:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
- ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C13]], [[BITCAST4]]
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[C13]], [[SELECT4]]
; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[SELECT5]](f32)
; GFX9-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
; GFX9-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
@@ -961,17 +961,17 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
; GFX9-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
- ; GFX9-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[FPEXT2]], [[C3]]
; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
- ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT10]](f32)
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT2]](f32)
; GFX9-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST5]], [[C11]]
; GFX9-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[BITCAST6]], [[C10]]
; GFX9-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND5]], [[AND6]]
; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX9-NEXT: [[SELECT10:%[0-9]+]]:_(f32) = G_SELECT [[AND4]](s1), [[BITCAST7]], [[FMUL4]]
; GFX9-NEXT: [[IS_FPCLASS1:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[FPEXT2]](f32), 24
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[FCMP6]], [[C12]]
; GFX9-NEXT: [[AND7:%[0-9]+]]:_(s1) = G_AND [[IS_FPCLASS1]], [[XOR1]]
- ; GFX9-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C13]], [[BITCAST7]]
+ ; GFX9-NEXT: [[SELECT11:%[0-9]+]]:_(f32) = G_SELECT [[AND7]](s1), [[C13]], [[SELECT10]]
; GFX9-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[SELECT11]](f32)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FPTRUNC]](f16), [[FPTRUNC1]](f16)
; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
@@ -1032,16 +1032,16 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C3]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT]](f32)
; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX6-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST2]], [[C11]]
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[BITCAST4]](f32)
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST4]], [[FMUL1]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[SELECT4]](f32)
; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[TRUNC1]](f16)
; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[TRUNC3]](f16)
; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(f32) = nnan nsz G_FABS [[FPEXT2]]
@@ -1064,14 +1064,14 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
; GFX6-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
- ; GFX6-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[FPEXT2]], [[C3]]
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
- ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT9]](f32)
+ ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT2]](f32)
; GFX6-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[BITCAST5]], [[C11]]
; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST6]], [[C10]]
; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND4]], [[AND5]]
; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[BITCAST7]](f32)
+ ; GFX6-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[BITCAST7]], [[FMUL4]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[SELECT9]](f32)
; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
@@ -1124,16 +1124,16 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C3]]
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT]](f32)
; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST2]], [[C11]]
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C10]]
; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
- ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[BITCAST4]](f32)
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST4]], [[FMUL1]]
+ ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[SELECT4]](f32)
; GFX9-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[TRUNC1]](f16)
; GFX9-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = nnan nsz G_FPEXT [[TRUNC3]](f16)
; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(f32) = nnan nsz G_FABS [[FPEXT2]]
@@ -1156,14 +1156,14 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL5]]
; GFX9-NEXT: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC3]](f32), [[FMUL5]]
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
- ; GFX9-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[FPEXT2]], [[C3]]
; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL4]](f32)
- ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT9]](f32)
+ ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT2]](f32)
; GFX9-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[BITCAST5]], [[C11]]
; GFX9-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[BITCAST6]], [[C10]]
; GFX9-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND4]], [[AND5]]
; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
- ; GFX9-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[BITCAST7]](f32)
+ ; GFX9-NEXT: [[SELECT9:%[0-9]+]]:_(f32) = G_SELECT [[AND3]](s1), [[BITCAST7]], [[FMUL4]]
+ ; GFX9-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = nnan nsz G_FPTRUNC [[SELECT9]](f32)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FPTRUNC]](f16), [[FPTRUNC1]](f16)
; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
%0:_(<2 x f16>) = COPY $vgpr0
@@ -1192,23 +1192,23 @@ body: |
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan ninf G_FMUL [[FABS]], [[SELECT]]
- ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[FABS]], [[SELECT]]
+ ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
- ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan ninf G_FSUB [[INT]], [[SELECT1]]
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT1]](f32), [[FSUB]](f32)
+ ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+ ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan G_FSUB [[INT]], [[SELECT1]]
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT1]](f32), [[FSUB]](f32)
; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan ninf G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
- ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan ninf G_FADD [[INT1]], [[SELECT2]]
- ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[INT1]], [[SELECT2]]
+ ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
; GFX6-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
- ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan ninf G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan G_FMUL [[INT2]], [[SELECT3]]
; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT1]]
; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[FPEXT1]]
; GFX6-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
@@ -1216,16 +1216,16 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C2]]
; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT]](f32)
; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan ninf G_FPTRUNC [[BITCAST2]](f32)
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan ninf G_FPTRUNC [[SELECT4]](f32)
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
@@ -1243,23 +1243,23 @@ body: |
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan ninf G_FMUL [[FABS]], [[SELECT]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[FABS]], [[SELECT]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan ninf G_FSUB [[INT]], [[SELECT1]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT1]](f32), [[FSUB]](f32)
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan G_FSUB [[INT]], [[SELECT1]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT1]](f32), [[FSUB]](f32)
; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan ninf G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
- ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan ninf G_FADD [[INT1]], [[SELECT2]]
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = nnan ninf G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[INT1]], [[SELECT2]]
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
; GFX9-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
- ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan ninf G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan ninf G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan G_FMUL [[INT2]], [[SELECT3]]
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT1]]
; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[INTRINSIC_TRUNC]](f32), [[FPEXT1]]
; GFX9-NEXT: [[C8:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
@@ -1267,16 +1267,16 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C2]]
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT]](f32)
; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
- ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan ninf G_FPTRUNC [[BITCAST2]](f32)
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
+ ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan ninf G_FPTRUNC [[SELECT4]](f32)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
%0:_(i32) = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
index 51bbf22b94ce9..8a5dcc4e2856e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
@@ -47,16 +47,16 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C2]]
; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT]](f32)
; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[BITCAST2]](f32)
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[SELECT4]](f32)
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
@@ -97,16 +97,16 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[FPEXT]], [[C2]]
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[FPEXT]](f32)
; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
- ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[BITCAST2]](f32)
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
+ ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[SELECT4]](f32)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
%0:_(i32) = COPY $vgpr0
@@ -158,16 +158,16 @@ body: |
; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[COPY]], [[C2]]
; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX6-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX6-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
+ ; GFX6-NEXT: $vgpr0 = COPY [[SELECT4]](f32)
;
; GFX9-LABEL: name: test_fpowi_f32_i32_flags
; GFX9: liveins: $vgpr0, $vgpr1
@@ -204,16 +204,16 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FMUL2]]
; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[INTRINSIC_TRUNC1]](f32), [[FMUL2]]
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
- ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[COPY]], [[C2]]
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMUL1]](f32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT4]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX9-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C10]]
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C9]]
; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND1]], [[AND2]]
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
- ; GFX9-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[AND]](s1), [[BITCAST2]], [[FMUL1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[SELECT4]](f32)
%0:_(f32) = COPY $vgpr0
%1:_(i32) = COPY $vgpr1
%2:_(f32) = nnan G_FPOWI %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
index 757c261488ed1..40678dbc7ff8d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
@@ -34,13 +34,13 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX7-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX7-NEXT: v_trunc_f32_e32 v3, v1
; GFX7-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX7-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v3
; GFX7-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX7-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX7-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX7-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX7-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX7-NEXT: v_or_b32_e32 v1, v2, v1
; GFX7-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX7-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -76,13 +76,13 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX8-NEXT: v_trunc_f32_e32 v3, v1
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -97,40 +97,41 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v3
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, s1
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v6, v3
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -142,40 +143,41 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v2, |v0|, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v2, v2
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v3
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, s1
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v0, 24
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v6, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%l.cast = bitcast i16 %l to half
@@ -213,13 +215,13 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX7-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX7-NEXT: v_trunc_f32_e32 v3, v1
; GFX7-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX7-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v3
; GFX7-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX7-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX7-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX7-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX7-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX7-NEXT: v_or_b32_e32 v1, v2, v1
; GFX7-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX7-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -253,13 +255,13 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1
; GFX8-NEXT: v_trunc_f32_e32 v3, v1
; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 1.0, v0, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -270,40 +272,40 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
; GFX11-NEXT: v_trunc_f32_e32 v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
-; GFX11-NEXT: v_trunc_f32_e32 v6, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v6, v3
-; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_and_b32 vcc_lo, s0, s1
-; GFX11-NEXT: v_cmp_class_f32_e64 s1, v0, 24
-; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX11-NEXT: s_xor_b32 s0, s0, exec_lo
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT: s_and_b32 s0, s1, s0
+; GFX11-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v6, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v3
-; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0
+; GFX11-NEXT: s_xor_b32 s0, vcc_lo, exec_lo
+; GFX11-NEXT: s_and_b32 s0, s2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 %r)
diff --git a/llvm/test/CodeGen/AMDGPU/fpow.ll b/llvm/test/CodeGen/AMDGPU/fpow.ll
index 21d5cbd612572..3b2263fa47a30 100644
--- a/llvm/test/CodeGen/AMDGPU/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/fpow.ll
@@ -27,19 +27,19 @@ define float @v_pow_f32(float %x, float %y) {
; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
; GFX6-NEXT: v_exp_f32_e32 v2, v2
; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_mul_f32_e32 v4, 0.5, v1
; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_trunc_f32_e32 v5, v4
; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
-; GFX6-NEXT: v_mul_f32_e32 v3, 0.5, v1
-; GFX6-NEXT: v_trunc_f32_e32 v4, v3
-; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX6-NEXT: v_trunc_f32_e32 v3, v1
-; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
-; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
; GFX6-NEXT: s_brev_b32 s4, -2
-; GFX6-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX6-NEXT: v_trunc_f32_e32 v4, v1
+; GFX6-NEXT: v_bfi_b32 v3, s4, v2, v0
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, v1
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -64,19 +64,19 @@ define float @v_pow_f32(float %x, float %y) {
; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
; GFX8-NEXT: v_exp_f32_e32 v2, v2
; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_mul_f32_e32 v4, 0.5, v1
; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_trunc_f32_e32 v5, v4
; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v1
-; GFX8-NEXT: v_trunc_f32_e32 v4, v3
-; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX8-NEXT: v_trunc_f32_e32 v3, v1
-; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
-; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
; GFX8-NEXT: s_brev_b32 s4, -2
-; GFX8-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX8-NEXT: v_trunc_f32_e32 v4, v1
+; GFX8-NEXT: v_bfi_b32 v3, s4, v2, v0
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -101,19 +101,19 @@ define float @v_pow_f32(float %x, float %y) {
; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
; GFX9-NEXT: v_exp_f32_e32 v2, v2
; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_mul_f32_e32 v4, 0.5, v1
; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_trunc_f32_e32 v5, v4
; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX9-NEXT: v_mul_f32_e32 v3, 0.5, v1
-; GFX9-NEXT: v_trunc_f32_e32 v4, v3
-; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX9-NEXT: v_trunc_f32_e32 v3, v1
-; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
-; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX9-NEXT: v_trunc_f32_e32 v4, v1
+; GFX9-NEXT: v_bfi_b32 v3, s4, v2, v0
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, v1
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -138,19 +138,19 @@ define float @v_pow_f32(float %x, float %y) {
; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
; GFX90A-NEXT: v_exp_f32_e32 v2, v2
; GFX90A-NEXT: v_not_b32_e32 v3, 63
+; GFX90A-NEXT: v_mul_f32_e32 v4, 0.5, v1
; GFX90A-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX90A-NEXT: v_trunc_f32_e32 v5, v4
; GFX90A-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX90A-NEXT: v_mul_f32_e32 v3, 0.5, v1
-; GFX90A-NEXT: v_trunc_f32_e32 v4, v3
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX90A-NEXT: v_trunc_f32_e32 v3, v1
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
-; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
; GFX90A-NEXT: s_brev_b32 s4, -2
-; GFX90A-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v1
+; GFX90A-NEXT: v_bfi_b32 v3, s4, v2, v0
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, v1
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
; GFX90A-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -160,29 +160,29 @@ define float @v_pow_f32(float %x, float %y) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
-; GFX10-NEXT: v_trunc_f32_e32 v4, v1
+; GFX10-NEXT: v_trunc_f32_e32 v6, v1
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v4, v1
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v6, v1
+; GFX10-NEXT: v_cmp_neq_f32_e64 s5, v6, v1
; GFX10-NEXT: v_ldexp_f32 v3, |v0|, v3
; GFX10-NEXT: v_log_f32_e32 v3, v3
; GFX10-NEXT: v_sub_f32_e32 v2, v3, v2
; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX10-NEXT: v_exp_f32_e32 v2, v2
; GFX10-NEXT: v_trunc_f32_e32 v5, v3
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
-; GFX10-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v4
; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
-; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX10-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v4, v1
-; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
-; GFX10-NEXT: s_and_b32 s4, s4, vcc_lo
+; GFX10-NEXT: s_and_b32 s4, s6, s5
+; GFX10-NEXT: v_bfi_b32 v3, 0x7fffffff, v2, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -190,12 +190,14 @@ define float @v_pow_f32(float %x, float %y) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-NEXT: v_trunc_f32_e32 v4, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_trunc_f32_e32 v6, v1
+; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
-; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v4, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v6, v1
+; GFX11-NEXT: v_cmp_neq_f32_e64 s1, v6, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v3, |v0|, v3
; GFX11-NEXT: v_log_f32_e32 v3, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -204,7 +206,7 @@ define float @v_pow_f32(float %x, float %y) {
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
; GFX11-NEXT: v_exp_f32_e32 v2, v2
@@ -212,15 +214,13 @@ define float @v_pow_f32(float %x, float %y) {
; GFX11-NEXT: v_trunc_f32_e32 v5, v3
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v4
; GFX11-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
-; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX11-NEXT: v_cmp_neq_f32_e32 vcc_lo, v4, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
-; GFX11-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s0, s2, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_bfi_b32 v3, 0x7fffffff, v2, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call float @llvm.pow.f32(float %x, float %y)
@@ -246,26 +246,26 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
; GFX6-NEXT: v_add_f32_e32 v5, v5, v7
; GFX6-NEXT: v_exp_f32_e32 v5, v5
+; GFX6-NEXT: v_mul_f32_e32 v9, 0.5, v2
; GFX6-NEXT: v_not_b32_e32 v7, 63
+; GFX6-NEXT: v_trunc_f32_e32 v10, v9
; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX6-NEXT: s_brev_b32 s9, -2
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v10, v9
+; GFX6-NEXT: v_trunc_f32_e32 v9, v2
; GFX6-NEXT: v_ldexp_f32_e32 v5, v5, v8
-; GFX6-NEXT: v_mul_f32_e32 v8, 0.5, v2
-; GFX6-NEXT: v_trunc_f32_e32 v9, v8
-; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v9, v8
-; GFX6-NEXT: v_trunc_f32_e32 v8, v2
-; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v8, v2
+; GFX6-NEXT: s_brev_b32 s9, -2
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v9, v2
+; GFX6-NEXT: v_bfi_b32 v8, s9, v5, v0
; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v9, 1.0, v0, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s6
-; GFX6-NEXT: v_bfi_b32 v5, s9, v5, v9
-; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, 32, vcc
-; GFX6-NEXT: v_ldexp_f32_e64 v9, |v1|, v9
-; GFX6-NEXT: v_log_f32_e32 v9, v9
+; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v8, |v1|, v8
+; GFX6-NEXT: v_log_f32_e32 v8, v8
; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v0, 24
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v8, v2
-; GFX6-NEXT: v_sub_f32_e32 v0, v9, v4
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v9, v2
+; GFX6-NEXT: v_sub_f32_e32 v0, v8, v4
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v3, v0
; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v0
; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[4:5]
@@ -273,19 +273,19 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX6-NEXT: v_exp_f32_e32 v4, v0
; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX6-NEXT: v_mul_f32_e32 v6, 0.5, v3
; GFX6-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX6-NEXT: v_trunc_f32_e32 v7, v6
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v7, v6
+; GFX6-NEXT: v_trunc_f32_e32 v6, v3
; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v5
-; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v3
-; GFX6-NEXT: v_trunc_f32_e32 v6, v5
-; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
-; GFX6-NEXT: v_trunc_f32_e32 v5, v3
-; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v3
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v6, v3
+; GFX6-NEXT: v_bfi_b32 v5, s9, v4, v1
; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v5, v3
-; GFX6-NEXT: v_bfi_b32 v4, s9, v4, v6
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v6, v3
; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -308,26 +308,26 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
; GFX8-NEXT: v_add_f32_e32 v5, v5, v7
; GFX8-NEXT: v_exp_f32_e32 v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v9, 0.5, v2
; GFX8-NEXT: v_not_b32_e32 v7, 63
+; GFX8-NEXT: v_trunc_f32_e32 v10, v9
; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX8-NEXT: s_brev_b32 s9, -2
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v10, v9
+; GFX8-NEXT: v_trunc_f32_e32 v9, v2
; GFX8-NEXT: v_ldexp_f32 v5, v5, v8
-; GFX8-NEXT: v_mul_f32_e32 v8, 0.5, v2
-; GFX8-NEXT: v_trunc_f32_e32 v9, v8
-; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v9, v8
-; GFX8-NEXT: v_trunc_f32_e32 v8, v2
-; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v8, v2
+; GFX8-NEXT: s_brev_b32 s9, -2
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v9, v2
+; GFX8-NEXT: v_bfi_b32 v8, s9, v5, v0
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v9, 1.0, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s6
-; GFX8-NEXT: v_bfi_b32 v5, s9, v5, v9
-; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 32, vcc
-; GFX8-NEXT: v_ldexp_f32 v9, |v1|, v9
-; GFX8-NEXT: v_log_f32_e32 v9, v9
+; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v8, |v1|, v8
+; GFX8-NEXT: v_log_f32_e32 v8, v8
; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v0, 24
-; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v8, v2
-; GFX8-NEXT: v_sub_f32_e32 v0, v9, v4
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v9, v2
+; GFX8-NEXT: v_sub_f32_e32 v0, v8, v4
; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v3, v0
; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v0
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[4:5]
@@ -335,19 +335,19 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX8-NEXT: v_exp_f32_e32 v4, v0
; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX8-NEXT: v_mul_f32_e32 v6, 0.5, v3
; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX8-NEXT: v_trunc_f32_e32 v7, v6
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v7, v6
+; GFX8-NEXT: v_trunc_f32_e32 v6, v3
; GFX8-NEXT: v_ldexp_f32 v4, v4, v5
-; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v3
-; GFX8-NEXT: v_trunc_f32_e32 v6, v5
-; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
-; GFX8-NEXT: v_trunc_f32_e32 v5, v3
-; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v3
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v6, v3
+; GFX8-NEXT: v_bfi_b32 v5, s9, v4, v1
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
-; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v5, v3
-; GFX8-NEXT: v_bfi_b32 v4, s9, v4, v6
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v6, v3
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -370,26 +370,26 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
; GFX9-NEXT: v_add_f32_e32 v5, v5, v7
; GFX9-NEXT: v_exp_f32_e32 v5, v5
+; GFX9-NEXT: v_mul_f32_e32 v9, 0.5, v2
; GFX9-NEXT: v_not_b32_e32 v7, 63
+; GFX9-NEXT: v_trunc_f32_e32 v10, v9
; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX9-NEXT: s_brev_b32 s9, -2
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v10, v9
+; GFX9-NEXT: v_trunc_f32_e32 v9, v2
; GFX9-NEXT: v_ldexp_f32 v5, v5, v8
-; GFX9-NEXT: v_mul_f32_e32 v8, 0.5, v2
-; GFX9-NEXT: v_trunc_f32_e32 v9, v8
-; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v9, v8
-; GFX9-NEXT: v_trunc_f32_e32 v8, v2
-; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v8, v2
+; GFX9-NEXT: s_brev_b32 s9, -2
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v9, v2
+; GFX9-NEXT: v_bfi_b32 v8, s9, v5, v0
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v9, 1.0, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s6
-; GFX9-NEXT: v_bfi_b32 v5, s9, v5, v9
-; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 32, vcc
-; GFX9-NEXT: v_ldexp_f32 v9, |v1|, v9
-; GFX9-NEXT: v_log_f32_e32 v9, v9
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v8, |v1|, v8
+; GFX9-NEXT: v_log_f32_e32 v8, v8
; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v0, 24
-; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v8, v2
-; GFX9-NEXT: v_sub_f32_e32 v0, v9, v4
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v9, v2
+; GFX9-NEXT: v_sub_f32_e32 v0, v8, v4
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v3, v0
; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v0
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[4:5]
@@ -397,19 +397,19 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX9-NEXT: v_exp_f32_e32 v4, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX9-NEXT: v_mul_f32_e32 v6, 0.5, v3
; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX9-NEXT: v_trunc_f32_e32 v7, v6
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v7, v6
+; GFX9-NEXT: v_trunc_f32_e32 v6, v3
; GFX9-NEXT: v_ldexp_f32 v4, v4, v5
-; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v3
-; GFX9-NEXT: v_trunc_f32_e32 v6, v5
-; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
-; GFX9-NEXT: v_trunc_f32_e32 v5, v3
-; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v3
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v6, v3
+; GFX9-NEXT: v_bfi_b32 v5, s9, v4, v1
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
-; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v5, v3
-; GFX9-NEXT: v_bfi_b32 v4, s9, v4, v6
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v6, v3
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -432,26 +432,26 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX90A-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
; GFX90A-NEXT: v_add_f32_e32 v5, v5, v7
; GFX90A-NEXT: v_exp_f32_e32 v5, v5
+; GFX90A-NEXT: v_mul_f32_e32 v9, 0.5, v2
; GFX90A-NEXT: v_not_b32_e32 v7, 63
+; GFX90A-NEXT: v_trunc_f32_e32 v10, v9
; GFX90A-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX90A-NEXT: s_brev_b32 s9, -2
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v10, v9
+; GFX90A-NEXT: v_trunc_f32_e32 v9, v2
; GFX90A-NEXT: v_ldexp_f32 v5, v5, v8
-; GFX90A-NEXT: v_mul_f32_e32 v8, 0.5, v2
-; GFX90A-NEXT: v_trunc_f32_e32 v9, v8
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v9, v8
-; GFX90A-NEXT: v_trunc_f32_e32 v8, v2
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v8, v2
+; GFX90A-NEXT: s_brev_b32 s9, -2
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v9, v2
+; GFX90A-NEXT: v_bfi_b32 v8, s9, v5, v0
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v9, 1.0, v0, vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s6
-; GFX90A-NEXT: v_bfi_b32 v5, s9, v5, v9
-; GFX90A-NEXT: v_cndmask_b32_e64 v9, 0, 32, vcc
-; GFX90A-NEXT: v_ldexp_f32 v9, |v1|, v9
-; GFX90A-NEXT: v_log_f32_e32 v9, v9
+; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v8, |v1|, v8
+; GFX90A-NEXT: v_log_f32_e32 v8, v8
; GFX90A-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v0, 24
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v8, v2
-; GFX90A-NEXT: v_sub_f32_e32 v0, v9, v4
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v9, v2
+; GFX90A-NEXT: v_sub_f32_e32 v0, v8, v4
; GFX90A-NEXT: v_mul_legacy_f32 v0, v3, v0
; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v0
; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[4:5]
@@ -459,19 +459,19 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX90A-NEXT: v_exp_f32_e32 v4, v0
; GFX90A-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX90A-NEXT: v_mul_f32_e32 v6, 0.5, v3
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX90A-NEXT: v_trunc_f32_e32 v7, v6
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v7, v6
+; GFX90A-NEXT: v_trunc_f32_e32 v6, v3
; GFX90A-NEXT: v_ldexp_f32 v4, v4, v5
-; GFX90A-NEXT: v_mul_f32_e32 v5, 0.5, v3
-; GFX90A-NEXT: v_trunc_f32_e32 v6, v5
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
-; GFX90A-NEXT: v_trunc_f32_e32 v5, v3
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v3
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v6, v3
+; GFX90A-NEXT: v_bfi_b32 v5, s9, v4, v1
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v5, v3
-; GFX90A-NEXT: v_bfi_b32 v4, s9, v4, v6
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v6, v3
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -481,53 +481,53 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v1|
-; GFX10-NEXT: v_mul_f32_e32 v10, 0.5, v3
-; GFX10-NEXT: v_cmp_class_f32_e64 s8, v0, 24
+; GFX10-NEXT: v_mul_f32_e32 v8, 0.5, v3
+; GFX10-NEXT: v_trunc_f32_e32 v9, v3
+; GFX10-NEXT: v_cmp_class_f32_e64 s9, v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 32, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 32, s5
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s4
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s5
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v9, v3
; GFX10-NEXT: v_ldexp_f32 v5, |v0|, v5
; GFX10-NEXT: v_ldexp_f32 v7, |v1|, v7
+; GFX10-NEXT: v_cmp_class_f32_e64 s10, v1, 24
+; GFX10-NEXT: v_cmp_neq_f32_e64 s8, v9, v3
; GFX10-NEXT: v_log_f32_e32 v5, v5
; GFX10-NEXT: v_log_f32_e32 v7, v7
; GFX10-NEXT: v_sub_f32_e32 v4, v5, v4
; GFX10-NEXT: v_sub_f32_e32 v5, v7, v6
-; GFX10-NEXT: v_mul_f32_e32 v6, 0.5, v2
-; GFX10-NEXT: v_trunc_f32_e32 v7, v2
; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v2, v4
; GFX10-NEXT: v_mul_legacy_f32_e32 v5, v3, v5
-; GFX10-NEXT: v_trunc_f32_e32 v11, v6
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v7, v2
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v5
-; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v11, v6
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v4, v4, v8
-; GFX10-NEXT: v_add_f32_e32 v5, v5, v9
-; GFX10-NEXT: v_trunc_f32_e32 v8, v3
-; GFX10-NEXT: v_trunc_f32_e32 v9, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v6
+; GFX10-NEXT: v_add_f32_e32 v5, v5, v7
+; GFX10-NEXT: v_mul_f32_e32 v6, 0.5, v2
+; GFX10-NEXT: v_trunc_f32_e32 v7, v2
; GFX10-NEXT: v_exp_f32_e32 v4, v4
; GFX10-NEXT: v_exp_f32_e32 v5, v5
-; GFX10-NEXT: v_cmp_eq_f32_e64 s7, v8, v3
-; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v9, v10
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0xffffffc0, s4
-; GFX10-NEXT: s_and_b32 s4, s5, s6
-; GFX10-NEXT: v_cmp_class_f32_e64 s5, v1, 24
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 1.0, v0, s4
-; GFX10-NEXT: s_and_b32 vcc_lo, s7, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f32_e64 s4, v8, v3
-; GFX10-NEXT: v_ldexp_f32 v4, v4, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc_lo
-; GFX10-NEXT: v_ldexp_f32 v5, v5, v9
-; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v7, v2
-; GFX10-NEXT: s_and_b32 s4, s5, s4
-; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
-; GFX10-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v6
-; GFX10-NEXT: s_and_b32 s6, s8, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s6
+; GFX10-NEXT: v_trunc_f32_e32 v11, v6
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v2
+; GFX10-NEXT: v_cmp_neq_f32_e64 s4, v7, v2
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v11, v6
+; GFX10-NEXT: s_and_b32 s4, s9, s4
+; GFX10-NEXT: v_ldexp_f32 v2, v4, v10
+; GFX10-NEXT: v_trunc_f32_e32 v4, v8
+; GFX10-NEXT: v_ldexp_f32 v5, v5, v12
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s6
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX10-NEXT: v_cmp_lg_f32_e64 s7, v4, v8
+; GFX10-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX10-NEXT: s_and_b32 vcc_lo, s5, s7
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
+; GFX10-NEXT: s_and_b32 s4, s10, s8
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -536,60 +536,61 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v1|
-; GFX11-NEXT: v_mul_f32_e32 v10, 0.5, v3
-; GFX11-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cmp_class_f32_e64 s6, v1, 24
+; GFX11-NEXT: v_mul_f32_e32 v8, 0.5, v3
+; GFX11-NEXT: v_trunc_f32_e32 v9, v3
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 32, s1
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cmp_class_f32_e64 s5, v0, 24
; GFX11-NEXT: v_ldexp_f32 v5, |v0|, v5
; GFX11-NEXT: v_ldexp_f32 v7, |v1|, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v9, v3
+; GFX11-NEXT: v_cmp_neq_f32_e64 s4, v9, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_log_f32_e32 v5, v5
; GFX11-NEXT: v_log_f32_e32 v7, v7
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_sub_f32 v4, v5, v4 :: v_dual_sub_f32 v5, v7, v6
-; GFX11-NEXT: v_trunc_f32_e32 v7, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_dual_mul_dx9_zero_f32 v4, v2, v4 :: v_dual_mul_dx9_zero_f32 v5, v3, v5
-; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v7, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
-; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v5
-; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s0
-; GFX11-NEXT: v_mul_f32_e32 v6, 0.5, v2
-; GFX11-NEXT: v_dual_add_f32 v4, v4, v8 :: v_dual_add_f32 v5, v5, v9
-; GFX11-NEXT: v_trunc_f32_e32 v8, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_trunc_f32_e32 v11, v6
-; GFX11-NEXT: v_trunc_f32_e32 v9, v10
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v5
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v12, 0, 0xffffffc0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_add_f32 v5, v5, v7
+; GFX11-NEXT: v_trunc_f32_e32 v7, v2
; GFX11-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v5, v5
-; GFX11-NEXT: v_cmp_eq_f32_e64 s3, v8, v3
+; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v2
+; GFX11-NEXT: v_cmp_neq_f32_e64 s0, v7, v2
+; GFX11-NEXT: s_and_b32 s0, s5, s0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v5, v5, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v1
+; GFX11-NEXT: v_mul_f32_e32 v6, 0.5, v2
+; GFX11-NEXT: v_ldexp_f32 v2, v4, v10
+; GFX11-NEXT: v_trunc_f32_e32 v4, v8
+; GFX11-NEXT: v_trunc_f32_e32 v11, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX11-NEXT: v_cmp_lg_f32_e64 s3, v4, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_lg_f32_e64 s2, v11, v6
-; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v9, v10
-; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, 0xffffffc0, s0
-; GFX11-NEXT: s_and_b32 s0, s1, s2
-; GFX11-NEXT: v_cmp_class_f32_e64 s1, v1, 24
-; GFX11-NEXT: s_and_b32 vcc_lo, s3, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 1.0, v0, s0
-; GFX11-NEXT: v_ldexp_f32 v4, v4, v6
-; GFX11-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc_lo
-; GFX11-NEXT: v_ldexp_f32 v5, v5, v9
-; GFX11-NEXT: v_cmp_neq_f32_e32 vcc_lo, v7, v2
-; GFX11-NEXT: v_cmp_neq_f32_e64 s0, v8, v3
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v6
-; GFX11-NEXT: s_and_b32 s2, s4, vcc_lo
-; GFX11-NEXT: s_and_b32 s0, s1, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: s_and_b32 vcc_lo, vcc_lo, s2
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-NEXT: s_and_b32 vcc_lo, s1, s3
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-NEXT: s_and_b32 s0, s6, s4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y)
@@ -610,6 +611,7 @@ define half @v_pow_f16(half %x, half %y) {
; GFX6-NEXT: v_log_f32_e32 v3, v3
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX6-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX6-NEXT: v_mul_f32_e32 v4, 0.5, v1
; GFX6-NEXT: v_sub_f32_e32 v2, v3, v2
; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
@@ -619,18 +621,17 @@ define half @v_pow_f16(half %x, half %y) {
; GFX6-NEXT: v_exp_f32_e32 v2, v2
; GFX6-NEXT: v_not_b32_e32 v3, 63
; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_trunc_f32_e32 v5, v4
; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
-; GFX6-NEXT: v_mul_f32_e32 v3, 0.5, v1
-; GFX6-NEXT: v_trunc_f32_e32 v4, v3
-; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX6-NEXT: v_trunc_f32_e32 v3, v1
-; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
-; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
; GFX6-NEXT: s_brev_b32 s4, -2
-; GFX6-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX6-NEXT: v_trunc_f32_e32 v4, v1
+; GFX6-NEXT: v_bfi_b32 v3, s4, v2, v0
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, v1
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -640,154 +641,158 @@ define half @v_pow_f16(half %x, half %y) {
; GFX8-LABEL: v_pow_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX8-NEXT: s_mov_b32 s4, 0x800000
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
-; GFX8-NEXT: v_ldexp_f32 v3, |v0|, v3
-; GFX8-NEXT: v_log_f32_e32 v3, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
-; GFX8-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000
-; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX8-NEXT: v_exp_f32_e32 v2, v2
-; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX8-NEXT: v_log_f32_e32 v4, v4
; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v1
-; GFX8-NEXT: v_trunc_f32_e32 v4, v3
-; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX8-NEXT: v_trunc_f32_e32 v3, v1
-; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
-; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_sub_f32_e32 v3, v4, v3
+; GFX8-NEXT: v_mul_legacy_f32_e32 v3, v1, v3
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX8-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX8-NEXT: v_exp_f32_e32 v3, v3
+; GFX8-NEXT: v_not_b32_e32 v4, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX8-NEXT: s_brev_b32 s4, -2
-; GFX8-NEXT: v_bfi_b32 v2, s4, v2, v4
-; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: v_ldexp_f32 v3, v3, v4
+; GFX8-NEXT: v_mul_f32_e32 v4, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v5, v4
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX8-NEXT: v_trunc_f32_e32 v4, v1
+; GFX8-NEXT: v_bfi_b32 v0, s4, v3, v0
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, v1
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX9-NEXT: s_mov_b32 s4, 0x800000
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
-; GFX9-NEXT: v_ldexp_f32 v3, |v0|, v3
-; GFX9-NEXT: v_log_f32_e32 v3, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX9-NEXT: s_mov_b32 s4, 0xc2fc0000
-; GFX9-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX9-NEXT: v_exp_f32_e32 v2, v2
-; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX9-NEXT: v_log_f32_e32 v4, v4
; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX9-NEXT: v_mul_f32_e32 v3, 0.5, v1
-; GFX9-NEXT: v_trunc_f32_e32 v4, v3
-; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX9-NEXT: v_trunc_f32_e32 v3, v1
-; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
-; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_sub_f32_e32 v3, v4, v3
+; GFX9-NEXT: v_mul_legacy_f32_e32 v3, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX9-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX9-NEXT: v_exp_f32_e32 v3, v3
+; GFX9-NEXT: v_not_b32_e32 v4, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: v_bfi_b32 v2, s4, v2, v4
-; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: v_ldexp_f32 v3, v3, v4
+; GFX9-NEXT: v_mul_f32_e32 v4, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v5, v4
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX9-NEXT: v_trunc_f32_e32 v4, v1
+; GFX9-NEXT: v_bfi_b32 v0, s4, v3, v0
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, v1
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_f16:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX90A-NEXT: s_mov_b32 s4, 0x800000
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v4, v1
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
-; GFX90A-NEXT: v_ldexp_f32 v3, |v0|, v3
-; GFX90A-NEXT: v_log_f32_e32 v3, v3
-; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX90A-NEXT: s_mov_b32 s4, 0xc2fc0000
-; GFX90A-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX90A-NEXT: v_mul_legacy_f32 v2, v4, v2
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0x42800000
-; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s4
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX90A-NEXT: v_log_f32_e32 v4, v4
; GFX90A-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX90A-NEXT: v_exp_f32_e32 v2, v2
-; GFX90A-NEXT: v_not_b32_e32 v3, 63
+; GFX90A-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX90A-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX90A-NEXT: v_sub_f32_e32 v3, v4, v3
+; GFX90A-NEXT: v_mul_legacy_f32 v3, v5, v3
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s4, v3
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX90A-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX90A-NEXT: v_exp_f32_e32 v3, v3
+; GFX90A-NEXT: v_not_b32_e32 v4, 63
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX90A-NEXT: s_brev_b32 s4, -2
+; GFX90A-NEXT: v_ldexp_f32 v3, v3, v4
+; GFX90A-NEXT: v_bfi_b32 v0, s4, v3, v0
; GFX90A-NEXT: s_mov_b32 s4, 0.5
-; GFX90A-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
; GFX90A-NEXT: v_fma_mix_f32 v1, v1, s4, neg(0) op_sel_hi:[1,0,0]
-; GFX90A-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX90A-NEXT: v_trunc_f32_e32 v3, v1
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1
-; GFX90A-NEXT: v_trunc_f32_e32 v1, v4
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v4
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v1
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v1, v5
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v5
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc
-; GFX90A-NEXT: s_brev_b32 s4, -2
-; GFX90A-NEXT: v_bfi_b32 v2, s4, v2, v3
-; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v4
-; GFX90A-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v5
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0x7fc00000
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v1
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
-; GFX10-NEXT: v_trunc_f32_e32 v5, v4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX10-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
+; GFX10-NEXT: v_trunc_f32_e32 v7, v5
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v2, 24
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4
; GFX10-NEXT: s_mov_b32 s4, 0.5
+; GFX10-NEXT: v_cmp_neq_f32_e64 s5, v7, v5
; GFX10-NEXT: v_fma_mix_f32 v1, v1, s4, neg(0) op_sel_hi:[1,0,0]
-; GFX10-NEXT: v_ldexp_f32 v3, |v0|, v3
-; GFX10-NEXT: v_log_f32_e32 v3, v3
-; GFX10-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v4, v2
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_trunc_f32_e32 v3, v1
-; GFX10-NEXT: v_exp_f32_e32 v2, v2
-; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v3, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
-; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX10-NEXT: v_ldexp_f32 v1, v2, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v5, v4
-; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v2
-; GFX10-NEXT: s_and_b32 s4, s4, vcc_lo
+; GFX10-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v7, v5
+; GFX10-NEXT: v_trunc_f32_e32 v6, v1
+; GFX10-NEXT: v_log_f32_e32 v4, v4
+; GFX10-NEXT: v_sub_f32_e32 v3, v4, v3
+; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v1
+; GFX10-NEXT: v_exp_f32_e32 v3, v3
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT: s_and_b32 s4, s6, s5
+; GFX10-NEXT: v_ldexp_f32 v3, v3, v4
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -795,90 +800,91 @@ define half @v_pow_f16(half %x, half %y) {
; GFX11-TRUE16-LABEL: v_pow_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 32, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0.5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, |v2|, v0
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v3|
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v3, 24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 32, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0.5
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, |v3|, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v5, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, s0, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v1
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v4, v3
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v0
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v0, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v4, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v4, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v0
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v2
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v2, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v7, v2
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s1, v7, v2
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v1
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s1
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v3, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v2, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v5, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v5
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s2, v2, 24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 32, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0.5
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s1, v7, v5
; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, s0, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v0|, v3
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v7, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v1
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v4, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v4, v2
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v3, v1
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v3, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v0, 24
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v5, v3
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v1
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, s1
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v2, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%pow = call half @llvm.pow.f16(half %x, half %y)
@@ -889,70 +895,70 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX6-LABEL: v_pow_v2f16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX6-NEXT: s_mov_b32 s8, 0x800000
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
-; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
-; GFX6-NEXT: v_ldexp_f32_e64 v7, |v3|, v7
-; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v2
-; GFX6-NEXT: v_log_f32_e32 v7, v7
-; GFX6-NEXT: v_trunc_f32_e32 v6, v5
-; GFX6-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX6-NEXT: s_mov_b32 s6, 0x800000
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v4, |v2|, v4
+; GFX6-NEXT: v_log_f32_e32 v4, v4
; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX6-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v4, v4, v6
+; GFX6-NEXT: v_mul_legacy_f32_e32 v4, v3, v4
+; GFX6-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s8, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX6-NEXT: v_add_f32_e32 v4, v4, v7
+; GFX6-NEXT: v_exp_f32_e32 v4, v4
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX6-NEXT: v_trunc_f32_e32 v4, v2
-; GFX6-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
-; GFX6-NEXT: s_mov_b32 s9, 0xc2fc0000
-; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
-; GFX6-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
-; GFX6-NEXT: v_not_b32_e32 v9, 63
-; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; GFX6-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
-; GFX6-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX6-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
-; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
-; GFX6-NEXT: v_ldexp_f32_e64 v4, |v0|, v4
-; GFX6-NEXT: v_log_f32_e32 v4, v4
+; GFX6-NEXT: v_not_b32_e32 v7, 63
+; GFX6-NEXT: v_mul_f32_e32 v10, 0.5, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX6-NEXT: v_trunc_f32_e32 v9, v3
+; GFX6-NEXT: v_trunc_f32_e32 v11, v10
+; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v8
+; GFX6-NEXT: s_brev_b32 s9, -2
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v9, v3
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v11, v10
+; GFX6-NEXT: v_bfi_b32 v8, s9, v4, v2
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s6
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v9, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e64 v5, |v0|, v5
+; GFX6-NEXT: v_log_f32_e32 v5, v5
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
-; GFX6-NEXT: v_exp_f32_e32 v6, v6
-; GFX6-NEXT: v_sub_f32_e32 v2, v4, v2
-; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
-; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
-; GFX6-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX6-NEXT: v_exp_f32_e32 v2, v2
-; GFX6-NEXT: v_ldexp_f32_e32 v6, v6, v10
-; GFX6-NEXT: s_brev_b32 s10, -2
-; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
-; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
-; GFX6-NEXT: v_bfi_b32 v6, s10, v6, v8
-; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX6-NEXT: v_sub_f32_e32 v3, v5, v3
+; GFX6-NEXT: v_mul_legacy_f32_e32 v3, v1, v3
+; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX6-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX6-NEXT: v_exp_f32_e32 v3, v3
+; GFX6-NEXT: v_mul_f32_e32 v6, 0.5, v1
; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5
-; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
-; GFX6-NEXT: v_trunc_f32_e32 v6, v5
-; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
-; GFX6-NEXT: v_trunc_f32_e32 v5, v1
-; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX6-NEXT: v_trunc_f32_e32 v7, v6
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v7, v6
+; GFX6-NEXT: v_trunc_f32_e32 v6, v1
+; GFX6-NEXT: v_ldexp_f32_e32 v3, v3, v5
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v6, v1
+; GFX6-NEXT: v_bfi_b32 v5, s9, v3, v0
; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
-; GFX6-NEXT: v_bfi_b32 v2, s10, v2, v6
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v6, v1
; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
@@ -961,206 +967,215 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX8-LABEL: v_pow_v2f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: s_mov_b32 s8, 0x800000
-; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
-; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
-; GFX8-NEXT: v_ldexp_f32 v7, |v3|, v7
-; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v2
-; GFX8-NEXT: v_log_f32_e32 v7, v7
-; GFX8-NEXT: v_trunc_f32_e32 v6, v5
-; GFX8-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: s_mov_b32 s6, 0x800000
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
-; GFX8-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX8-NEXT: v_trunc_f32_e32 v4, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
-; GFX8-NEXT: s_mov_b32 s9, 0xc2fc0000
-; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
-; GFX8-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
-; GFX8-NEXT: v_not_b32_e32 v9, 63
-; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX8-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
-; GFX8-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX8-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
-; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
-; GFX8-NEXT: v_ldexp_f32 v4, |v0|, v4
-; GFX8-NEXT: v_log_f32_e32 v4, v4
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX8-NEXT: v_log_f32_e32 v3, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX8-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX8-NEXT: v_mul_f32_e32 v10, 0.5, v4
+; GFX8-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX8-NEXT: v_mul_legacy_f32_e32 v3, v4, v3
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s8, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX8-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX8-NEXT: v_exp_f32_e32 v3, v3
+; GFX8-NEXT: v_trunc_f32_e32 v11, v10
+; GFX8-NEXT: v_not_b32_e32 v7, 63
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v11, v10
+; GFX8-NEXT: v_cvt_f32_f16_e32 v10, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX8-NEXT: v_mov_b32_e32 v8, 16
+; GFX8-NEXT: v_trunc_f32_e32 v9, v4
+; GFX8-NEXT: v_lshlrev_b32_sdwa v8, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: s_brev_b32 s9, -2
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v9, v4
+; GFX8-NEXT: v_bfi_b32 v8, s9, v3, v8
+; GFX8-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v10|, s6
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v9, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v5, |v10|, v5
+; GFX8-NEXT: v_log_f32_e32 v5, v5
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
-; GFX8-NEXT: v_exp_f32_e32 v6, v6
-; GFX8-NEXT: v_sub_f32_e32 v2, v4, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
-; GFX8-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX8-NEXT: v_exp_f32_e32 v2, v2
-; GFX8-NEXT: v_ldexp_f32 v6, v6, v10
-; GFX8-NEXT: s_brev_b32 s10, -2
-; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
-; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
-; GFX8-NEXT: v_bfi_b32 v6, s10, v6, v8
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX8-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_mul_legacy_f32_e32 v4, v1, v4
+; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX8-NEXT: v_add_f32_e32 v4, v4, v5
+; GFX8-NEXT: v_exp_f32_e32 v4, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; GFX8-NEXT: v_ldexp_f32 v4, v4, v5
; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
; GFX8-NEXT: v_trunc_f32_e32 v6, v5
; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: v_bfi_b32 v0, s9, v4, v0
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
-; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v10, 24
; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
-; GFX8-NEXT: v_bfi_b32 v2, s10, v2, v6
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; GFX8-NEXT: v_cvt_f16_f32_sdwa v4, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX8-NEXT: v_cvt_f16_f32_sdwa v3, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_v2f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: s_mov_b32 s8, 0x800000
-; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
-; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
-; GFX9-NEXT: v_ldexp_f32 v7, |v3|, v7
-; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v2
-; GFX9-NEXT: v_log_f32_e32 v7, v7
-; GFX9-NEXT: v_trunc_f32_e32 v6, v5
-; GFX9-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: s_mov_b32 s6, 0x800000
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
-; GFX9-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX9-NEXT: v_trunc_f32_e32 v4, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
-; GFX9-NEXT: s_mov_b32 s9, 0xc2fc0000
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
-; GFX9-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
-; GFX9-NEXT: v_not_b32_e32 v9, 63
-; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX9-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
-; GFX9-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX9-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
-; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
-; GFX9-NEXT: v_ldexp_f32 v4, |v0|, v4
-; GFX9-NEXT: v_log_f32_e32 v4, v4
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX9-NEXT: v_log_f32_e32 v3, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX9-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX9-NEXT: v_mul_f32_e32 v10, 0.5, v4
+; GFX9-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX9-NEXT: v_mul_legacy_f32_e32 v3, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s8, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX9-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX9-NEXT: v_exp_f32_e32 v3, v3
+; GFX9-NEXT: v_trunc_f32_e32 v11, v10
+; GFX9-NEXT: v_not_b32_e32 v7, 63
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v11, v10
+; GFX9-NEXT: v_cvt_f32_f16_e32 v10, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX9-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, 16
+; GFX9-NEXT: v_trunc_f32_e32 v9, v4
+; GFX9-NEXT: v_lshlrev_b32_sdwa v8, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: s_brev_b32 s9, -2
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v9, v4
+; GFX9-NEXT: v_bfi_b32 v8, s9, v3, v8
+; GFX9-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v10|, s6
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v9, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v5, |v10|, v5
+; GFX9-NEXT: v_log_f32_e32 v5, v5
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
-; GFX9-NEXT: v_exp_f32_e32 v6, v6
-; GFX9-NEXT: v_sub_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX9-NEXT: v_exp_f32_e32 v2, v2
-; GFX9-NEXT: v_ldexp_f32 v6, v6, v10
-; GFX9-NEXT: s_brev_b32 s10, -2
-; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
-; GFX9-NEXT: v_bfi_b32 v6, s10, v6, v8
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX9-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_mul_legacy_f32_e32 v4, v1, v4
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX9-NEXT: v_add_f32_e32 v4, v4, v5
+; GFX9-NEXT: v_exp_f32_e32 v4, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; GFX9-NEXT: v_ldexp_f32 v4, v4, v5
; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
; GFX9-NEXT: v_trunc_f32_e32 v6, v5
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: v_bfi_b32 v0, s9, v4, v0
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
-; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v10, 24
; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
-; GFX9-NEXT: v_bfi_b32 v2, s10, v2, v6
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT: v_pack_b32_f16 v0, v0, v4
+; GFX9-NEXT: v_pack_b32_f16 v0, v0, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_v2f16:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: s_mov_b32 s8, 0.5
-; GFX90A-NEXT: v_fma_mix_f32 v2, v1, s8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX90A-NEXT: s_mov_b32 s9, 0x800000
-; GFX90A-NEXT: v_trunc_f32_e32 v4, v2
-; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v5|, s9
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v2
-; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
-; GFX90A-NEXT: v_ldexp_f32 v4, |v5|, v4
-; GFX90A-NEXT: v_log_f32_e32 v4, v4
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0x42000000
-; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[4:5]
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX90A-NEXT: v_sub_f32_e32 v4, v4, v7
-; GFX90A-NEXT: v_trunc_f32_e32 v2, v3
-; GFX90A-NEXT: v_mul_legacy_f32 v4, v3, v4
-; GFX90A-NEXT: s_mov_b32 s10, 0xc2fc0000
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[6:7], v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v4
-; GFX90A-NEXT: v_not_b32_e32 v9, 63
-; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX90A-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s9
-; GFX90A-NEXT: v_add_f32_e32 v4, v4, v8
-; GFX90A-NEXT: v_cndmask_b32_e32 v8, 1.0, v5, vcc
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v2, v3
-; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, s[4:5]
-; GFX90A-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: s_mov_b32 s6, 0x800000
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v3, |v2|, v3
; GFX90A-NEXT: v_log_f32_e32 v3, v3
-; GFX90A-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v6, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX90A-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX90A-NEXT: s_mov_b32 s10, 0.5
+; GFX90A-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX90A-NEXT: v_mul_legacy_f32 v3, v4, v3
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s8, v3
+; GFX90A-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX90A-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX90A-NEXT: v_exp_f32_e32 v3, v3
+; GFX90A-NEXT: v_fma_mix_f32 v9, v1, s10, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX90A-NEXT: v_not_b32_e32 v7, 63
+; GFX90A-NEXT: v_trunc_f32_e32 v10, v9
+; GFX90A-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v10, v9
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v10, v0
+; GFX90A-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX90A-NEXT: v_mov_b32_e32 v8, 16
+; GFX90A-NEXT: v_trunc_f32_e32 v9, v4
+; GFX90A-NEXT: v_lshlrev_b32_sdwa v8, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX90A-NEXT: s_brev_b32 s9, -2
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v9, v4
+; GFX90A-NEXT: v_bfi_b32 v8, s9, v3, v8
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v10|, s6
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v9, v4
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
+; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX90A-NEXT: v_ldexp_f32 v5, |v10|, v5
+; GFX90A-NEXT: v_log_f32_e32 v5, v5
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v8, v1
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX90A-NEXT: v_fma_mix_f32 v1, v1, s10, neg(0) op_sel_hi:[1,0,0]
+; GFX90A-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX90A-NEXT: v_mul_legacy_f32 v4, v8, v4
+; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v4
+; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX90A-NEXT: v_add_f32_e32 v4, v4, v5
; GFX90A-NEXT: v_exp_f32_e32 v4, v4
-; GFX90A-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX90A-NEXT: s_brev_b32 s11, -2
-; GFX90A-NEXT: v_mul_legacy_f32 v2, v6, v2
-; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v2
-; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[4:5]
-; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX90A-NEXT: v_exp_f32_e32 v2, v2
-; GFX90A-NEXT: v_ldexp_f32 v4, v4, v10
-; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v5, 24
-; GFX90A-NEXT: v_bfi_b32 v4, s11, v4, v8
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0x7fc00000
+; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v9, s[4:5]
-; GFX90A-NEXT: v_fma_mix_f32 v1, v1, s8, neg(0) op_sel_hi:[1,0,0]
-; GFX90A-NEXT: v_ldexp_f32 v2, v2, v4
-; GFX90A-NEXT: v_trunc_f32_e32 v4, v1
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v1
-; GFX90A-NEXT: v_trunc_f32_e32 v1, v6
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v6
+; GFX90A-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX90A-NEXT: v_trunc_f32_e32 v5, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v5, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v1, v8
+; GFX90A-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v8
+; GFX90A-NEXT: v_bfi_b32 v0, s9, v4, v0
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
-; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v6
-; GFX90A-NEXT: v_bfi_b32 v2, s11, v2, v4
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v10, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v8
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX90A-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v3
@@ -1170,59 +1185,62 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_mov_b32_e32 v9, 16
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
-; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
-; GFX10-NEXT: v_trunc_f32_e32 v10, v7
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 32, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s5
-; GFX10-NEXT: s_mov_b32 s4, 0.5
-; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX10-NEXT: v_ldexp_f32 v5, |v0|, v5
-; GFX10-NEXT: v_fma_mix_f32 v8, v1, s4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v10, v7
-; GFX10-NEXT: v_log_f32_e32 v3, v3
-; GFX10-NEXT: v_log_f32_e32 v5, v5
-; GFX10-NEXT: v_trunc_f32_e32 v9, v8
-; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v9, v8
-; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
-; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v1
-; GFX10-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX10-NEXT: v_fma_mix_f32 v1, v1, s4, neg(0) op_sel_hi:[1,0,0]
-; GFX10-NEXT: s_and_b32 s5, s6, s5
-; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v7, v3
-; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
-; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
-; GFX10-NEXT: v_trunc_f32_e32 v11, v1
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v11, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, v2, s5
-; GFX10-NEXT: v_cmp_class_f32_e64 s5, v2, 24
-; GFX10-NEXT: v_add_f32_e32 v3, v3, v5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, s4
-; GFX10-NEXT: v_exp_f32_e32 v3, v3
-; GFX10-NEXT: v_add_f32_e32 v4, v4, v5
-; GFX10-NEXT: v_trunc_f32_e32 v5, v6
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v3|
+; GFX10-NEXT: v_trunc_f32_e32 v12, v8
+; GFX10-NEXT: v_lshlrev_b32_sdwa v9, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 32, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s5
+; GFX10-NEXT: s_mov_b32 s5, 0.5
+; GFX10-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX10-NEXT: v_ldexp_f32 v6, |v3|, v6
+; GFX10-NEXT: v_fma_mix_f32 v10, v1, s5, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24
+; GFX10-NEXT: v_cmp_class_f32_e64 s9, v3, 24
+; GFX10-NEXT: v_log_f32_e32 v4, v4
+; GFX10-NEXT: v_log_f32_e32 v6, v6
+; GFX10-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v1
+; GFX10-NEXT: v_sub_f32_e32 v5, v6, v5
+; GFX10-NEXT: v_fma_mix_f32 v1, v1, s5, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_neq_f32_e64 s5, v12, v8
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v8, v4
+; GFX10-NEXT: v_trunc_f32_e32 v14, v7
+; GFX10-NEXT: v_mul_legacy_f32_e32 v5, v7, v5
+; GFX10-NEXT: v_trunc_f32_e32 v13, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s7, v14, v7
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v5
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v13, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s4
; GFX10-NEXT: v_exp_f32_e32 v4, v4
-; GFX10-NEXT: v_ldexp_f32 v3, v3, v8
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v6
-; GFX10-NEXT: v_bfi_b32 v1, 0x7fffffff, v3, v1
-; GFX10-NEXT: v_ldexp_f32 v3, v4, v8
+; GFX10-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX10-NEXT: v_trunc_f32_e32 v6, v10
+; GFX10-NEXT: v_exp_f32_e32 v5, v5
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v10
+; GFX10-NEXT: v_ldexp_f32 v4, v4, v11
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v12, v8
+; GFX10-NEXT: v_bfi_b32 v6, 0x7fffffff, v4, v9
+; GFX10-NEXT: v_ldexp_f32 v5, v5, v11
; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f32_e64 s4, v5, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v10, v7
-; GFX10-NEXT: s_and_b32 s4, s6, s4
-; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v4
-; GFX10-NEXT: s_and_b32 s5, s5, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s5
+; GFX10-NEXT: s_and_b32 s4, s7, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v5, v0
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v14, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v0, s4
+; GFX10-NEXT: s_and_b32 s4, s8, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
+; GFX10-NEXT: s_and_b32 s4, s9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
@@ -1233,77 +1251,77 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v3|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0.5
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, |v0|, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v3, 24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v4|
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 32, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s6, v4, 24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, 0.5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v11, v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, |v4|, v5
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v7, v7
; GFX11-TRUE16-NEXT: v_log_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v7
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, s0, neg(0) op_sel_hi:[1,0,0]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v5
-; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v6, v7, v6 :: v_dual_sub_f32 v5, v5, v9
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v9, v1.l
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, s1, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v5, v8, v5 :: v_dual_mul_dx9_zero_f32 v6, v9, v6
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v1
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v12, v9
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s3, v12, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
-; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s4, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v3, v1
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, v5
-; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v7 :: v_dual_add_f32 v6, v6, v10
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v11
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v8
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v10, v1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v11, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v5, v3
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v6, v7
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s4, v11, v8
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s1, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s6, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1311,78 +1329,79 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v6
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0.5
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v0|, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v3|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v8, v8
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v3, 24
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v4|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 32, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s6, v4, 24
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, 0.5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v11, v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v4|, v5
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v7, v7
; GFX11-FAKE16-NEXT: v_log_f32_e32 v5, v5
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v7
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v1
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, s0, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v5
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_dual_sub_f32 v6, v7, v6 :: v_dual_sub_f32 v5, v5, v9
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v9, v1
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, s1, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v5, v8, v5 :: v_dual_mul_dx9_zero_f32 v6, v9, v6
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v9
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, v12, v9
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s3, v12, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v7
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
-; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s4, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v7 :: v_dual_add_f32 v6, v6, v10
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v11
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
-; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v6, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v11
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v8
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v10, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v11, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v5, v3
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v6, v7
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s4, v11, v8
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s6, s4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y)
@@ -1394,67 +1413,67 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT: s_mov_b32 s8, 0x800000
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
-; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
-; GFX6-NEXT: v_ldexp_f32_e64 v7, |v3|, v7
-; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v2
-; GFX6-NEXT: v_log_f32_e32 v7, v7
-; GFX6-NEXT: v_trunc_f32_e32 v6, v5
-; GFX6-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s8
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v4, |v2|, v4
+; GFX6-NEXT: v_log_f32_e32 v4, v4
; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
-; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX6-NEXT: v_trunc_f32_e32 v4, v2
-; GFX6-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
; GFX6-NEXT: s_mov_b32 s9, 0xc2fc0000
-; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
-; GFX6-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
-; GFX6-NEXT: v_not_b32_e32 v9, 63
-; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; GFX6-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
+; GFX6-NEXT: v_sub_f32_e32 v4, v4, v6
+; GFX6-NEXT: v_mul_legacy_f32_e32 v4, v3, v4
+; GFX6-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s9, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX6-NEXT: v_add_f32_e32 v4, v4, v7
+; GFX6-NEXT: v_exp_f32_e32 v4, v4
+; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX6-NEXT: v_mul_f32_e32 v10, 0.5, v3
+; GFX6-NEXT: v_not_b32_e32 v7, 63
+; GFX6-NEXT: v_trunc_f32_e32 v9, v3
+; GFX6-NEXT: v_trunc_f32_e32 v11, v10
+; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v9, v3
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v11, v10
+; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v8
+; GFX6-NEXT: s_brev_b32 s10, -2
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
-; GFX6-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX6-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
+; GFX6-NEXT: v_bfi_b32 v8, s10, v4, v2
+; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 32, s[4:5]
; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
; GFX6-NEXT: v_log_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
-; GFX6-NEXT: v_exp_f32_e32 v6, v6
-; GFX6-NEXT: v_sub_f32_e32 v2, v2, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5
; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
-; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
-; GFX6-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v5
; GFX6-NEXT: v_exp_f32_e32 v2, v2
-; GFX6-NEXT: v_ldexp_f32_e32 v6, v6, v10
-; GFX6-NEXT: s_brev_b32 s10, -2
-; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
-; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
-; GFX6-NEXT: v_bfi_b32 v6, s10, v6, v8
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v9, v3
+; GFX6-NEXT: v_mul_f32_e32 v6, 0.5, v1
; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX6-NEXT: v_trunc_f32_e32 v7, v6
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v3, vcc
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v7, v6
+; GFX6-NEXT: v_trunc_f32_e32 v6, v1
; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5
-; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
-; GFX6-NEXT: v_trunc_f32_e32 v6, v5
-; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
-; GFX6-NEXT: v_trunc_f32_e32 v5, v1
-; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v6, v1
+; GFX6-NEXT: v_bfi_b32 v5, s10, v2, v0
; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v6, v1
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX6-NEXT: v_bfi_b32 v2, s10, v2, v6
; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
@@ -1466,206 +1485,215 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX8-LABEL: v_pow_v2f16_fneg_lhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: s_mov_b32 s8, 0x800000
-; GFX8-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
-; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
-; GFX8-NEXT: v_ldexp_f32 v7, |v3|, v7
-; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v2
-; GFX8-NEXT: v_log_f32_e32 v7, v7
-; GFX8-NEXT: v_trunc_f32_e32 v6, v5
-; GFX8-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: s_mov_b32 s6, 0x800000
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
-; GFX8-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX8-NEXT: v_trunc_f32_e32 v4, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
-; GFX8-NEXT: s_mov_b32 s9, 0xc2fc0000
-; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
-; GFX8-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
-; GFX8-NEXT: v_not_b32_e32 v9, 63
-; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX8-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
-; GFX8-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX8-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
-; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
-; GFX8-NEXT: v_ldexp_f32 v4, |v0|, v4
-; GFX8-NEXT: v_log_f32_e32 v4, v4
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX8-NEXT: v_log_f32_e32 v3, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX8-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX8-NEXT: v_mul_f32_e32 v11, 0.5, v4
+; GFX8-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX8-NEXT: v_mul_legacy_f32_e32 v3, v4, v3
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s8, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX8-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX8-NEXT: v_exp_f32_e32 v3, v3
+; GFX8-NEXT: v_trunc_f32_e32 v12, v11
+; GFX8-NEXT: v_not_b32_e32 v7, 63
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v12, v11
+; GFX8-NEXT: v_cvt_f32_f16_e64 v11, -v0
+; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX8-NEXT: v_mov_b32_e32 v8, 0x8000
+; GFX8-NEXT: v_trunc_f32_e32 v10, v4
+; GFX8-NEXT: v_xor_b32_sdwa v9, v8, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: s_brev_b32 s9, -2
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v10, v4
+; GFX8-NEXT: v_bfi_b32 v9, s9, v3, v9
+; GFX8-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v11|, s6
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v10, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v5, |v11|, v5
+; GFX8-NEXT: v_log_f32_e32 v5, v5
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
-; GFX8-NEXT: v_exp_f32_e32 v6, v6
-; GFX8-NEXT: v_sub_f32_e32 v2, v4, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
-; GFX8-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX8-NEXT: v_exp_f32_e32 v2, v2
-; GFX8-NEXT: v_ldexp_f32 v6, v6, v10
-; GFX8-NEXT: s_brev_b32 s10, -2
-; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
-; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
-; GFX8-NEXT: v_bfi_b32 v6, s10, v6, v8
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX8-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_mul_legacy_f32_e32 v4, v1, v4
+; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX8-NEXT: v_add_f32_e32 v4, v4, v5
+; GFX8-NEXT: v_exp_f32_e32 v4, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; GFX8-NEXT: v_ldexp_f32 v4, v4, v5
; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
; GFX8-NEXT: v_trunc_f32_e32 v6, v5
; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_xor_b32_sdwa v0, v8, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: v_bfi_b32 v0, s9, v4, v0
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
-; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v11, 24
; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
-; GFX8-NEXT: v_bfi_b32 v2, s10, v2, v6
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; GFX8-NEXT: v_cvt_f16_f32_sdwa v4, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX8-NEXT: v_cvt_f16_f32_sdwa v3, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_v2f16_fneg_lhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: s_mov_b32 s8, 0x800000
-; GFX9-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
-; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
-; GFX9-NEXT: v_ldexp_f32 v7, |v3|, v7
-; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v2
-; GFX9-NEXT: v_log_f32_e32 v7, v7
-; GFX9-NEXT: v_trunc_f32_e32 v6, v5
-; GFX9-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: s_mov_b32 s6, 0x800000
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
-; GFX9-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX9-NEXT: v_trunc_f32_e32 v4, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
-; GFX9-NEXT: s_mov_b32 s9, 0xc2fc0000
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
-; GFX9-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
-; GFX9-NEXT: v_not_b32_e32 v9, 63
-; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX9-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
-; GFX9-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX9-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
-; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
-; GFX9-NEXT: v_ldexp_f32 v4, |v0|, v4
-; GFX9-NEXT: v_log_f32_e32 v4, v4
-; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
-; GFX9-NEXT: v_exp_f32_e32 v6, v6
-; GFX9-NEXT: v_sub_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX9-NEXT: v_exp_f32_e32 v2, v2
-; GFX9-NEXT: v_ldexp_f32 v6, v6, v10
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX9-NEXT: v_log_f32_e32 v3, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX9-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX9-NEXT: v_mul_f32_e32 v10, 0.5, v4
+; GFX9-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX9-NEXT: v_mul_legacy_f32_e32 v3, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s8, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX9-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX9-NEXT: v_exp_f32_e32 v3, v3
+; GFX9-NEXT: v_trunc_f32_e32 v11, v10
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v11, v10
+; GFX9-NEXT: v_cvt_f32_f16_e64 v10, -v0
+; GFX9-NEXT: v_not_b32_e32 v7, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX9-NEXT: s_mov_b32 s9, 0x8000
+; GFX9-NEXT: v_trunc_f32_e32 v9, v4
+; GFX9-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX9-NEXT: v_xor_b32_sdwa v8, s9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: s_brev_b32 s10, -2
-; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
-; GFX9-NEXT: v_bfi_b32 v6, s10, v6, v8
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v9, v4
+; GFX9-NEXT: v_bfi_b32 v8, s10, v3, v8
+; GFX9-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v10|, s6
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v9, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v5, |v10|, v5
+; GFX9-NEXT: v_log_f32_e32 v5, v5
+; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX9-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_mul_legacy_f32_e32 v4, v1, v4
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX9-NEXT: v_add_f32_e32 v4, v4, v5
+; GFX9-NEXT: v_exp_f32_e32 v4, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; GFX9-NEXT: v_ldexp_f32 v4, v4, v5
; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
; GFX9-NEXT: v_trunc_f32_e32 v6, v5
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_xor_b32_sdwa v0, s9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: v_bfi_b32 v0, s10, v4, v0
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
-; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v10, 24
; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
-; GFX9-NEXT: v_bfi_b32 v2, s10, v2, v6
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT: v_pack_b32_f16 v0, v0, v4
+; GFX9-NEXT: v_pack_b32_f16 v0, v0, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_v2f16_fneg_lhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v5, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: s_mov_b32 s8, 0.5
-; GFX90A-NEXT: v_fma_mix_f32 v2, v1, s8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX90A-NEXT: s_mov_b32 s9, 0x800000
-; GFX90A-NEXT: v_trunc_f32_e32 v4, v2
-; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v5|, s9
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v2
-; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
-; GFX90A-NEXT: v_ldexp_f32 v4, |v5|, v4
-; GFX90A-NEXT: v_log_f32_e32 v4, v4
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0x42000000
-; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[4:5]
-; GFX90A-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX90A-NEXT: v_sub_f32_e32 v4, v4, v7
-; GFX90A-NEXT: v_trunc_f32_e32 v2, v3
-; GFX90A-NEXT: v_mul_legacy_f32 v4, v3, v4
-; GFX90A-NEXT: s_mov_b32 s10, 0xc2fc0000
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[6:7], v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v4
-; GFX90A-NEXT: v_not_b32_e32 v9, 63
-; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX90A-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s9
-; GFX90A-NEXT: v_add_f32_e32 v4, v4, v8
-; GFX90A-NEXT: v_cndmask_b32_e32 v8, 1.0, v5, vcc
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v2, v3
-; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, s[4:5]
-; GFX90A-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: s_mov_b32 s6, 0x800000
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v3, |v2|, v3
; GFX90A-NEXT: v_log_f32_e32 v3, v3
-; GFX90A-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v6, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX90A-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX90A-NEXT: s_mov_b32 s11, 0.5
+; GFX90A-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX90A-NEXT: v_mul_legacy_f32 v3, v4, v3
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s8, v3
+; GFX90A-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX90A-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX90A-NEXT: v_fma_mix_f32 v9, v1, s11, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX90A-NEXT: v_exp_f32_e32 v3, v3
+; GFX90A-NEXT: v_not_b32_e32 v7, 63
+; GFX90A-NEXT: v_trunc_f32_e32 v10, v9
+; GFX90A-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v10, v9
+; GFX90A-NEXT: v_cvt_f32_f16_e64 v10, -v0
+; GFX90A-NEXT: s_mov_b32 s9, 0x8000
+; GFX90A-NEXT: v_trunc_f32_e32 v9, v4
+; GFX90A-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX90A-NEXT: v_xor_b32_sdwa v8, s9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX90A-NEXT: s_brev_b32 s10, -2
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v9, v4
+; GFX90A-NEXT: v_bfi_b32 v8, s10, v3, v8
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v10|, s6
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v9, v4
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
+; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX90A-NEXT: v_ldexp_f32 v5, |v10|, v5
+; GFX90A-NEXT: v_log_f32_e32 v5, v5
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v8, v1
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX90A-NEXT: v_fma_mix_f32 v1, v1, s11, neg(0) op_sel_hi:[1,0,0]
+; GFX90A-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX90A-NEXT: v_mul_legacy_f32 v4, v8, v4
+; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v4
+; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX90A-NEXT: v_add_f32_e32 v4, v4, v5
; GFX90A-NEXT: v_exp_f32_e32 v4, v4
-; GFX90A-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX90A-NEXT: s_brev_b32 s11, -2
-; GFX90A-NEXT: v_mul_legacy_f32 v2, v6, v2
-; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v2
-; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[4:5]
-; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX90A-NEXT: v_exp_f32_e32 v2, v2
-; GFX90A-NEXT: v_ldexp_f32 v4, v4, v10
-; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v5, 24
-; GFX90A-NEXT: v_bfi_b32 v4, s11, v4, v8
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0x7fc00000
+; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v9, s[4:5]
-; GFX90A-NEXT: v_fma_mix_f32 v1, v1, s8, neg(0) op_sel_hi:[1,0,0]
-; GFX90A-NEXT: v_ldexp_f32 v2, v2, v4
-; GFX90A-NEXT: v_trunc_f32_e32 v4, v1
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v1
-; GFX90A-NEXT: v_trunc_f32_e32 v1, v6
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v6
+; GFX90A-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX90A-NEXT: v_trunc_f32_e32 v5, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v5, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v1, v8
+; GFX90A-NEXT: v_xor_b32_sdwa v0, s9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v8
+; GFX90A-NEXT: v_bfi_b32 v0, s10, v4, v0
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
-; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v6
-; GFX90A-NEXT: v_bfi_b32 v2, s11, v2, v4
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v10, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v8
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX90A-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v3
@@ -1675,59 +1703,62 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_f16_e64 v3, -v0
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_mov_b32_e32 v9, 0x8000
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
-; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
-; GFX10-NEXT: v_trunc_f32_e32 v10, v7
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 32, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s5
-; GFX10-NEXT: s_mov_b32 s4, 0.5
-; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX10-NEXT: v_ldexp_f32 v5, |v0|, v5
-; GFX10-NEXT: v_fma_mix_f32 v8, v1, s4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v10, v7
-; GFX10-NEXT: v_log_f32_e32 v3, v3
-; GFX10-NEXT: v_log_f32_e32 v5, v5
-; GFX10-NEXT: v_trunc_f32_e32 v9, v8
-; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v9, v8
-; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
-; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v1
-; GFX10-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX10-NEXT: v_fma_mix_f32 v1, v1, s4, neg(0) op_sel_hi:[1,0,0]
-; GFX10-NEXT: s_and_b32 s5, s6, s5
-; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v7, v3
-; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
-; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
-; GFX10-NEXT: v_trunc_f32_e32 v11, v1
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v11, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, v2, s5
-; GFX10-NEXT: v_cmp_class_f32_e64 s5, v2, 24
-; GFX10-NEXT: v_add_f32_e32 v3, v3, v5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, s4
-; GFX10-NEXT: v_exp_f32_e32 v3, v3
-; GFX10-NEXT: v_add_f32_e32 v4, v4, v5
-; GFX10-NEXT: v_trunc_f32_e32 v5, v6
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v3|
+; GFX10-NEXT: v_trunc_f32_e32 v12, v8
+; GFX10-NEXT: v_xor_b32_sdwa v10, v9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_xor_b32_sdwa v0, v9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 32, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s5
+; GFX10-NEXT: s_mov_b32 s5, 0.5
+; GFX10-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX10-NEXT: v_ldexp_f32 v6, |v3|, v6
+; GFX10-NEXT: v_fma_mix_f32 v11, v1, s5, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24
+; GFX10-NEXT: v_cmp_class_f32_e64 s9, v3, 24
+; GFX10-NEXT: v_log_f32_e32 v4, v4
+; GFX10-NEXT: v_log_f32_e32 v6, v6
+; GFX10-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v1
+; GFX10-NEXT: v_sub_f32_e32 v5, v6, v5
+; GFX10-NEXT: v_fma_mix_f32 v1, v1, s5, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_neq_f32_e64 s5, v12, v8
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v8, v4
+; GFX10-NEXT: v_trunc_f32_e32 v14, v7
+; GFX10-NEXT: v_mul_legacy_f32_e32 v5, v7, v5
+; GFX10-NEXT: v_trunc_f32_e32 v13, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s7, v14, v7
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v5
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v13, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s4
; GFX10-NEXT: v_exp_f32_e32 v4, v4
-; GFX10-NEXT: v_ldexp_f32 v3, v3, v8
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v6
-; GFX10-NEXT: v_bfi_b32 v1, 0x7fffffff, v3, v1
-; GFX10-NEXT: v_ldexp_f32 v3, v4, v8
+; GFX10-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX10-NEXT: v_trunc_f32_e32 v6, v11
+; GFX10-NEXT: v_exp_f32_e32 v5, v5
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v11
+; GFX10-NEXT: v_ldexp_f32 v4, v4, v9
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v12, v8
+; GFX10-NEXT: v_bfi_b32 v6, 0x7fffffff, v4, v10
+; GFX10-NEXT: v_ldexp_f32 v5, v5, v9
; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f32_e64 s4, v5, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v10, v7
-; GFX10-NEXT: s_and_b32 s4, s6, s4
-; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v4
-; GFX10-NEXT: s_and_b32 s5, s5, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s5
+; GFX10-NEXT: s_and_b32 s4, s7, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v5, v0
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v14, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v0, s4
+; GFX10-NEXT: s_and_b32 s4, s8, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
+; GFX10-NEXT: s_and_b32 s4, s9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
@@ -1738,77 +1769,77 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, -v2.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, -v0.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v4, -v2.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v3|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0.5
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, |v0|, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v3, 24
+; GFX11-TRUE16-NEXT: v_xor_b16 v2.h, 0x8000, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v4|
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 32, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s6, v4, 24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, 0.5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v11, v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, |v4|, v5
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v7, v7
; GFX11-TRUE16-NEXT: v_log_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v7
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, s0, neg(0) op_sel_hi:[1,0,0]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v5
-; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v6, v7, v6 :: v_dual_sub_f32 v5, v5, v9
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v9, v1.l
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, s1, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v5, v8, v5 :: v_dual_mul_dx9_zero_f32 v6, v9, v6
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v1
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v12, v9
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s3, v12, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
-; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s4, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v3, v1
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, v5
-; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v7 :: v_dual_add_f32 v6, v6, v10
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v11
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v8
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v10, v1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v11, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v5, v3
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v6, v7
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s4, v11, v8
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s1, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s6, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1816,78 +1847,81 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v6
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0.5
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v0|, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, -v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v4, -v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v3|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v8, v8
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0x8000, v2
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v3, 24
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v4|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 32, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, 0.5
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s6, v4, 24
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v4|, v5
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v7, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v5, v5
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v7
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v1
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, s0, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v5
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v7, v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v9
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v9, v1
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, s1, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v5, v8, v5 :: v_dual_mul_dx9_zero_f32 v6, v9, v6
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v9
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, v12, v9
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s3, v12, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v10 :: v_dual_add_f32 v6, v6, v11
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v7
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v7
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
-; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s4, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
-; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v6, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v10, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v8
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v11, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v10, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v5, v3
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v6, v7
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s4, v10, v8
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s6, s4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%x.fneg = fneg <2 x half> %x
@@ -1899,279 +1933,288 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6-LABEL: v_pow_v2f16_fneg_rhs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX6-NEXT: s_mov_b32 s8, 0x800000
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
-; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
-; GFX6-NEXT: v_ldexp_f32_e64 v7, |v3|, v7
-; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v2
-; GFX6-NEXT: v_log_f32_e32 v7, v7
-; GFX6-NEXT: v_trunc_f32_e32 v6, v5
-; GFX6-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX6-NEXT: s_mov_b32 s6, 0x800000
+; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v4, |v2|, v4
+; GFX6-NEXT: v_log_f32_e32 v4, v4
+; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
-; GFX6-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX6-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
-; GFX6-NEXT: s_mov_b32 s9, 0xc2fc0000
-; GFX6-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
-; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX6-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX6-NEXT: v_exp_f32_e32 v6, v6
-; GFX6-NEXT: v_trunc_f32_e32 v4, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX6-NEXT: v_sub_f32_e32 v4, v4, v6
+; GFX6-NEXT: v_mul_legacy_f32_e32 v4, v3, v4
+; GFX6-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX6-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s8, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX6-NEXT: v_add_f32_e32 v4, v4, v7
+; GFX6-NEXT: v_exp_f32_e32 v4, v4
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
-; GFX6-NEXT: v_not_b32_e32 v9, 63
-; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; GFX6-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v6, v6, v10
-; GFX6-NEXT: s_brev_b32 s10, -2
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
-; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v3, 24
-; GFX6-NEXT: v_bfi_b32 v6, s10, v6, v8
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v6, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 32, s[4:5]
-; GFX6-NEXT: v_ldexp_f32_e64 v6, |v0|, v6
-; GFX6-NEXT: v_log_f32_e32 v6, v6
+; GFX6-NEXT: v_not_b32_e32 v7, 63
+; GFX6-NEXT: v_mul_f32_e32 v10, 0.5, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX6-NEXT: v_trunc_f32_e32 v9, v3
+; GFX6-NEXT: v_trunc_f32_e32 v11, v10
+; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v8
+; GFX6-NEXT: s_brev_b32 s9, -2
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v9, v3
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v11, v10
+; GFX6-NEXT: v_bfi_b32 v8, s9, v4, v2
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s6
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v9, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e64 v5, |v0|, v5
+; GFX6-NEXT: v_log_f32_e32 v5, v5
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
-; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX6-NEXT: v_sub_f32_e32 v5, v6, v5
-; GFX6-NEXT: v_mul_legacy_f32_e32 v5, v1, v5
-; GFX6-NEXT: v_cmp_gt_f32_e64 s[6:7], s9, v5
-; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[6:7]
-; GFX6-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX6-NEXT: v_mul_f32_e32 v8, 0.5, v1
-; GFX6-NEXT: v_exp_f32_e32 v5, v5
-; GFX6-NEXT: v_trunc_f32_e32 v4, v1
-; GFX6-NEXT: v_trunc_f32_e32 v10, v8
-; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v1
-; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v8
+; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX6-NEXT: v_sub_f32_e32 v3, v5, v3
+; GFX6-NEXT: v_mul_legacy_f32_e32 v3, v1, v3
+; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX6-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX6-NEXT: v_exp_f32_e32 v3, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX6-NEXT: v_mul_f32_e32 v7, 0.5, v1
+; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX6-NEXT: v_trunc_f32_e32 v6, v1
+; GFX6-NEXT: v_trunc_f32_e32 v8, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v3, v3, v5
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v6, v1
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v8, v7
+; GFX6-NEXT: v_bfi_b32 v5, s9, v3, v0
; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, v9, s[6:7]
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v5, v5, v7
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v6, v1
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX6-NEXT: v_bfi_b32 v5, s10, v5, v6
; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
+; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_v2f16_fneg_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: s_mov_b32 s8, 0x800000
-; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
-; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
-; GFX8-NEXT: v_ldexp_f32 v7, |v3|, v7
-; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v2
-; GFX8-NEXT: v_log_f32_e32 v7, v7
-; GFX8-NEXT: v_trunc_f32_e32 v6, v5
-; GFX8-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: s_mov_b32 s6, 0x800000
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v4, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
-; GFX8-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX8-NEXT: v_trunc_f32_e32 v4, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
-; GFX8-NEXT: s_mov_b32 s9, 0xc2fc0000
-; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
-; GFX8-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
-; GFX8-NEXT: v_not_b32_e32 v9, 63
-; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX8-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
-; GFX8-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX8-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
-; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
-; GFX8-NEXT: v_ldexp_f32 v4, |v0|, v4
-; GFX8-NEXT: v_log_f32_e32 v4, v4
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX8-NEXT: v_log_f32_e32 v3, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX8-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX8-NEXT: v_mul_f32_e32 v10, 0.5, v4
+; GFX8-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX8-NEXT: v_mul_legacy_f32_e32 v3, v4, v3
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s8, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX8-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX8-NEXT: v_exp_f32_e32 v3, v3
+; GFX8-NEXT: v_trunc_f32_e32 v11, v10
+; GFX8-NEXT: v_not_b32_e32 v7, 63
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v11, v10
+; GFX8-NEXT: v_cvt_f32_f16_e32 v10, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX8-NEXT: v_mov_b32_e32 v8, 16
+; GFX8-NEXT: v_trunc_f32_e32 v9, v4
+; GFX8-NEXT: v_lshlrev_b32_sdwa v8, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: s_brev_b32 s9, -2
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v9, v4
+; GFX8-NEXT: v_bfi_b32 v8, s9, v3, v8
+; GFX8-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v10|, s6
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v9, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v5, |v10|, v5
+; GFX8-NEXT: v_log_f32_e32 v5, v5
; GFX8-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
-; GFX8-NEXT: v_exp_f32_e32 v6, v6
-; GFX8-NEXT: v_sub_f32_e32 v2, v4, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
-; GFX8-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX8-NEXT: v_exp_f32_e32 v2, v2
-; GFX8-NEXT: v_ldexp_f32 v6, v6, v10
-; GFX8-NEXT: s_brev_b32 s10, -2
-; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
-; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
-; GFX8-NEXT: v_bfi_b32 v6, s10, v6, v8
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX8-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_mul_legacy_f32_e32 v4, v1, v4
+; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX8-NEXT: v_add_f32_e32 v4, v4, v5
+; GFX8-NEXT: v_exp_f32_e32 v4, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; GFX8-NEXT: v_ldexp_f32 v4, v4, v5
; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
; GFX8-NEXT: v_trunc_f32_e32 v6, v5
; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: v_bfi_b32 v0, s9, v4, v0
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
-; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v10, 24
; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
-; GFX8-NEXT: v_bfi_b32 v2, s10, v2, v6
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; GFX8-NEXT: v_cvt_f16_f32_sdwa v4, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX8-NEXT: v_cvt_f16_f32_sdwa v3, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_v2f16_fneg_rhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: s_mov_b32 s8, 0x800000
-; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
-; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
-; GFX9-NEXT: v_ldexp_f32 v7, |v3|, v7
-; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v2
-; GFX9-NEXT: v_log_f32_e32 v7, v7
-; GFX9-NEXT: v_trunc_f32_e32 v6, v5
-; GFX9-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: s_mov_b32 s6, 0x800000
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v4, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
-; GFX9-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX9-NEXT: v_trunc_f32_e32 v4, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
-; GFX9-NEXT: s_mov_b32 s9, 0xc2fc0000
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
-; GFX9-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
-; GFX9-NEXT: v_not_b32_e32 v9, 63
-; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX9-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
-; GFX9-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX9-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
-; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
-; GFX9-NEXT: v_ldexp_f32 v4, |v0|, v4
-; GFX9-NEXT: v_log_f32_e32 v4, v4
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX9-NEXT: v_log_f32_e32 v3, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX9-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX9-NEXT: v_mul_f32_e32 v10, 0.5, v4
+; GFX9-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX9-NEXT: v_mul_legacy_f32_e32 v3, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s8, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX9-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX9-NEXT: v_exp_f32_e32 v3, v3
+; GFX9-NEXT: v_trunc_f32_e32 v11, v10
+; GFX9-NEXT: v_not_b32_e32 v7, 63
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v11, v10
+; GFX9-NEXT: v_cvt_f32_f16_e32 v10, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX9-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, 16
+; GFX9-NEXT: v_trunc_f32_e32 v9, v4
+; GFX9-NEXT: v_lshlrev_b32_sdwa v8, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: s_brev_b32 s9, -2
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v9, v4
+; GFX9-NEXT: v_bfi_b32 v8, s9, v3, v8
+; GFX9-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v10|, s6
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v9, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v5, |v10|, v5
+; GFX9-NEXT: v_log_f32_e32 v5, v5
; GFX9-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
-; GFX9-NEXT: v_exp_f32_e32 v6, v6
-; GFX9-NEXT: v_sub_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX9-NEXT: v_exp_f32_e32 v2, v2
-; GFX9-NEXT: v_ldexp_f32 v6, v6, v10
-; GFX9-NEXT: s_brev_b32 s10, -2
-; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
-; GFX9-NEXT: v_bfi_b32 v6, s10, v6, v8
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX9-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_mul_legacy_f32_e32 v4, v1, v4
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX9-NEXT: v_add_f32_e32 v4, v4, v5
+; GFX9-NEXT: v_exp_f32_e32 v4, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; GFX9-NEXT: v_ldexp_f32 v4, v4, v5
; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
; GFX9-NEXT: v_trunc_f32_e32 v6, v5
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: v_bfi_b32 v0, s9, v4, v0
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
-; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v10, 24
; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
-; GFX9-NEXT: v_bfi_b32 v2, s10, v2, v6
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT: v_pack_b32_f16 v0, v0, v4
+; GFX9-NEXT: v_pack_b32_f16 v0, v0, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_v2f16_fneg_rhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: s_mov_b32 s8, 0.5
-; GFX90A-NEXT: v_fma_mix_f32 v2, -v1, s8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX90A-NEXT: s_mov_b32 s9, 0x800000
-; GFX90A-NEXT: v_trunc_f32_e32 v4, v2
-; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v5|, s9
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v2
-; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
-; GFX90A-NEXT: v_ldexp_f32 v4, |v5|, v4
-; GFX90A-NEXT: v_log_f32_e32 v4, v4
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0x42000000
-; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[4:5]
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX90A-NEXT: v_sub_f32_e32 v4, v4, v7
-; GFX90A-NEXT: v_trunc_f32_e32 v2, v3
-; GFX90A-NEXT: v_mul_legacy_f32 v4, v3, v4
-; GFX90A-NEXT: s_mov_b32 s10, 0xc2fc0000
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[6:7], v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v4
-; GFX90A-NEXT: v_not_b32_e32 v9, 63
-; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX90A-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s9
-; GFX90A-NEXT: v_add_f32_e32 v4, v4, v8
-; GFX90A-NEXT: v_cndmask_b32_e32 v8, 1.0, v5, vcc
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v2, v3
-; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, s[4:5]
-; GFX90A-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: s_mov_b32 s6, 0x800000
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v4, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v3, |v2|, v3
; GFX90A-NEXT: v_log_f32_e32 v3, v3
-; GFX90A-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
-; GFX90A-NEXT: v_cvt_f32_f16_e64 v6, -v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX90A-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX90A-NEXT: s_mov_b32 s10, 0.5
+; GFX90A-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX90A-NEXT: v_mul_legacy_f32 v3, v4, v3
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s8, v3
+; GFX90A-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX90A-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX90A-NEXT: v_exp_f32_e32 v3, v3
+; GFX90A-NEXT: v_fma_mix_f32 v9, -v1, s10, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX90A-NEXT: v_not_b32_e32 v7, 63
+; GFX90A-NEXT: v_trunc_f32_e32 v10, v9
+; GFX90A-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v10, v9
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v10, v0
+; GFX90A-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX90A-NEXT: v_mov_b32_e32 v8, 16
+; GFX90A-NEXT: v_trunc_f32_e32 v9, v4
+; GFX90A-NEXT: v_lshlrev_b32_sdwa v8, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX90A-NEXT: s_brev_b32 s9, -2
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v9, v4
+; GFX90A-NEXT: v_bfi_b32 v8, s9, v3, v8
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v10|, s6
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v9, v4
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
+; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX90A-NEXT: v_ldexp_f32 v5, |v10|, v5
+; GFX90A-NEXT: v_log_f32_e32 v5, v5
+; GFX90A-NEXT: v_cvt_f32_f16_e64 v8, -v1
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX90A-NEXT: v_fma_mix_f32 v1, -v1, s10, neg(0) op_sel_hi:[1,0,0]
+; GFX90A-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX90A-NEXT: v_mul_legacy_f32 v4, v8, v4
+; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v4
+; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX90A-NEXT: v_add_f32_e32 v4, v4, v5
; GFX90A-NEXT: v_exp_f32_e32 v4, v4
-; GFX90A-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX90A-NEXT: s_brev_b32 s11, -2
-; GFX90A-NEXT: v_mul_legacy_f32 v2, v6, v2
-; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v2
-; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[4:5]
-; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX90A-NEXT: v_exp_f32_e32 v2, v2
-; GFX90A-NEXT: v_ldexp_f32 v4, v4, v10
-; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v5, 24
-; GFX90A-NEXT: v_bfi_b32 v4, s11, v4, v8
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0x7fc00000
+; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v9, s[4:5]
-; GFX90A-NEXT: v_fma_mix_f32 v1, -v1, s8, neg(0) op_sel_hi:[1,0,0]
-; GFX90A-NEXT: v_ldexp_f32 v2, v2, v4
-; GFX90A-NEXT: v_trunc_f32_e32 v4, v1
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v1
-; GFX90A-NEXT: v_trunc_f32_e32 v1, v6
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v6
+; GFX90A-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX90A-NEXT: v_trunc_f32_e32 v5, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v5, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v1, v8
+; GFX90A-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v8
+; GFX90A-NEXT: v_bfi_b32 v0, s9, v4, v0
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
-; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v6
-; GFX90A-NEXT: v_bfi_b32 v2, s11, v2, v4
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v10, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v8
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX90A-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v3
@@ -2181,59 +2224,62 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v7, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v8, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_mov_b32_e32 v9, 16
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
-; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
-; GFX10-NEXT: v_trunc_f32_e32 v10, v7
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 32, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s5
-; GFX10-NEXT: s_mov_b32 s4, 0.5
-; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX10-NEXT: v_ldexp_f32 v5, |v0|, v5
-; GFX10-NEXT: v_fma_mix_f32 v8, -v1, s4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v10, v7
-; GFX10-NEXT: v_log_f32_e32 v3, v3
-; GFX10-NEXT: v_log_f32_e32 v5, v5
-; GFX10-NEXT: v_trunc_f32_e32 v9, v8
-; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v9, v8
-; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
-; GFX10-NEXT: v_cvt_f32_f16_e64 v6, -v1
-; GFX10-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX10-NEXT: v_fma_mix_f32 v1, -v1, s4, neg(0) op_sel_hi:[1,0,0]
-; GFX10-NEXT: s_and_b32 s5, s6, s5
-; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v7, v3
-; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
-; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
-; GFX10-NEXT: v_trunc_f32_e32 v11, v1
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v11, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, v2, s5
-; GFX10-NEXT: v_cmp_class_f32_e64 s5, v2, 24
-; GFX10-NEXT: v_add_f32_e32 v3, v3, v5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, s4
-; GFX10-NEXT: v_exp_f32_e32 v3, v3
-; GFX10-NEXT: v_add_f32_e32 v4, v4, v5
-; GFX10-NEXT: v_trunc_f32_e32 v5, v6
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v3|
+; GFX10-NEXT: v_trunc_f32_e32 v12, v8
+; GFX10-NEXT: v_lshlrev_b32_sdwa v9, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 32, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s5
+; GFX10-NEXT: s_mov_b32 s5, 0.5
+; GFX10-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX10-NEXT: v_ldexp_f32 v6, |v3|, v6
+; GFX10-NEXT: v_fma_mix_f32 v10, -v1, s5, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24
+; GFX10-NEXT: v_cmp_class_f32_e64 s9, v3, 24
+; GFX10-NEXT: v_log_f32_e32 v4, v4
+; GFX10-NEXT: v_log_f32_e32 v6, v6
+; GFX10-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX10-NEXT: v_cvt_f32_f16_e64 v7, -v1
+; GFX10-NEXT: v_sub_f32_e32 v5, v6, v5
+; GFX10-NEXT: v_fma_mix_f32 v1, -v1, s5, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_neq_f32_e64 s5, v12, v8
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v8, v4
+; GFX10-NEXT: v_trunc_f32_e32 v14, v7
+; GFX10-NEXT: v_mul_legacy_f32_e32 v5, v7, v5
+; GFX10-NEXT: v_trunc_f32_e32 v13, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s7, v14, v7
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v5
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v13, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s4
; GFX10-NEXT: v_exp_f32_e32 v4, v4
-; GFX10-NEXT: v_ldexp_f32 v3, v3, v8
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v6
-; GFX10-NEXT: v_bfi_b32 v1, 0x7fffffff, v3, v1
-; GFX10-NEXT: v_ldexp_f32 v3, v4, v8
+; GFX10-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX10-NEXT: v_trunc_f32_e32 v6, v10
+; GFX10-NEXT: v_exp_f32_e32 v5, v5
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v10
+; GFX10-NEXT: v_ldexp_f32 v4, v4, v11
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v12, v8
+; GFX10-NEXT: v_bfi_b32 v6, 0x7fffffff, v4, v9
+; GFX10-NEXT: v_ldexp_f32 v5, v5, v11
; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f32_e64 s4, v5, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v10, v7
-; GFX10-NEXT: s_and_b32 s4, s6, s4
-; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v4
-; GFX10-NEXT: s_and_b32 s5, s5, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s5
+; GFX10-NEXT: s_and_b32 s4, s7, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v5, v0
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v14, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v0, s4
+; GFX10-NEXT: s_and_b32 s4, s8, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
+; GFX10-NEXT: s_and_b32 s4, s9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
@@ -2244,77 +2290,77 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, -v6.l
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v3|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0.5
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, |v0|, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v8, -v8.l
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v3, 24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v4|
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 32, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s6, v4, 24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, 0.5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v11, -v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, |v4|, v5
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v7, v7
; GFX11-TRUE16-NEXT: v_log_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v7
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v7, -v1.l
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, s0, neg(0) op_sel_hi:[1,0,0]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v5
-; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v6, v7, v6 :: v_dual_sub_f32 v5, v5, v9
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v9, -v1.l
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, s1, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v5, v8, v5 :: v_dual_mul_dx9_zero_f32 v6, v9, v6
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v1
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v12, v9
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s3, v12, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
-; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s4, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v3, v1
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, v5
-; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v7 :: v_dual_add_f32 v6, v6, v10
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v11
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v8
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v10, v1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v11, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v5, v3
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v6, v7
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s4, v11, v8
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s1, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s6, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2322,78 +2368,79 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v6, -v6
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0.5
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v0|, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v3|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v8, -v8
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v3, 24
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v4|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 32, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s6, v4, 24
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, 0.5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v11, -v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v4|, v5
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v7, v7
; GFX11-FAKE16-NEXT: v_log_f32_e32 v5, v5
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v7
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v7, -v1
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, s0, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v5
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_dual_sub_f32 v6, v7, v6 :: v_dual_sub_f32 v5, v5, v9
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v9, -v1
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, s1, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v5, v8, v5 :: v_dual_mul_dx9_zero_f32 v6, v9, v6
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v9
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, v12, v9
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s3, v12, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v7
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
-; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s4, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v7 :: v_dual_add_f32 v6, v6, v10
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v11
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
-; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v6, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v11
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v8
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v10, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v11, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v5, v3
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v6, v7
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s4, v11, v8
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s6, s4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%y.fneg = fneg <2 x half> %y
@@ -2406,279 +2453,288 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT: s_mov_b32 s8, 0x800000
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
-; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
-; GFX6-NEXT: v_ldexp_f32_e64 v7, |v3|, v7
-; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v2
-; GFX6-NEXT: v_log_f32_e32 v7, v7
-; GFX6-NEXT: v_trunc_f32_e32 v6, v5
-; GFX6-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s8
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 32, vcc
+; GFX6-NEXT: v_ldexp_f32_e64 v4, |v2|, v4
+; GFX6-NEXT: v_log_f32_e32 v4, v4
+; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
-; GFX6-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX6-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
+; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX6-NEXT: v_sub_f32_e32 v4, v4, v6
+; GFX6-NEXT: v_mul_legacy_f32_e32 v4, v3, v4
; GFX6-NEXT: s_mov_b32 s9, 0xc2fc0000
-; GFX6-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
-; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX6-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX6-NEXT: v_trunc_f32_e32 v4, v2
-; GFX6-NEXT: v_exp_f32_e32 v6, v6
+; GFX6-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX6-NEXT: v_cmp_gt_f32_e32 vcc, s9, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX6-NEXT: v_add_f32_e32 v4, v4, v7
+; GFX6-NEXT: v_exp_f32_e32 v4, v4
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
-; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; GFX6-NEXT: v_not_b32_e32 v9, 63
-; GFX6-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
-; GFX6-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
-; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v3, 24
-; GFX6-NEXT: v_ldexp_f32_e32 v6, v6, v10
+; GFX6-NEXT: v_mul_f32_e32 v10, 0.5, v3
+; GFX6-NEXT: v_not_b32_e32 v7, 63
+; GFX6-NEXT: v_trunc_f32_e32 v9, v3
+; GFX6-NEXT: v_trunc_f32_e32 v11, v10
+; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v9, v3
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v11, v10
+; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v8
; GFX6-NEXT: s_brev_b32 s10, -2
-; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
-; GFX6-NEXT: v_bfi_b32 v6, s10, v6, v8
-; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, 32, s[4:5]
-; GFX6-NEXT: v_ldexp_f32_e64 v8, |v0|, v8
-; GFX6-NEXT: v_log_f32_e32 v8, v8
+; GFX6-NEXT: v_bfi_b32 v8, s10, v4, v2
+; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 32, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GFX6-NEXT: v_sub_f32_e32 v5, v8, v5
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v6, v2, vcc
-; GFX6-NEXT: v_mul_f32_e32 v6, 0.5, v1
-; GFX6-NEXT: v_mul_legacy_f32_e32 v5, v1, v5
-; GFX6-NEXT: v_trunc_f32_e32 v10, v6
-; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v5
-; GFX6-NEXT: v_cmp_lg_f32_e64 s[6:7], v10, v6
-; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[4:5]
-; GFX6-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX6-NEXT: v_exp_f32_e32 v5, v5
-; GFX6-NEXT: v_trunc_f32_e32 v4, v1
-; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v1
-; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, v9, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
-; GFX6-NEXT: v_ldexp_f32_e32 v5, v5, v7
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
+; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v9, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX6-NEXT: v_mul_f32_e32 v7, 0.5, v1
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc
+; GFX6-NEXT: v_trunc_f32_e32 v6, v1
+; GFX6-NEXT: v_trunc_f32_e32 v8, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v3, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v6, v1
+; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v8, v7
+; GFX6-NEXT: v_bfi_b32 v5, s10, v2, v0
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v6, v1
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX6-NEXT: v_bfi_b32 v5, s10, v5, v6
; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
+; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: s_mov_b32 s8, 0x800000
-; GFX8-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
-; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
-; GFX8-NEXT: v_ldexp_f32 v7, |v3|, v7
-; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v2
-; GFX8-NEXT: v_log_f32_e32 v7, v7
-; GFX8-NEXT: v_trunc_f32_e32 v6, v5
-; GFX8-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: s_mov_b32 s6, 0x800000
+; GFX8-NEXT: v_cvt_f32_f16_sdwa v4, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
-; GFX8-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX8-NEXT: v_trunc_f32_e32 v4, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
-; GFX8-NEXT: s_mov_b32 s9, 0xc2fc0000
-; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
-; GFX8-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
-; GFX8-NEXT: v_not_b32_e32 v9, 63
-; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX8-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
-; GFX8-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX8-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
-; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
-; GFX8-NEXT: v_ldexp_f32 v4, |v0|, v4
-; GFX8-NEXT: v_log_f32_e32 v4, v4
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX8-NEXT: v_log_f32_e32 v3, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX8-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX8-NEXT: v_mul_f32_e32 v11, 0.5, v4
+; GFX8-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX8-NEXT: v_mul_legacy_f32_e32 v3, v4, v3
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s8, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX8-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX8-NEXT: v_exp_f32_e32 v3, v3
+; GFX8-NEXT: v_trunc_f32_e32 v12, v11
+; GFX8-NEXT: v_not_b32_e32 v7, 63
+; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v12, v11
+; GFX8-NEXT: v_cvt_f32_f16_e64 v11, -v0
+; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX8-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX8-NEXT: v_mov_b32_e32 v8, 0x8000
+; GFX8-NEXT: v_trunc_f32_e32 v10, v4
+; GFX8-NEXT: v_xor_b32_sdwa v9, v8, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: s_brev_b32 s9, -2
+; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v10, v4
+; GFX8-NEXT: v_bfi_b32 v9, s9, v3, v9
+; GFX8-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v11|, s6
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v10, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v5, |v11|, v5
+; GFX8-NEXT: v_log_f32_e32 v5, v5
; GFX8-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
-; GFX8-NEXT: v_exp_f32_e32 v6, v6
-; GFX8-NEXT: v_sub_f32_e32 v2, v4, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
-; GFX8-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX8-NEXT: v_exp_f32_e32 v2, v2
-; GFX8-NEXT: v_ldexp_f32 v6, v6, v10
-; GFX8-NEXT: s_brev_b32 s10, -2
-; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
-; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
-; GFX8-NEXT: v_bfi_b32 v6, s10, v6, v8
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX8-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX8-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_mul_legacy_f32_e32 v4, v1, v4
+; GFX8-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX8-NEXT: v_add_f32_e32 v4, v4, v5
+; GFX8-NEXT: v_exp_f32_e32 v4, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX8-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; GFX8-NEXT: v_ldexp_f32 v4, v4, v5
; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
; GFX8-NEXT: v_trunc_f32_e32 v6, v5
; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
; GFX8-NEXT: v_trunc_f32_e32 v5, v1
+; GFX8-NEXT: v_xor_b32_sdwa v0, v8, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX8-NEXT: v_bfi_b32 v0, s9, v4, v0
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
-; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v11, 24
; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
-; GFX8-NEXT: v_bfi_b32 v2, s10, v2, v6
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; GFX8-NEXT: v_cvt_f16_f32_sdwa v4, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX8-NEXT: v_cvt_f16_f32_sdwa v3, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: s_mov_b32 s8, 0x800000
-; GFX9-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s8
-; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 32, s[4:5]
-; GFX9-NEXT: v_ldexp_f32 v7, |v3|, v7
-; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v2
-; GFX9-NEXT: v_log_f32_e32 v7, v7
-; GFX9-NEXT: v_trunc_f32_e32 v6, v5
-; GFX9-NEXT: v_cmp_lg_f32_e64 s[6:7], v6, v5
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: s_mov_b32 s6, 0x800000
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v4, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000
-; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[4:5]
-; GFX9-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX9-NEXT: v_trunc_f32_e32 v4, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v6, v2, v6
-; GFX9-NEXT: s_mov_b32 s9, 0xc2fc0000
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v2
-; GFX9-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v6
-; GFX9-NEXT: v_not_b32_e32 v9, 63
-; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX9-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
-; GFX9-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX9-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc
-; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v4, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
-; GFX9-NEXT: v_ldexp_f32 v4, |v0|, v4
-; GFX9-NEXT: v_log_f32_e32 v4, v4
-; GFX9-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[4:5]
-; GFX9-NEXT: v_exp_f32_e32 v6, v6
-; GFX9-NEXT: v_sub_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s9, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[4:5]
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX9-NEXT: v_exp_f32_e32 v2, v2
-; GFX9-NEXT: v_ldexp_f32 v6, v6, v10
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX9-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX9-NEXT: v_log_f32_e32 v3, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX9-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX9-NEXT: v_mul_f32_e32 v10, 0.5, v4
+; GFX9-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX9-NEXT: v_mul_legacy_f32_e32 v3, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s8, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX9-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX9-NEXT: v_exp_f32_e32 v3, v3
+; GFX9-NEXT: v_trunc_f32_e32 v11, v10
+; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v11, v10
+; GFX9-NEXT: v_cvt_f32_f16_e64 v10, -v0
+; GFX9-NEXT: v_not_b32_e32 v7, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX9-NEXT: s_mov_b32 s9, 0x8000
+; GFX9-NEXT: v_trunc_f32_e32 v9, v4
+; GFX9-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX9-NEXT: v_xor_b32_sdwa v8, s9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: s_brev_b32 s10, -2
-; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v3, 24
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[4:5]
-; GFX9-NEXT: v_bfi_b32 v6, s10, v6, v8
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v9, v4
+; GFX9-NEXT: v_bfi_b32 v8, s10, v3, v8
+; GFX9-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v10|, s6
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v9, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v5, |v10|, v5
+; GFX9-NEXT: v_log_f32_e32 v5, v5
+; GFX9-NEXT: v_cvt_f32_f16_e64 v1, -v1
+; GFX9-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
+; GFX9-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_mul_legacy_f32_e32 v4, v1, v4
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX9-NEXT: v_add_f32_e32 v4, v4, v5
+; GFX9-NEXT: v_exp_f32_e32 v4, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX9-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; GFX9-NEXT: v_ldexp_f32 v4, v4, v5
; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v3, vcc
; GFX9-NEXT: v_trunc_f32_e32 v6, v5
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v6, v5
; GFX9-NEXT: v_trunc_f32_e32 v5, v1
+; GFX9-NEXT: v_xor_b32_sdwa v0, s9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v5, v1
+; GFX9-NEXT: v_bfi_b32 v0, s10, v4, v0
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v6, 1.0, v0, vcc
-; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v10, 24
; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v5, v1
-; GFX9-NEXT: v_bfi_b32 v2, s10, v2, v6
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
-; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT: v_pack_b32_f16 v0, v0, v4
+; GFX9-NEXT: v_pack_b32_f16 v0, v0, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v5, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: s_mov_b32 s8, 0.5
-; GFX90A-NEXT: v_fma_mix_f32 v2, -v1, s8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX90A-NEXT: s_mov_b32 s9, 0x800000
-; GFX90A-NEXT: v_trunc_f32_e32 v4, v2
-; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v5|, s9
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v2
-; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
-; GFX90A-NEXT: v_ldexp_f32 v4, |v5|, v4
-; GFX90A-NEXT: v_log_f32_e32 v4, v4
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0x42000000
-; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[4:5]
-; GFX90A-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX90A-NEXT: v_sub_f32_e32 v4, v4, v7
-; GFX90A-NEXT: v_trunc_f32_e32 v2, v3
-; GFX90A-NEXT: v_mul_legacy_f32 v4, v3, v4
-; GFX90A-NEXT: s_mov_b32 s10, 0xc2fc0000
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[6:7], v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v7, 0x42800000
-; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v4
-; GFX90A-NEXT: v_not_b32_e32 v9, 63
-; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[4:5]
-; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX90A-NEXT: v_cndmask_b32_e64 v10, 0, v9, s[4:5]
-; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s9
-; GFX90A-NEXT: v_add_f32_e32 v4, v4, v8
-; GFX90A-NEXT: v_cndmask_b32_e32 v8, 1.0, v5, vcc
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v2, v3
-; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, s[4:5]
-; GFX90A-NEXT: v_ldexp_f32 v3, |v0|, v3
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: s_mov_b32 s6, 0x800000
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v4, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s6
+; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
+; GFX90A-NEXT: v_ldexp_f32 v3, |v2|, v3
; GFX90A-NEXT: v_log_f32_e32 v3, v3
-; GFX90A-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
-; GFX90A-NEXT: v_cvt_f32_f16_e64 v6, -v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX90A-NEXT: s_mov_b32 s8, 0xc2fc0000
+; GFX90A-NEXT: s_mov_b32 s11, 0.5
+; GFX90A-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX90A-NEXT: v_mul_legacy_f32 v3, v4, v3
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX90A-NEXT: v_cmp_gt_f32_e32 vcc, s8, v3
+; GFX90A-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX90A-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX90A-NEXT: v_fma_mix_f32 v9, -v1, s11, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX90A-NEXT: v_exp_f32_e32 v3, v3
+; GFX90A-NEXT: v_not_b32_e32 v7, 63
+; GFX90A-NEXT: v_trunc_f32_e32 v10, v9
+; GFX90A-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v10, v9
+; GFX90A-NEXT: v_cvt_f32_f16_e64 v10, -v0
+; GFX90A-NEXT: s_mov_b32 s9, 0x8000
+; GFX90A-NEXT: v_trunc_f32_e32 v9, v4
+; GFX90A-NEXT: v_ldexp_f32 v3, v3, v8
+; GFX90A-NEXT: v_xor_b32_sdwa v8, s9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX90A-NEXT: s_brev_b32 s10, -2
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v9, v4
+; GFX90A-NEXT: v_bfi_b32 v8, s10, v3, v8
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cmp_lt_f32_e64 s[4:5], |v10|, s6
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v9, v4
+; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[4:5]
+; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, 32, s[4:5]
+; GFX90A-NEXT: v_ldexp_f32 v5, |v10|, v5
+; GFX90A-NEXT: v_log_f32_e32 v5, v5
+; GFX90A-NEXT: v_cvt_f32_f16_e64 v8, -v1
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v2, 24
+; GFX90A-NEXT: v_fma_mix_f32 v1, -v1, s11, neg(0) op_sel_hi:[1,0,0]
+; GFX90A-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX90A-NEXT: v_mul_legacy_f32 v4, v8, v4
+; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s8, v4
+; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5]
+; GFX90A-NEXT: v_add_f32_e32 v4, v4, v5
; GFX90A-NEXT: v_exp_f32_e32 v4, v4
-; GFX90A-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX90A-NEXT: s_brev_b32 s11, -2
-; GFX90A-NEXT: v_mul_legacy_f32 v2, v6, v2
-; GFX90A-NEXT: v_cmp_gt_f32_e64 s[4:5], s10, v2
-; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[4:5]
-; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX90A-NEXT: v_exp_f32_e32 v2, v2
-; GFX90A-NEXT: v_ldexp_f32 v4, v4, v10
-; GFX90A-NEXT: v_cmp_class_f32_e64 s[6:7], v5, 24
-; GFX90A-NEXT: v_bfi_b32 v4, s11, v4, v8
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0x7fc00000
+; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[4:5]
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; GFX90A-NEXT: s_and_b64 vcc, s[6:7], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, v9, s[4:5]
-; GFX90A-NEXT: v_fma_mix_f32 v1, -v1, s8, neg(0) op_sel_hi:[1,0,0]
-; GFX90A-NEXT: v_ldexp_f32 v2, v2, v4
-; GFX90A-NEXT: v_trunc_f32_e32 v4, v1
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v1
-; GFX90A-NEXT: v_trunc_f32_e32 v1, v6
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v6
+; GFX90A-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX90A-NEXT: v_trunc_f32_e32 v5, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v5, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v1, v8
+; GFX90A-NEXT: v_xor_b32_sdwa v0, s9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v1, v8
+; GFX90A-NEXT: v_bfi_b32 v0, s10, v4, v0
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
-; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v6
-; GFX90A-NEXT: v_bfi_b32 v2, s11, v2, v4
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v10, 24
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v1, v8
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX90A-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v3
@@ -2688,59 +2744,62 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v7, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_f16_e64 v3, -v0
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v8, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_mov_b32_e32 v9, 0x8000
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
-; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
-; GFX10-NEXT: v_trunc_f32_e32 v10, v7
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 32, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s5
-; GFX10-NEXT: s_mov_b32 s4, 0.5
-; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX10-NEXT: v_ldexp_f32 v5, |v0|, v5
-; GFX10-NEXT: v_fma_mix_f32 v8, -v1, s4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v10, v7
-; GFX10-NEXT: v_log_f32_e32 v3, v3
-; GFX10-NEXT: v_log_f32_e32 v5, v5
-; GFX10-NEXT: v_trunc_f32_e32 v9, v8
-; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v9, v8
-; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
-; GFX10-NEXT: v_cvt_f32_f16_e64 v6, -v1
-; GFX10-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX10-NEXT: v_fma_mix_f32 v1, -v1, s4, neg(0) op_sel_hi:[1,0,0]
-; GFX10-NEXT: s_and_b32 s5, s6, s5
-; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v7, v3
-; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24
-; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
-; GFX10-NEXT: v_trunc_f32_e32 v11, v1
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v11, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, v2, s5
-; GFX10-NEXT: v_cmp_class_f32_e64 s5, v2, 24
-; GFX10-NEXT: v_add_f32_e32 v3, v3, v5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, s4
-; GFX10-NEXT: v_exp_f32_e32 v3, v3
-; GFX10-NEXT: v_add_f32_e32 v4, v4, v5
-; GFX10-NEXT: v_trunc_f32_e32 v5, v6
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v3|
+; GFX10-NEXT: v_trunc_f32_e32 v12, v8
+; GFX10-NEXT: v_xor_b32_sdwa v10, v9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_xor_b32_sdwa v0, v9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 32, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 32, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s5
+; GFX10-NEXT: s_mov_b32 s5, 0.5
+; GFX10-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX10-NEXT: v_ldexp_f32 v6, |v3|, v6
+; GFX10-NEXT: v_fma_mix_f32 v11, -v1, s5, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24
+; GFX10-NEXT: v_cmp_class_f32_e64 s9, v3, 24
+; GFX10-NEXT: v_log_f32_e32 v4, v4
+; GFX10-NEXT: v_log_f32_e32 v6, v6
+; GFX10-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX10-NEXT: v_cvt_f32_f16_e64 v7, -v1
+; GFX10-NEXT: v_sub_f32_e32 v5, v6, v5
+; GFX10-NEXT: v_fma_mix_f32 v1, -v1, s5, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_cmp_neq_f32_e64 s5, v12, v8
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v8, v4
+; GFX10-NEXT: v_trunc_f32_e32 v14, v7
+; GFX10-NEXT: v_mul_legacy_f32_e32 v5, v7, v5
+; GFX10-NEXT: v_trunc_f32_e32 v13, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s7, v14, v7
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v5
+; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v13, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s4
; GFX10-NEXT: v_exp_f32_e32 v4, v4
-; GFX10-NEXT: v_ldexp_f32 v3, v3, v8
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0xffffffc0, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v6
-; GFX10-NEXT: v_bfi_b32 v1, 0x7fffffff, v3, v1
-; GFX10-NEXT: v_ldexp_f32 v3, v4, v8
+; GFX10-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX10-NEXT: v_trunc_f32_e32 v6, v11
+; GFX10-NEXT: v_exp_f32_e32 v5, v5
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v11
+; GFX10-NEXT: v_ldexp_f32 v4, v4, v9
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v12, v8
+; GFX10-NEXT: v_bfi_b32 v6, 0x7fffffff, v4, v10
+; GFX10-NEXT: v_ldexp_f32 v5, v5, v9
; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f32_e64 s4, v5, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v10, v7
-; GFX10-NEXT: s_and_b32 s4, s6, s4
-; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v4
-; GFX10-NEXT: s_and_b32 s5, s5, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s5
+; GFX10-NEXT: s_and_b32 s4, s7, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v5, v0
+; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v14, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v0, s4
+; GFX10-NEXT: s_and_b32 s4, s8, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
+; GFX10-NEXT: s_and_b32 s4, s9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
@@ -2751,156 +2810,159 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, -v2.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, -v6.l
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, -v0.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v4, -v2.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v3|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0.5
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, |v0|, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v8, -v8.l
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v3, 24
+; GFX11-TRUE16-NEXT: v_xor_b16 v2.h, 0x8000, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v4|
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 32, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s6, v4, 24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, 0.5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v11, -v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, |v4|, v5
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v7, v7
; GFX11-TRUE16-NEXT: v_log_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v7
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v7, -v1.l
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, s0, neg(0) op_sel_hi:[1,0,0]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v5
-; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v6, v7, v6 :: v_dual_sub_f32 v5, v5, v9
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v9, -v1.l
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, s1, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v5, v8, v5 :: v_dual_mul_dx9_zero_f32 v6, v9, v6
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v1
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v12, v9
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s3, v12, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
-; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s4, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v3, v1
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, v5
-; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v7 :: v_dual_add_f32 v6, v6, v10
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v11
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v8
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v10, v1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v11, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v5, v3
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v6, v7
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s4, v11, v8
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s1, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s6, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v6, -v6
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v2|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0.5
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s1
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v0|, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, -v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v4, -v2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v3|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v8, -v8
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0x8000, v2
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v3, 24
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v4|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 32, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s1
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, |v3|, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, 0.5
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s6, v4, 24
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v4|, v5
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v7, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v5, v5
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v1, s0, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v7
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v7, -v1
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, s0, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v5
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v6, v3 :: v_dual_mul_dx9_zero_f32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v9
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v9, -v1
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, s1, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v5, v8, v5 :: v_dual_mul_dx9_zero_f32 v6, v9, v6
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v9
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, v12, v9
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s3, v12, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v10 :: v_dual_add_f32 v6, v6, v11
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v7
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s3, v11, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, s0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v10
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v7
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 1.0, v2, s0
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s1, v2, 24
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
-; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s0, v8, v7
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s3
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s4, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v12, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v9
-; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v6, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v10, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v8
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v11, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v10, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v5, v3
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v6, v7
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s4, v10, v8
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s6, s4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%x.fneg = fneg <2 x half> %x
@@ -2937,7 +2999,6 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX6-NEXT: v_not_b32_e32 v1, 63
; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fabs_lhs:
@@ -2961,7 +3022,6 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX8-NEXT: v_not_b32_e32 v1, 63
; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fabs_lhs:
@@ -2985,7 +3045,6 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX9-NEXT: v_not_b32_e32 v1, 63
; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_f32_fabs_lhs:
@@ -3009,7 +3068,6 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX90A-NEXT: v_not_b32_e32 v1, 63
; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX90A-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX90A-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_lhs:
@@ -3028,7 +3086,6 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_lhs:
@@ -3049,11 +3106,10 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
%pow = call float @llvm.pow.f32(float %fabs.x, float %y)
@@ -3080,19 +3136,19 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX6-NEXT: v_add_f32_e32 v2, v2, v3
; GFX6-NEXT: v_exp_f32_e32 v2, v2
; GFX6-NEXT: v_not_b32_e32 v3, 63
+; GFX6-NEXT: v_mul_f32_e64 v4, |v1|, 0.5
; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_trunc_f32_e32 v5, v4
; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
-; GFX6-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
-; GFX6-NEXT: v_trunc_f32_e32 v4, v3
-; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX6-NEXT: v_trunc_f32_e64 v3, |v1|
-; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, |v1|
-; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
; GFX6-NEXT: s_brev_b32 s4, -2
-; GFX6-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX6-NEXT: v_trunc_f32_e64 v4, |v1|
+; GFX6-NEXT: v_bfi_b32 v3, s4, v2, v0
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, |v1|
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX6-NEXT: v_cmp_neq_f32_e64 s[6:7], v3, |v1|
+; GFX6-NEXT: v_cmp_neq_f32_e64 s[6:7], v4, |v1|
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -3117,19 +3173,19 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
; GFX8-NEXT: v_exp_f32_e32 v2, v2
; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_mul_f32_e64 v4, |v1|, 0.5
; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_trunc_f32_e32 v5, v4
; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX8-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
-; GFX8-NEXT: v_trunc_f32_e32 v4, v3
-; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX8-NEXT: v_trunc_f32_e64 v3, |v1|
-; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, |v1|
-; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
; GFX8-NEXT: s_brev_b32 s4, -2
-; GFX8-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX8-NEXT: v_trunc_f32_e64 v4, |v1|
+; GFX8-NEXT: v_bfi_b32 v3, s4, v2, v0
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, |v1|
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX8-NEXT: v_cmp_neq_f32_e64 s[6:7], v3, |v1|
+; GFX8-NEXT: v_cmp_neq_f32_e64 s[6:7], v4, |v1|
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -3154,19 +3210,19 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX9-NEXT: v_add_f32_e32 v2, v2, v3
; GFX9-NEXT: v_exp_f32_e32 v2, v2
; GFX9-NEXT: v_not_b32_e32 v3, 63
+; GFX9-NEXT: v_mul_f32_e64 v4, |v1|, 0.5
; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_trunc_f32_e32 v5, v4
; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX9-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
-; GFX9-NEXT: v_trunc_f32_e32 v4, v3
-; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX9-NEXT: v_trunc_f32_e64 v3, |v1|
-; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, |v1|
-; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX9-NEXT: v_trunc_f32_e64 v4, |v1|
+; GFX9-NEXT: v_bfi_b32 v3, s4, v2, v0
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, |v1|
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX9-NEXT: v_cmp_neq_f32_e64 s[6:7], v3, |v1|
+; GFX9-NEXT: v_cmp_neq_f32_e64 s[6:7], v4, |v1|
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -3191,19 +3247,19 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX90A-NEXT: v_add_f32_e32 v2, v2, v3
; GFX90A-NEXT: v_exp_f32_e32 v2, v2
; GFX90A-NEXT: v_not_b32_e32 v3, 63
+; GFX90A-NEXT: v_mul_f32_e64 v4, |v1|, 0.5
; GFX90A-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX90A-NEXT: v_trunc_f32_e32 v5, v4
; GFX90A-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX90A-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
-; GFX90A-NEXT: v_trunc_f32_e32 v4, v3
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX90A-NEXT: v_trunc_f32_e64 v3, |v1|
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, |v1|
-; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
; GFX90A-NEXT: s_brev_b32 s4, -2
-; GFX90A-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX90A-NEXT: v_trunc_f32_e64 v4, |v1|
+; GFX90A-NEXT: v_bfi_b32 v3, s4, v2, v0
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, |v1|
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX90A-NEXT: v_cmp_neq_f32_e64 s[6:7], v3, |v1|
+; GFX90A-NEXT: v_cmp_neq_f32_e64 s[6:7], v4, |v1|
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX90A-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], s[6:7]
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -3213,29 +3269,29 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
-; GFX10-NEXT: v_trunc_f32_e64 v4, |v1|
+; GFX10-NEXT: v_trunc_f32_e64 v6, |v1|
+; GFX10-NEXT: v_cmp_class_f32_e64 s5, v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v4, |v1|
-; GFX10-NEXT: v_cmp_neq_f32_e64 s5, v4, |v1|
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v6, |v1|
+; GFX10-NEXT: v_cmp_neq_f32_e64 s6, v6, |v1|
; GFX10-NEXT: v_ldexp_f32 v3, |v0|, v3
; GFX10-NEXT: v_log_f32_e32 v3, v3
; GFX10-NEXT: v_sub_f32_e32 v2, v3, v2
; GFX10-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
; GFX10-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
; GFX10-NEXT: v_exp_f32_e32 v2, v2
; GFX10-NEXT: v_trunc_f32_e32 v5, v3
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
-; GFX10-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v4
; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
-; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24
-; GFX10-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX10-NEXT: s_and_b32 s4, s4, s5
-; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
+; GFX10-NEXT: s_and_b32 s4, s5, s6
+; GFX10-NEXT: v_bfi_b32 v3, 0x7fffffff, v2, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -3243,12 +3299,13 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-NEXT: v_trunc_f32_e64 v4, |v1|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_trunc_f32_e64 v6, |v1|
+; GFX11-NEXT: v_cmp_class_f32_e64 s1, v0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
-; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v4, |v1|
-; GFX11-NEXT: v_cmp_neq_f32_e64 s1, v4, |v1|
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v6, |v1|
+; GFX11-NEXT: v_cmp_neq_f32_e64 s2, v6, |v1|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v3, |v0|, v3
; GFX11-NEXT: v_log_f32_e32 v3, v3
@@ -3258,7 +3315,7 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v2, |v1|, v2
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_f32_e32 v2, v2, v3
; GFX11-NEXT: v_mul_f32_e64 v3, |v1|, 0.5
@@ -3267,13 +3324,13 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX11-NEXT: v_trunc_f32_e32 v5, v3
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v4
; GFX11-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
-; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX11-NEXT: s_and_b32 s0, s0, s1
+; GFX11-NEXT: s_and_b32 s0, s1, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
+; GFX11-NEXT: v_bfi_b32 v3, 0x7fffffff, v2, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call float @llvm.fabs.f32(float %y)
@@ -3303,7 +3360,6 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX6-NEXT: v_not_b32_e32 v1, 63
; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs:
@@ -3327,7 +3383,6 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX8-NEXT: v_not_b32_e32 v1, 63
; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs:
@@ -3351,7 +3406,6 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX9-NEXT: v_not_b32_e32 v1, 63
; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_f32_fabs_lhs_rhs:
@@ -3375,7 +3429,6 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX90A-NEXT: v_not_b32_e32 v1, 63
; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX90A-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX90A-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs:
@@ -3394,7 +3447,6 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_lhs_rhs:
@@ -3415,11 +3467,10 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
%fabs.y = call float @llvm.fabs.f32(float %y)
@@ -3440,6 +3491,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX6-NEXT: v_ldexp_f32_e64 v2, |s0|, v2
; GFX6-NEXT: v_log_f32_e32 v2, v2
; GFX6-NEXT: s_mov_b32 s1, 0xc2fc0000
+; GFX6-NEXT: v_mul_f32_e32 v3, 0.5, v0
+; GFX6-NEXT: v_trunc_f32_e32 v4, v3
; GFX6-NEXT: v_sub_f32_e32 v1, v2, v1
; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v0, v1
; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
@@ -3449,19 +3502,17 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX6-NEXT: v_exp_f32_e32 v1, v1
; GFX6-NEXT: v_not_b32_e32 v2, 63
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX6-NEXT: s_brev_b32 s1, -2
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v0
; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
-; GFX6-NEXT: v_mul_f32_e32 v2, 0.5, v0
-; GFX6-NEXT: v_trunc_f32_e32 v3, v2
-; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
-; GFX6-NEXT: v_trunc_f32_e32 v2, v0
-; GFX6-NEXT: v_cmp_eq_f32_e64 s[2:3], v2, v0
-; GFX6-NEXT: v_mov_b32_e32 v3, s0
+; GFX6-NEXT: s_brev_b32 s1, -2
+; GFX6-NEXT: v_mov_b32_e32 v2, s0
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[2:3], v3, v0
+; GFX6-NEXT: v_bfi_b32 v2, s1, v1, v2
; GFX6-NEXT: s_and_b64 vcc, s[2:3], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
-; GFX6-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v2, v0
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v3, v0
; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[0:1], vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -3479,6 +3530,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX8-NEXT: v_ldexp_f32 v2, |s0|, v2
; GFX8-NEXT: v_log_f32_e32 v2, v2
; GFX8-NEXT: s_mov_b32 s1, 0xc2fc0000
+; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v0
+; GFX8-NEXT: v_trunc_f32_e32 v4, v3
; GFX8-NEXT: v_sub_f32_e32 v1, v2, v1
; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
@@ -3488,19 +3541,17 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX8-NEXT: v_exp_f32_e32 v1, v1
; GFX8-NEXT: v_not_b32_e32 v2, 63
; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX8-NEXT: s_brev_b32 s1, -2
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, v0
; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX8-NEXT: v_mul_f32_e32 v2, 0.5, v0
-; GFX8-NEXT: v_trunc_f32_e32 v3, v2
-; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
-; GFX8-NEXT: v_trunc_f32_e32 v2, v0
-; GFX8-NEXT: v_cmp_eq_f32_e64 s[2:3], v2, v0
-; GFX8-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NEXT: s_brev_b32 s1, -2
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[2:3], v3, v0
+; GFX8-NEXT: v_bfi_b32 v2, s1, v1, v2
; GFX8-NEXT: s_and_b64 vcc, s[2:3], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
-; GFX8-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX8-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
-; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v2, v0
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v3, v0
; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[0:1], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -3518,6 +3569,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX9-NEXT: v_ldexp_f32 v2, |s0|, v2
; GFX9-NEXT: v_log_f32_e32 v2, v2
; GFX9-NEXT: s_mov_b32 s1, 0xc2fc0000
+; GFX9-NEXT: v_mul_f32_e32 v3, 0.5, v0
+; GFX9-NEXT: v_trunc_f32_e32 v4, v3
; GFX9-NEXT: v_sub_f32_e32 v1, v2, v1
; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
@@ -3527,19 +3580,17 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX9-NEXT: v_exp_f32_e32 v1, v1
; GFX9-NEXT: v_not_b32_e32 v2, 63
; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX9-NEXT: s_brev_b32 s1, -2
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v0
; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX9-NEXT: v_mul_f32_e32 v2, 0.5, v0
-; GFX9-NEXT: v_trunc_f32_e32 v3, v2
-; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
-; GFX9-NEXT: v_trunc_f32_e32 v2, v0
-; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], v2, v0
-; GFX9-NEXT: v_mov_b32_e32 v3, s0
+; GFX9-NEXT: s_brev_b32 s1, -2
+; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], v3, v0
+; GFX9-NEXT: v_bfi_b32 v2, s1, v1, v2
; GFX9-NEXT: s_and_b64 vcc, s[2:3], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
-; GFX9-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX9-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
-; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v2, v0
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v3, v0
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX9-NEXT: s_and_b64 vcc, s[0:1], vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -3557,6 +3608,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX90A-NEXT: v_ldexp_f32 v2, |s0|, v2
; GFX90A-NEXT: v_log_f32_e32 v2, v2
; GFX90A-NEXT: s_mov_b32 s1, 0xc2fc0000
+; GFX90A-NEXT: v_mul_f32_e32 v3, 0.5, v0
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v3
; GFX90A-NEXT: v_sub_f32_e32 v1, v2, v1
; GFX90A-NEXT: v_mul_legacy_f32 v1, v0, v1
; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42800000
@@ -3566,19 +3619,17 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX90A-NEXT: v_exp_f32_e32 v1, v1
; GFX90A-NEXT: v_not_b32_e32 v2, 63
; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX90A-NEXT: s_brev_b32 s1, -2
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX90A-NEXT: v_trunc_f32_e32 v3, v0
; GFX90A-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX90A-NEXT: v_mul_f32_e32 v2, 0.5, v0
-; GFX90A-NEXT: v_trunc_f32_e32 v3, v2
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
-; GFX90A-NEXT: v_trunc_f32_e32 v2, v0
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[2:3], v2, v0
-; GFX90A-NEXT: v_mov_b32_e32 v3, s0
+; GFX90A-NEXT: s_brev_b32 s1, -2
+; GFX90A-NEXT: v_mov_b32_e32 v2, s0
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[2:3], v3, v0
+; GFX90A-NEXT: v_bfi_b32 v2, s1, v1, v2
; GFX90A-NEXT: s_and_b64 vcc, s[2:3], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
-; GFX90A-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX90A-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v2, v0
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v3, v0
; GFX90A-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX90A-NEXT: s_and_b64 vcc, s[0:1], vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -3587,43 +3638,44 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX10-LABEL: v_pow_f32_sgpr_vgpr:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0|
-; GFX10-NEXT: v_trunc_f32_e32 v3, v0
+; GFX10-NEXT: v_trunc_f32_e32 v5, v0
+; GFX10-NEXT: v_cmp_class_f32_e64 s2, s0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s1
; GFX10-NEXT: s_and_b32 s1, s1, exec_lo
; GFX10-NEXT: s_cselect_b32 s1, 32, 0
; GFX10-NEXT: v_ldexp_f32 v2, |s0|, s1
-; GFX10-NEXT: v_cmp_eq_f32_e64 s1, v3, v0
+; GFX10-NEXT: v_cmp_eq_f32_e64 s1, v5, v0
; GFX10-NEXT: v_log_f32_e32 v2, v2
; GFX10-NEXT: v_sub_f32_e32 v1, v2, v1
; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v0, v1
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_add_f32_e32 v1, v1, v2
; GFX10-NEXT: v_mul_f32_e32 v2, 0.5, v0
; GFX10-NEXT: v_exp_f32_e32 v1, v1
; GFX10-NEXT: v_trunc_f32_e32 v4, v2
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v4, v2
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
-; GFX10-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v3, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, s0, s1
-; GFX10-NEXT: v_cmp_class_f32_e64 s0, s0, 24
-; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v2
-; GFX10-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX10-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
+; GFX10-NEXT: v_bfi_b32 v2, 0x7fffffff, v1, s0
+; GFX10-NEXT: v_cmp_neq_f32_e64 s0, v5, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX10-NEXT: s_and_b32 s0, s2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_pow_f32_sgpr_vgpr:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0|
-; GFX11-NEXT: v_trunc_f32_e32 v3, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_trunc_f32_e32 v5, v0
+; GFX11-NEXT: v_cmp_class_f32_e64 s2, s0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s1
; GFX11-NEXT: s_and_b32 s1, s1, exec_lo
; GFX11-NEXT: s_cselect_b32 s1, 32, 0
; GFX11-NEXT: v_ldexp_f32 v2, |s0|, s1
-; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v3, v0
+; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v5, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -3632,22 +3684,21 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mul_f32 v2, 0.5, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v1, v1
; GFX11-NEXT: v_trunc_f32_e32 v4, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v4, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v5
-; GFX11-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX11-NEXT: v_cmp_neq_f32_e32 vcc_lo, v3, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, s0, s1
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, s0, 24
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX11-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
+; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v1, s0
+; GFX11-NEXT: v_cmp_neq_f32_e64 s0, v5, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v2
-; GFX11-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-NEXT: s_and_b32 s0, s2, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: ; return to shader part epilog
@@ -3673,20 +3724,20 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX6-NEXT: v_add_f32_e32 v1, v1, v2
; GFX6-NEXT: v_exp_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_f32_e64 v3, s0, 0.5
; GFX6-NEXT: v_not_b32_e32 v2, 63
+; GFX6-NEXT: v_trunc_f32_e32 v4, v3
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX6-NEXT: s_brev_b32 s1, -2
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, s0
; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
-; GFX6-NEXT: v_mul_f32_e64 v2, s0, 0.5
-; GFX6-NEXT: v_trunc_f32_e32 v3, v2
-; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
-; GFX6-NEXT: v_trunc_f32_e32 v2, s0
-; GFX6-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, v2
+; GFX6-NEXT: s_brev_b32 s1, -2
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, v3
+; GFX6-NEXT: v_bfi_b32 v2, s1, v1, v0
; GFX6-NEXT: s_and_b64 vcc, s[2:3], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_cmp_class_f32_e64 s[2:3], v0, 24
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, s0, v2
-; GFX6-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, s0, v3
; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[2:3], vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -3709,20 +3760,20 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX8-NEXT: v_add_f32_e32 v1, v1, v2
; GFX8-NEXT: v_exp_f32_e32 v1, v1
+; GFX8-NEXT: v_mul_f32_e64 v3, s0, 0.5
; GFX8-NEXT: v_not_b32_e32 v2, 63
+; GFX8-NEXT: v_trunc_f32_e32 v4, v3
; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX8-NEXT: s_brev_b32 s1, -2
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX8-NEXT: v_trunc_f32_e32 v3, s0
; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX8-NEXT: v_mul_f32_e64 v2, s0, 0.5
-; GFX8-NEXT: v_trunc_f32_e32 v3, v2
-; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
-; GFX8-NEXT: v_trunc_f32_e32 v2, s0
-; GFX8-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, v2
+; GFX8-NEXT: s_brev_b32 s1, -2
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, v3
+; GFX8-NEXT: v_bfi_b32 v2, s1, v1, v0
; GFX8-NEXT: s_and_b64 vcc, s[2:3], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX8-NEXT: v_cmp_class_f32_e64 s[2:3], v0, 24
-; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, s0, v2
-; GFX8-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, s0, v3
; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[2:3], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -3745,20 +3796,20 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX9-NEXT: v_add_f32_e32 v1, v1, v2
; GFX9-NEXT: v_exp_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_f32_e64 v3, s0, 0.5
; GFX9-NEXT: v_not_b32_e32 v2, 63
+; GFX9-NEXT: v_trunc_f32_e32 v4, v3
; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX9-NEXT: s_brev_b32 s1, -2
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, s0
; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX9-NEXT: v_mul_f32_e64 v2, s0, 0.5
-; GFX9-NEXT: v_trunc_f32_e32 v3, v2
-; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
-; GFX9-NEXT: v_trunc_f32_e32 v2, s0
-; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, v2
+; GFX9-NEXT: s_brev_b32 s1, -2
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, v3
+; GFX9-NEXT: v_bfi_b32 v2, s1, v1, v0
; GFX9-NEXT: s_and_b64 vcc, s[2:3], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX9-NEXT: v_cmp_class_f32_e64 s[2:3], v0, 24
-; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, s0, v2
-; GFX9-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, s0, v3
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX9-NEXT: s_and_b64 vcc, s[2:3], vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -3781,20 +3832,20 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX90A-NEXT: v_add_f32_e32 v1, v1, v2
; GFX90A-NEXT: v_exp_f32_e32 v1, v1
+; GFX90A-NEXT: v_mul_f32_e64 v3, s0, 0.5
; GFX90A-NEXT: v_not_b32_e32 v2, 63
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v3
; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX90A-NEXT: s_brev_b32 s1, -2
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX90A-NEXT: v_trunc_f32_e32 v3, s0
; GFX90A-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX90A-NEXT: v_mul_f32_e64 v2, s0, 0.5
-; GFX90A-NEXT: v_trunc_f32_e32 v3, v2
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
-; GFX90A-NEXT: v_trunc_f32_e32 v2, s0
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, v2
+; GFX90A-NEXT: s_brev_b32 s1, -2
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, v3
+; GFX90A-NEXT: v_bfi_b32 v2, s1, v1, v0
; GFX90A-NEXT: s_and_b64 vcc, s[2:3], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX90A-NEXT: v_cmp_class_f32_e64 s[2:3], v0, 24
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, s0, v2
-; GFX90A-NEXT: v_bfi_b32 v1, s1, v1, v3
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, s0, v3
; GFX90A-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX90A-NEXT: s_and_b64 vcc, s[2:3], vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -3803,40 +3854,41 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX10-LABEL: v_pow_f32_vgpr_sgpr:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
-; GFX10-NEXT: v_trunc_f32_e32 v3, s0
+; GFX10-NEXT: v_trunc_f32_e32 v5, s0
+; GFX10-NEXT: v_cmp_class_f32_e64 s2, v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 32, s1
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s1
-; GFX10-NEXT: v_cmp_eq_f32_e64 s1, s0, v3
+; GFX10-NEXT: v_cmp_eq_f32_e64 s1, s0, v5
; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX10-NEXT: v_log_f32_e32 v2, v2
; GFX10-NEXT: v_sub_f32_e32 v1, v2, v1
; GFX10-NEXT: v_mul_legacy_f32_e32 v1, s0, v1
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_add_f32_e32 v1, v1, v2
; GFX10-NEXT: v_mul_f32_e64 v2, s0, 0.5
+; GFX10-NEXT: v_cmp_neq_f32_e64 s0, s0, v5
; GFX10-NEXT: v_exp_f32_e32 v1, v1
; GFX10-NEXT: v_trunc_f32_e32 v4, v2
+; GFX10-NEXT: s_and_b32 s0, s2, s0
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v4, v2
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v3
; GFX10-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
-; GFX10-NEXT: v_cmp_class_f32_e64 s1, v0, 24
-; GFX10-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, s0, v3
-; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v2
-; GFX10-NEXT: s_and_b32 s0, s1, vcc_lo
+; GFX10-NEXT: v_bfi_b32 v2, 0x7fffffff, v1, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_pow_f32_vgpr_sgpr:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
-; GFX11-NEXT: v_trunc_f32_e32 v3, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_trunc_f32_e32 v5, s0
+; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 32, s1
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s1
-; GFX11-NEXT: v_cmp_eq_f32_e64 s1, s0, v3
+; GFX11-NEXT: v_cmp_eq_f32_e64 s1, s0, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2
; GFX11-NEXT: v_log_f32_e32 v2, v2
@@ -3846,24 +3898,23 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, s0, v1
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
; GFX11-NEXT: v_mul_f32_e64 v2, s0, 0.5
+; GFX11-NEXT: v_cmp_neq_f32_e64 s0, s0, v5
; GFX11-NEXT: v_exp_f32_e32 v1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_trunc_f32_e32 v4, v2
+; GFX11-NEXT: s_and_b32 s0, s2, s0
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v4, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
; GFX11-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
-; GFX11-NEXT: v_cmp_class_f32_e64 s1, v0, 24
-; GFX11-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc_lo
-; GFX11-NEXT: v_cmp_neq_f32_e32 vcc_lo, s0, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v2
-; GFX11-NEXT: s_and_b32 s0, s1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v1, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
@@ -3883,6 +3934,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX6-NEXT: v_ldexp_f32_e64 v1, |s0|, v1
; GFX6-NEXT: v_log_f32_e32 v1, v1
; GFX6-NEXT: s_mov_b32 s2, 0xc2fc0000
+; GFX6-NEXT: v_mul_f32_e64 v2, s1, 0.5
+; GFX6-NEXT: v_trunc_f32_e32 v3, v2
; GFX6-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
; GFX6-NEXT: v_mov_b32_e32 v1, 0x42800000
@@ -3890,21 +3943,19 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
; GFX6-NEXT: v_exp_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_f32_e64 v1, s1, 0.5
; GFX6-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX6-NEXT: v_trunc_f32_e32 v2, v1
; GFX6-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
-; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v2, v1
-; GFX6-NEXT: v_trunc_f32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s2
-; GFX6-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, v1
-; GFX6-NEXT: v_mov_b32_e32 v2, s0
-; GFX6-NEXT: s_and_b64 vcc, s[2:3], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX6-NEXT: s_brev_b32 s2, -2
-; GFX6-NEXT: v_bfi_b32 v0, s2, v0, v2
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, s1
+; GFX6-NEXT: v_bfi_b32 v1, s2, v0, v1
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, v2
+; GFX6-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: v_cmp_class_f32_e64 s[2:3], s0, 24
-; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, s1, v1
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, s1, v2
; GFX6-NEXT: v_mov_b32_e32 v1, 0x7fc00000
; GFX6-NEXT: s_and_b64 vcc, s[2:3], vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
@@ -3922,6 +3973,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX8-NEXT: v_ldexp_f32 v1, |s0|, v1
; GFX8-NEXT: v_log_f32_e32 v1, v1
; GFX8-NEXT: s_mov_b32 s2, 0xc2fc0000
+; GFX8-NEXT: v_mul_f32_e64 v2, s1, 0.5
+; GFX8-NEXT: v_trunc_f32_e32 v3, v2
; GFX8-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
; GFX8-NEXT: v_mov_b32_e32 v1, 0x42800000
@@ -3929,21 +3982,19 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_f32_e64 v1, s1, 0.5
; GFX8-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX8-NEXT: v_trunc_f32_e32 v2, v1
; GFX8-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
-; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v2, v1
-; GFX8-NEXT: v_trunc_f32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: v_ldexp_f32 v0, v0, s2
-; GFX8-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, v1
-; GFX8-NEXT: v_mov_b32_e32 v2, s0
-; GFX8-NEXT: s_and_b64 vcc, s[2:3], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX8-NEXT: s_brev_b32 s2, -2
-; GFX8-NEXT: v_bfi_b32 v0, s2, v0, v2
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX8-NEXT: v_trunc_f32_e32 v2, s1
+; GFX8-NEXT: v_bfi_b32 v1, s2, v0, v1
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, v2
+; GFX8-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: v_cmp_class_f32_e64 s[2:3], s0, 24
-; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, s1, v1
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, s1, v2
; GFX8-NEXT: v_mov_b32_e32 v1, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[2:3], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
@@ -3961,6 +4012,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX9-NEXT: v_ldexp_f32 v1, |s0|, v1
; GFX9-NEXT: v_log_f32_e32 v1, v1
; GFX9-NEXT: s_mov_b32 s2, 0xc2fc0000
+; GFX9-NEXT: v_mul_f32_e64 v2, s1, 0.5
+; GFX9-NEXT: v_trunc_f32_e32 v3, v2
; GFX9-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 0x42800000
@@ -3968,21 +4021,19 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_f32_e64 v1, s1, 0.5
; GFX9-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX9-NEXT: v_trunc_f32_e32 v2, v1
; GFX9-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
-; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v2, v1
-; GFX9-NEXT: v_trunc_f32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: v_ldexp_f32 v0, v0, s2
-; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s0
-; GFX9-NEXT: s_and_b64 vcc, s[2:3], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX9-NEXT: s_brev_b32 s2, -2
-; GFX9-NEXT: v_bfi_b32 v0, s2, v0, v2
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX9-NEXT: v_trunc_f32_e32 v2, s1
+; GFX9-NEXT: v_bfi_b32 v1, s2, v0, v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, v2
+; GFX9-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT: v_cmp_class_f32_e64 s[2:3], s0, 24
-; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, s1, v1
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, s1, v2
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7fc00000
; GFX9-NEXT: s_and_b64 vcc, s[2:3], vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
@@ -4000,6 +4051,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX90A-NEXT: v_ldexp_f32 v1, |s0|, v1
; GFX90A-NEXT: v_log_f32_e32 v1, v1
; GFX90A-NEXT: s_mov_b32 s2, 0xc2fc0000
+; GFX90A-NEXT: v_mul_f32_e64 v2, s1, 0.5
+; GFX90A-NEXT: v_trunc_f32_e32 v3, v2
; GFX90A-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX90A-NEXT: v_mul_legacy_f32 v0, s1, v0
; GFX90A-NEXT: v_mov_b32_e32 v1, 0x42800000
@@ -4007,21 +4060,19 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX90A-NEXT: v_add_f32_e32 v0, v0, v1
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
-; GFX90A-NEXT: v_mul_f32_e64 v1, s1, 0.5
; GFX90A-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX90A-NEXT: v_trunc_f32_e32 v2, v1
; GFX90A-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
-; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v2, v1
-; GFX90A-NEXT: v_trunc_f32_e32 v1, s1
+; GFX90A-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-NEXT: v_ldexp_f32 v0, v0, s2
-; GFX90A-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, v1
-; GFX90A-NEXT: v_mov_b32_e32 v2, s0
-; GFX90A-NEXT: s_and_b64 vcc, s[2:3], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX90A-NEXT: s_brev_b32 s2, -2
-; GFX90A-NEXT: v_bfi_b32 v0, s2, v0, v2
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2
+; GFX90A-NEXT: v_trunc_f32_e32 v2, s1
+; GFX90A-NEXT: v_bfi_b32 v1, s2, v0, v1
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, v2
+; GFX90A-NEXT: s_and_b64 vcc, s[2:3], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX90A-NEXT: v_cmp_class_f32_e64 s[2:3], s0, 24
-; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, s1, v1
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, s1, v2
; GFX90A-NEXT: v_mov_b32_e32 v1, 0x7fc00000
; GFX90A-NEXT: s_and_b64 vcc, s[2:3], vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
@@ -4030,70 +4081,69 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX10-LABEL: v_pow_f32_sgpr_sgpr:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0|
-; GFX10-NEXT: v_trunc_f32_e32 v2, s1
+; GFX10-NEXT: v_trunc_f32_e32 v3, s1
+; GFX10-NEXT: v_cmp_class_f32_e64 s3, s0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s2
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
; GFX10-NEXT: s_cselect_b32 s2, 32, 0
; GFX10-NEXT: v_ldexp_f32 v1, |s0|, s2
-; GFX10-NEXT: v_cmp_eq_f32_e64 s2, s1, v2
; GFX10-NEXT: v_log_f32_e32 v1, v1
; GFX10-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: s_and_b32 s4, vcc_lo, exec_lo
-; GFX10-NEXT: s_cselect_b32 s4, 0xffffffc0, 0
-; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, s1, v2
+; GFX10-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-NEXT: v_mul_f32_e64 v1, s1, 0.5
; GFX10-NEXT: v_exp_f32_e32 v0, v0
-; GFX10-NEXT: v_trunc_f32_e32 v3, v1
-; GFX10-NEXT: v_cmp_lg_f32_e64 s3, v3, v1
-; GFX10-NEXT: v_ldexp_f32 v0, v0, s4
-; GFX10-NEXT: s_and_b32 s2, s2, s3
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, s0, s2
-; GFX10-NEXT: v_cmp_class_f32_e64 s0, s0, 24
-; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1
-; GFX10-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX10-NEXT: v_trunc_f32_e32 v2, v1
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v2, v1
+; GFX10-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX10-NEXT: v_cmp_eq_f32_e64 s2, s1, v3
+; GFX10-NEXT: v_bfi_b32 v1, 0x7fffffff, v0, s0
+; GFX10-NEXT: v_cmp_neq_f32_e64 s0, s1, v3
+; GFX10-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX10-NEXT: s_and_b32 s0, s3, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_pow_f32_sgpr_sgpr:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0|
-; GFX11-NEXT: v_trunc_f32_e32 v2, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_trunc_f32_e32 v3, s1
+; GFX11-NEXT: v_cmp_class_f32_e64 s3, s0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s2
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-NEXT: s_cselect_b32 s2, 32, 0
; GFX11-NEXT: v_ldexp_f32 v1, |s0|, s2
-; GFX11-NEXT: v_cmp_eq_f32_e64 s2, s1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v1, v1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: s_and_b32 s4, vcc_lo, exec_lo
-; GFX11-NEXT: s_cselect_b32 s4, 0xffffffc0, 0
-; GFX11-NEXT: v_cmp_neq_f32_e32 vcc_lo, s1, v2
+; GFX11-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
; GFX11-NEXT: v_mul_f32_e64 v1, s1, 0.5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: v_trunc_f32_e32 v3, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_cmp_lg_f32_e64 s3, v3, v1
+; GFX11-NEXT: v_trunc_f32_e32 v2, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v2, v1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, s4
-; GFX11-NEXT: s_and_b32 s2, s2, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, s0, s2
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, s0, 24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1
-; GFX11-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX11-NEXT: v_cmp_eq_f32_e64 s2, s1, v3
+; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v0, s0
+; GFX11-NEXT: v_cmp_neq_f32_e64 s0, s1, v3
+; GFX11-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-NEXT: s_and_b32 s0, s3, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: ; return to shader part epilog
@@ -4264,7 +4314,6 @@ define float @v_pow_f32_const_even_int(float %x) {
; GFX6-NEXT: v_not_b32_e32 v1, 63
; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_const_even_int:
@@ -4288,7 +4337,6 @@ define float @v_pow_f32_const_even_int(float %x) {
; GFX8-NEXT: v_not_b32_e32 v1, 63
; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_const_even_int:
@@ -4312,7 +4360,6 @@ define float @v_pow_f32_const_even_int(float %x) {
; GFX9-NEXT: v_not_b32_e32 v1, 63
; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_f32_const_even_int:
@@ -4336,7 +4383,6 @@ define float @v_pow_f32_const_even_int(float %x) {
; GFX90A-NEXT: v_not_b32_e32 v1, 63
; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX90A-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX90A-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_const_even_int:
@@ -4355,7 +4401,6 @@ define float @v_pow_f32_const_even_int(float %x) {
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_const_even_int:
@@ -4376,11 +4421,10 @@ define float @v_pow_f32_const_even_int(float %x) {
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call float @llvm.pow.f32(float %x, float 2.0)
ret float %pow
@@ -4556,10 +4600,10 @@ define float @v_pow_f32_const_non_int(float %x) {
; GFX6-NEXT: v_exp_f32_e32 v1, v1
; GFX6-NEXT: v_not_b32_e32 v2, 63
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX6-NEXT: v_cmp_class_f32_e64 vcc, v0, 24
; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GFX6-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_const_non_int:
@@ -4582,10 +4626,10 @@ define float @v_pow_f32_const_non_int(float %x) {
; GFX8-NEXT: v_exp_f32_e32 v1, v1
; GFX8-NEXT: v_not_b32_e32 v2, 63
; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v0, 24
; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_const_non_int:
@@ -4608,10 +4652,10 @@ define float @v_pow_f32_const_non_int(float %x) {
; GFX9-NEXT: v_exp_f32_e32 v1, v1
; GFX9-NEXT: v_not_b32_e32 v2, 63
; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, 24
; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GFX9-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_f32_const_non_int:
@@ -4634,10 +4678,10 @@ define float @v_pow_f32_const_non_int(float %x) {
; GFX90A-NEXT: v_exp_f32_e32 v1, v1
; GFX90A-NEXT: v_not_b32_e32 v2, 63
; GFX90A-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
+; GFX90A-NEXT: v_cmp_class_f32_e64 vcc, v0, 24
; GFX90A-NEXT: v_ldexp_f32 v1, v1, v2
; GFX90A-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GFX90A-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, s[4:5]
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_const_non_int:
@@ -4657,7 +4701,7 @@ define float @v_pow_f32_const_non_int(float %x) {
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v1, v1
; GFX10-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v0, |v1|, 0x7fc00000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, 0x7fc00000, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_const_non_int:
@@ -4683,7 +4727,7 @@ define float @v_pow_f32_const_non_int(float %x) {
; GFX11-NEXT: v_exp_f32_e32 v1, v1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, |v1|, 0x7fc00000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call float @llvm.pow.f32(float %x, float 5.000000e-01)
ret float %pow
@@ -4710,16 +4754,16 @@ define float @v_pow_f32_nnan(float %x, float %y) {
; GFX6-NEXT: v_exp_f32_e32 v2, v2
; GFX6-NEXT: v_not_b32_e32 v3, 63
; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3
; GFX6-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX6-NEXT: v_trunc_f32_e32 v4, v3
; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_bfi_b32 v0, s4, v2, v0
; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
-; GFX6-NEXT: s_brev_b32 s4, -2
-; GFX6-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_nnan:
@@ -4742,16 +4786,16 @@ define float @v_pow_f32_nnan(float %x, float %y) {
; GFX8-NEXT: v_exp_f32_e32 v2, v2
; GFX8-NEXT: v_not_b32_e32 v3, 63
; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX8-NEXT: v_trunc_f32_e32 v4, v3
; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_bfi_b32 v0, s4, v2, v0
; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
-; GFX8-NEXT: s_brev_b32 s4, -2
-; GFX8-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_nnan:
@@ -4774,16 +4818,16 @@ define float @v_pow_f32_nnan(float %x, float %y) {
; GFX9-NEXT: v_exp_f32_e32 v2, v2
; GFX9-NEXT: v_not_b32_e32 v3, 63
; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: s_brev_b32 s4, -2
; GFX9-NEXT: v_ldexp_f32 v2, v2, v3
; GFX9-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX9-NEXT: v_trunc_f32_e32 v4, v3
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_bfi_b32 v0, s4, v2, v0
; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
-; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_pow_f32_nnan:
@@ -4806,53 +4850,53 @@ define float @v_pow_f32_nnan(float %x, float %y) {
; GFX90A-NEXT: v_exp_f32_e32 v2, v2
; GFX90A-NEXT: v_not_b32_e32 v3, 63
; GFX90A-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX90A-NEXT: s_brev_b32 s4, -2
; GFX90A-NEXT: v_ldexp_f32 v2, v2, v3
; GFX90A-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX90A-NEXT: v_trunc_f32_e32 v4, v3
; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
; GFX90A-NEXT: v_trunc_f32_e32 v3, v1
+; GFX90A-NEXT: v_bfi_b32 v0, s4, v2, v0
; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX90A-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
-; GFX90A-NEXT: s_brev_b32 s4, -2
-; GFX90A-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_nnan:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
-; GFX10-NEXT: v_trunc_f32_e32 v4, v1
+; GFX10-NEXT: v_trunc_f32_e32 v6, v1
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 32, s4
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v4, v1
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v6, v1
; GFX10-NEXT: v_ldexp_f32 v3, |v0|, v3
; GFX10-NEXT: v_log_f32_e32 v3, v3
; GFX10-NEXT: v_sub_f32_e32 v2, v3, v2
; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v2, v2
; GFX10-NEXT: v_trunc_f32_e32 v5, v3
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
-; GFX10-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v4
; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
-; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX10-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_nnan:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-NEXT: v_trunc_f32_e32 v4, v1
+; GFX11-NEXT: v_trunc_f32_e32 v6, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
-; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v4, v1
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v6, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v3, |v0|, v3
; GFX11-NEXT: v_log_f32_e32 v3, v3
@@ -4862,24 +4906,161 @@ define float @v_pow_f32_nnan(float %x, float %y) {
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_exp_f32_e32 v2, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_trunc_f32_e32 v5, v3
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v4
; GFX11-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call nnan float @llvm.pow.f32(float %x, float %y)
ret float %pow
}
+define float @v_pow_f32_daz(float %x, float %y) #0 {
+; GFX6-LABEL: v_pow_f32_daz:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_log_f32_e64 v2, |v0|
+; GFX6-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX6-NEXT: v_trunc_f32_e32 v4, v3
+; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_exp_f32_e32 v2, v2
+; GFX6-NEXT: v_trunc_f32_e32 v3, v1
+; GFX6-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX6-NEXT: s_brev_b32 s6, -2
+; GFX6-NEXT: v_bfi_b32 v4, s6, v2, v0
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 8
+; GFX6-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_pow_f32_daz:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_log_f32_e64 v2, |v0|
+; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v4, v3
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX8-NEXT: v_exp_f32_e32 v2, v2
+; GFX8-NEXT: v_trunc_f32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX8-NEXT: s_brev_b32 s6, -2
+; GFX8-NEXT: v_bfi_b32 v4, s6, v2, v0
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 8
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_pow_f32_daz:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_log_f32_e64 v2, |v0|
+; GFX9-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX9-NEXT: v_trunc_f32_e32 v4, v3
+; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_exp_f32_e32 v2, v2
+; GFX9-NEXT: v_trunc_f32_e32 v3, v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX9-NEXT: s_brev_b32 s6, -2
+; GFX9-NEXT: v_bfi_b32 v4, s6, v2, v0
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 8
+; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX90A-LABEL: v_pow_f32_daz:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_log_f32_e64 v2, |v0|
+; GFX90A-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX90A-NEXT: v_trunc_f32_e32 v4, v3
+; GFX90A-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
+; GFX90A-NEXT: v_mul_legacy_f32 v2, v1, v2
+; GFX90A-NEXT: v_exp_f32_e32 v2, v2
+; GFX90A-NEXT: v_trunc_f32_e32 v3, v1
+; GFX90A-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
+; GFX90A-NEXT: s_brev_b32 s6, -2
+; GFX90A-NEXT: v_bfi_b32 v4, s6, v2, v0
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX90A-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 8
+; GFX90A-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX90A-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX90A-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_pow_f32_daz:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_log_f32_e64 v2, |v0|
+; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX10-NEXT: v_trunc_f32_e32 v5, v1
+; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 8
+; GFX10-NEXT: v_trunc_f32_e32 v4, v3
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v5, v1
+; GFX10-NEXT: v_cmp_neq_f32_e64 s5, v5, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v4, v3
+; GFX10-NEXT: v_exp_f32_e32 v2, v2
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT: s_and_b32 s4, s6, s5
+; GFX10-NEXT: v_bfi_b32 v3, 0x7fffffff, v2, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_pow_f32_daz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_log_f32_e64 v2, |v0|
+; GFX11-NEXT: v_trunc_f32_e32 v5, v1
+; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 8
+; GFX11-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v5, v1
+; GFX11-NEXT: v_cmp_neq_f32_e64 s1, v5, v1
+; GFX11-NEXT: v_trunc_f32_e32 v4, v3
+; GFX11-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
+; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v4, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: s_and_b32 s0, s2, s1
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_bfi_b32 v3, 0x7fffffff, v2, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %pow = call float @llvm.pow.f32(float %x, float %y)
+ ret float %pow
+}
+
declare half @llvm.pow.f16(half, half)
declare float @llvm.pow.f32(float, float)
declare double @llvm.pow.f64(double, double)
@@ -4889,3 +5070,5 @@ declare float @llvm.fabs.f32(float)
declare <2 x half> @llvm.pow.v2f16(<2 x half>, <2 x half>)
declare <2 x float> @llvm.pow.v2f32(<2 x float>, <2 x float>)
+
+attributes #0 = { denormal_fpenv(float:preservesign|preservesign) }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
index 865399ef7e15a..fd5ab9296cb7c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
@@ -18,6 +18,7 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX7-NEXT: v_log_f32_e32 v3, v3
; GFX7-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX7-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX7-NEXT: v_mul_f32_e32 v4, 0.5, v1
; GFX7-NEXT: v_sub_f32_e32 v2, v3, v2
; GFX7-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
; GFX7-NEXT: v_mov_b32_e32 v3, 0x42800000
@@ -27,18 +28,17 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX7-NEXT: v_exp_f32_e32 v2, v2
; GFX7-NEXT: v_not_b32_e32 v3, 63
; GFX7-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX7-NEXT: v_trunc_f32_e32 v5, v4
; GFX7-NEXT: v_ldexp_f32_e32 v2, v2, v3
-; GFX7-NEXT: v_mul_f32_e32 v3, 0.5, v1
-; GFX7-NEXT: v_trunc_f32_e32 v4, v3
-; GFX7-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX7-NEXT: v_trunc_f32_e32 v3, v1
-; GFX7-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
-; GFX7-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
; GFX7-NEXT: s_brev_b32 s4, -2
-; GFX7-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX7-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX7-NEXT: v_trunc_f32_e32 v4, v1
+; GFX7-NEXT: v_bfi_b32 v3, s4, v2, v0
+; GFX7-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, v1
+; GFX7-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX7-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX7-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX7-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
; GFX7-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX7-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -48,81 +48,84 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX8-LABEL: v_powi_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX8-NEXT: s_mov_b32 s4, 0x800000
; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
-; GFX8-NEXT: v_ldexp_f32 v3, |v0|, v3
-; GFX8-NEXT: v_log_f32_e32 v3, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
-; GFX8-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000
-; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX8-NEXT: v_exp_f32_e32 v2, v2
-; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 32, vcc
+; GFX8-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX8-NEXT: v_log_f32_e32 v4, v4
; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v1
-; GFX8-NEXT: v_trunc_f32_e32 v4, v3
-; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX8-NEXT: v_trunc_f32_e32 v3, v1
-; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
-; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
+; GFX8-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_sub_f32_e32 v3, v4, v3
+; GFX8-NEXT: v_mul_legacy_f32_e32 v3, v1, v3
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000
+; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX8-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX8-NEXT: v_exp_f32_e32 v3, v3
+; GFX8-NEXT: v_not_b32_e32 v4, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX8-NEXT: s_brev_b32 s4, -2
-; GFX8-NEXT: v_bfi_b32 v2, s4, v2, v4
-; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX8-NEXT: v_ldexp_f32 v3, v3, v4
+; GFX8-NEXT: v_mul_f32_e32 v4, 0.5, v1
+; GFX8-NEXT: v_trunc_f32_e32 v5, v4
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX8-NEXT: v_trunc_f32_e32 v4, v1
+; GFX8-NEXT: v_bfi_b32 v0, s4, v3, v0
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, v1
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_powi_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v4, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v4, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v0|, v3
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v2, 24
+; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e64 s1, v6, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 32, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v6, v1
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v4, v3
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v1, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_mul_f32 v4, 0.5, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v3
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s0, v0, 24
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v4, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s1
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
@@ -131,43 +134,43 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX11-FAKE16-LABEL: v_powi_f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v4, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v4, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v0|, v3
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v1
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s2, v2, 24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 32, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v6, v1
+; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s1, v6, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v2|, v4
+; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v4, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v1, v3
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0xffffffc0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_mul_f32 v4, 0.5, v1
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v3
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v4
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v4
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v0, 24
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v4, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%l.cast = bitcast i16 %l to half
@@ -197,19 +200,19 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX7-NEXT: v_add_f32_e32 v2, v2, v3
; GFX7-NEXT: v_exp_f32_e32 v2, v2
; GFX7-NEXT: v_not_b32_e32 v3, 63
+; GFX7-NEXT: v_mul_f32_e32 v4, 0.5, v1
; GFX7-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX7-NEXT: v_trunc_f32_e32 v5, v4
; GFX7-NEXT: v_ldexp_f32_e32 v2, v2, v3
-; GFX7-NEXT: v_mul_f32_e32 v3, 0.5, v1
-; GFX7-NEXT: v_trunc_f32_e32 v4, v3
-; GFX7-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX7-NEXT: v_trunc_f32_e32 v3, v1
-; GFX7-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
-; GFX7-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
; GFX7-NEXT: s_brev_b32 s4, -2
-; GFX7-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX7-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX7-NEXT: v_trunc_f32_e32 v4, v1
+; GFX7-NEXT: v_bfi_b32 v3, s4, v2, v0
+; GFX7-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, v1
+; GFX7-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX7-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX7-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX7-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
; GFX7-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX7-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -235,19 +238,19 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
; GFX8-NEXT: v_exp_f32_e32 v2, v2
; GFX8-NEXT: v_not_b32_e32 v3, 63
+; GFX8-NEXT: v_mul_f32_e32 v4, 0.5, v1
; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX8-NEXT: v_trunc_f32_e32 v5, v4
; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
-; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v1
-; GFX8-NEXT: v_trunc_f32_e32 v4, v3
-; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v4, v3
-; GFX8-NEXT: v_trunc_f32_e32 v3, v1
-; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v3, v1
-; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
; GFX8-NEXT: s_brev_b32 s4, -2
-; GFX8-NEXT: v_bfi_b32 v2, s4, v2, v4
+; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v5, v4
+; GFX8-NEXT: v_trunc_f32_e32 v4, v1
+; GFX8-NEXT: v_bfi_b32 v3, s4, v2, v0
+; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], v4, v1
+; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24
-; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v3, v1
+; GFX8-NEXT: v_cmp_neq_f32_e32 vcc, v4, v1
; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000
; GFX8-NEXT: s_and_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -258,14 +261,16 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 32, s0
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
-; GFX11-NEXT: v_trunc_f32_e32 v4, v1
+; GFX11-NEXT: v_trunc_f32_e32 v6, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_ldexp_f32 v3, |v0|, v3
-; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v4, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v6, v1
+; GFX11-NEXT: v_cmp_neq_f32_e64 s1, v6, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v3, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v2, v3, v2
@@ -273,23 +278,20 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v2, v2
; GFX11-NEXT: v_trunc_f32_e32 v5, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v5, v3
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v4
; GFX11-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24
-; GFX11-NEXT: v_cndmask_b32_e32 v3, 1.0, v0, vcc_lo
-; GFX11-NEXT: v_cmp_neq_f32_e32 vcc_lo, v4, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v3
-; GFX11-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s0, s2, s1
+; GFX11-NEXT: v_bfi_b32 v3, 0x7fffffff, v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 %r)
>From bbb5b960c1de20c390fcdce0d14a89d367c9fa24 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Wed, 9 Sep 2026 14:45:48 +0200
Subject: [PATCH 3/3] fix comment
---
llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll
index 01c99e7731ef3..be15af54b0429 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
; With real true16 instructions s16 values live in 16-bit register classes,
; and folding an fpext into a mix instruction's 32-bit source operand leaves
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