[llvm] [AArch64][GlobalISel] Copy flags in reduction fewerElements (PR #221608)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 9 03:12:33 PDT 2026
https://github.com/davemgreen updated https://github.com/llvm/llvm-project/pull/221608
>From 1867cb17ccfd53acca943b8b0b4cb1b506e096ff Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Sun, 6 Sep 2026 22:40:36 +0100
Subject: [PATCH] [AArch64][GlobalISel] Copy flags in reduction fewerElements
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 30 ++++++++++++-------
.../GlobalISel/legalize-reduce-fmul.mir | 6 ++--
llvm/test/CodeGen/AArch64/double_reduct.ll | 6 ++--
llvm/test/CodeGen/AArch64/vecreduce-fmul.ll | 16 +++++-----
4 files changed, 34 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index b73d363f22665..e4bbc62b83887 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -6169,7 +6169,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorReductions(
PartialResults.emplace_back(
MIRBuilder
.buildInstr(ScalarOpc, {NarrowTy},
- {SplitSrcs[Idx], SplitSrcs[Idx + 1]})
+ {SplitSrcs[Idx], SplitSrcs[Idx + 1]},
+ MI.getFlags())
.getReg(0));
}
SplitSrcs = PartialResults;
@@ -6184,7 +6185,9 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorReductions(
// If we can't generate a tree, then just do sequential operations.
Register Acc = SplitSrcs[0];
for (unsigned Idx = 1; Idx < NumParts; ++Idx)
- Acc = MIRBuilder.buildInstr(ScalarOpc, {NarrowTy}, {Acc, SplitSrcs[Idx]})
+ Acc = MIRBuilder
+ .buildInstr(ScalarOpc, {NarrowTy}, {Acc, SplitSrcs[Idx]},
+ MI.getFlags())
.getReg(0);
MIRBuilder.buildCopy(DstReg, Acc);
MI.eraseFromParent();
@@ -6192,9 +6195,11 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorReductions(
}
SmallVector<Register> PartialReductions;
for (unsigned Part = 0; Part < NumParts; ++Part) {
- PartialReductions.push_back(
- MIRBuilder.buildInstr(RdxMI.getOpcode(), {DstTy}, {SplitSrcs[Part]})
- .getReg(0));
+ PartialReductions.push_back(MIRBuilder
+ .buildInstr(RdxMI.getOpcode(), {DstTy},
+ {SplitSrcs[Part]},
+ MI.getFlags())
+ .getReg(0));
}
// If the types involved are powers of 2, we can generate intermediate vector
@@ -6207,11 +6212,12 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorReductions(
Register Acc = PartialReductions[0];
for (unsigned Part = 1; Part < NumParts; ++Part) {
if (Part == NumParts - 1) {
- MIRBuilder.buildInstr(ScalarOpc, {DstReg},
- {Acc, PartialReductions[Part]});
+ MIRBuilder.buildInstr(ScalarOpc, {DstReg}, {Acc, PartialReductions[Part]},
+ MI.getFlags());
} else {
Acc = MIRBuilder
- .buildInstr(ScalarOpc, {DstTy}, {Acc, PartialReductions[Part]})
+ .buildInstr(ScalarOpc, {DstTy}, {Acc, PartialReductions[Part]},
+ MI.getFlags())
.getReg(0);
}
}
@@ -6241,7 +6247,9 @@ LegalizerHelper::fewerElementsVectorSeqReductions(MachineInstr &MI,
extractParts(SrcReg, NarrowTy, NumParts, SplitSrcs, MIRBuilder, MRI);
Register Acc = ScalarReg;
for (unsigned i = 0; i < NumParts; i++)
- Acc = MIRBuilder.buildInstr(ScalarOpc, {NarrowTy}, {Acc, SplitSrcs[i]})
+ Acc = MIRBuilder
+ .buildInstr(ScalarOpc, {NarrowTy}, {Acc, SplitSrcs[i]},
+ MI.getFlags())
.getReg(0);
MIRBuilder.buildCopy(DstReg, Acc);
@@ -6267,7 +6275,9 @@ LegalizerHelper::tryNarrowPow2Reduction(MachineInstr &MI, Register SrcReg,
Register RHS = SplitSrcs[Idx + 1];
// Create the intermediate vector op.
Register Res =
- MIRBuilder.buildInstr(ScalarOpc, {NarrowTy}, {LHS, RHS}).getReg(0);
+ MIRBuilder
+ .buildInstr(ScalarOpc, {NarrowTy}, {LHS, RHS}, MI.getFlags())
+ .getReg(0);
PartialRdxs.push_back(Res);
}
SplitSrcs = std::move(PartialRdxs);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-fmul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-fmul.mir
index e4ce56f07d25e..9752d55a3361d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-fmul.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-fmul.mir
@@ -13,11 +13,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f32>) = COPY $q1
- ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(<4 x f32>) = G_FMUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(<4 x f32>) = nnan ninf nsz arcp contract afn reassoc G_FMUL [[COPY]], [[COPY1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x f32>), [[UV1:%[0-9]+]]:_(<2 x f32>) = G_UNMERGE_VALUES [[FMUL]](<4 x f32>)
- ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(<2 x f32>) = G_FMUL [[UV]], [[UV1]]
+ ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(<2 x f32>) = nnan ninf nsz arcp contract afn reassoc G_FMUL [[UV]], [[UV1]]
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[FMUL1]](<2 x f32>)
- ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[UV3]]
+ ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FMUL [[UV2]], [[UV3]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY [[FMUL2]](f32)
; CHECK-NEXT: $s0 = COPY [[COPY2]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
diff --git a/llvm/test/CodeGen/AArch64/double_reduct.ll b/llvm/test/CodeGen/AArch64/double_reduct.ll
index 6b681b20733b5..23cde1249b266 100644
--- a/llvm/test/CodeGen/AArch64/double_reduct.ll
+++ b/llvm/test/CodeGen/AArch64/double_reduct.ll
@@ -918,11 +918,11 @@ define float @nested_mul_f32(<4 x float> %a, <4 x float> %b, float %c, float %d)
; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v4.2s
; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v5.2s
; CHECK-GI-NEXT: mov s4, v0.s[1]
-; CHECK-GI-NEXT: mov s5, v1.s[1]
-; CHECK-GI-NEXT: fmul s0, s0, s4
-; CHECK-GI-NEXT: fmul s1, s1, s5
; CHECK-GI-NEXT: fmul s0, s0, s2
+; CHECK-GI-NEXT: mov s2, v1.s[1]
; CHECK-GI-NEXT: fmul s1, s1, s3
+; CHECK-GI-NEXT: fmul s0, s0, s4
+; CHECK-GI-NEXT: fmul s1, s1, s2
; CHECK-GI-NEXT: fmul s0, s0, s1
; CHECK-GI-NEXT: ret
%r1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a)
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fmul.ll b/llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
index 578568a6eeff1..3fc60e8032b68 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
@@ -260,10 +260,10 @@ define float @mul_S_init_42(<4 x float> %bin.rdx) {
; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: mov w8, #1109917696 // =0x42280000
; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: mov s1, v0.s[1]
-; CHECK-GI-NEXT: fmul s0, s0, s1
; CHECK-GI-NEXT: fmov s1, w8
+; CHECK-GI-NEXT: mov s2, v0.s[1]
; CHECK-GI-NEXT: fmul s0, s0, s1
+; CHECK-GI-NEXT: fmul s0, s0, s2
; CHECK-GI-NEXT: ret
%r = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 42.0, <4 x float> %bin.rdx)
ret float %r
@@ -426,14 +426,14 @@ define float @fmul_reduct_reassoc_v4f32_init(float %i, <4 x float> %a, <4 x floa
; CHECK-GI-LABEL: fmul_reduct_reassoc_v4f32_init:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: mov d4, v2.d[1]
; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v3.2s
-; CHECK-GI-NEXT: mov d3, v2.d[1]
-; CHECK-GI-NEXT: mov s4, v1.s[1]
-; CHECK-GI-NEXT: fmul v2.2s, v2.2s, v3.2s
-; CHECK-GI-NEXT: fmul s1, s1, s4
-; CHECK-GI-NEXT: mov s3, v2.s[1]
+; CHECK-GI-NEXT: fmul v2.2s, v2.2s, v4.2s
+; CHECK-GI-NEXT: mov s3, v1.s[1]
; CHECK-GI-NEXT: fmul s0, s0, s1
-; CHECK-GI-NEXT: fmul s1, s2, s3
+; CHECK-GI-NEXT: mov s1, v2.s[1]
+; CHECK-GI-NEXT: fmul s0, s0, s3
+; CHECK-GI-NEXT: fmul s1, s2, s1
; CHECK-GI-NEXT: fmul s0, s0, s1
; CHECK-GI-NEXT: ret
%r1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float %i, <4 x float> %a)
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