[llvm] 4e76287 - [GlobalISel] Restrict value offset tracking to aggregates (NFC) (#221287)
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Wed Sep 9 03:09:01 PDT 2026
Author: Cullen Rhodes
Date: 2026-09-09T11:08:56+01:00
New Revision: 4e7628708d6d09c4051fd1fa54cb6b517db326fe
URL: https://github.com/llvm/llvm-project/commit/4e7628708d6d09c4051fd1fa54cb6b517db326fe
DIFF: https://github.com/llvm/llvm-project/commit/4e7628708d6d09c4051fd1fa54cb6b517db326fe.diff
LOG: [GlobalISel] Restrict value offset tracking to aggregates (NFC) (#221287)
The single-vreg fast path added in d30d5fe8dd5d3 still populated an
offset list, even though offsets are only necessary for aggregate
values.
This wasn't the only place doing so. Avoid creating or updating offset
lists for non-aggregate values and add an assertion to enforce this
invariant.
Small -0.04% geomean improvement on CTMark aarch64-O0-g.
https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=2aeb9d236a2cacf8ab93722b8b629243384bae68&stat=instructions:u
Assisted-by: codex
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index d343633cb2105..a1fe689685258 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -140,6 +140,8 @@ class IRTranslatorImpl {
}
OffsetListT *getOffsets(const Value &V) {
+ assert(V.getType()->isAggregateType() &&
+ "Offsets are for aggregate values");
auto [It, Inserted] = TypeToOffsets.try_emplace(V.getType());
if (!Inserted)
return It->second;
@@ -761,14 +763,11 @@ class IRTranslatorImpl {
auto Reg = MRI->createGenericVirtualRegister(LLT::token());
Regs.push_back(Reg);
- auto &Offsets = *VMap.getOffsets(Token);
- if (Offsets.empty())
- Offsets.push_back(0);
return Reg;
}
- /// Allocate some vregs and offsets in the VMap. Then populate just the
- /// offsets while leaving the vregs empty.
+ /// Allocate empty vregs for \p Val. For aggregate values, also populate
+ /// their offsets.
ValueToVRegInfo::VRegListT &allocateVRegs(const Value &Val);
/// Get the frame index that represents \p Val.
@@ -937,6 +936,11 @@ IRTranslatorImpl::allocateVRegs(const Value &Val) {
if (VRegsIt != VMap.vregs_end())
return *VRegsIt->second;
auto *Regs = VMap.getVRegs(Val);
+ if (!Val.getType()->isAggregateType()) {
+ Regs->push_back(0);
+ return *Regs;
+ }
+
auto *Offsets = VMap.getOffsets(Val);
SmallVector<LLT, 4> SplitTys;
computeValueLLTs(*DL, *Val.getType(), SplitTys,
@@ -956,7 +960,6 @@ ArrayRef<Register> IRTranslatorImpl::getOrCreateVRegs(const Value &Val) {
// Create entry for this type.
auto *VRegs = VMap.getVRegs(Val);
- auto *Offsets = VMap.getOffsets(Val);
if (!Val.getType()->isTokenTy())
assert(Val.getType()->isSized() &&
@@ -965,8 +968,6 @@ ArrayRef<Register> IRTranslatorImpl::getOrCreateVRegs(const Value &Val) {
// Fast-path values that lower to a single vreg.
if (!Val.getType()->isAggregateType()) {
LLT Ty = getLLTForType(*Val.getType(), *DL);
- if (Offsets->empty())
- Offsets->push_back(0);
VRegs->push_back(MRI->createGenericVirtualRegister(Ty));
if (isa<Constant>(Val)) {
bool Success = translate(cast<Constant>(Val), VRegs->front());
@@ -982,6 +983,7 @@ ArrayRef<Register> IRTranslatorImpl::getOrCreateVRegs(const Value &Val) {
}
SmallVector<LLT, 4> SplitTys;
+ auto *Offsets = VMap.getOffsets(Val);
computeValueLLTs(*DL, *Val.getType(), SplitTys,
Offsets->empty() ? Offsets : nullptr);
@@ -2317,7 +2319,6 @@ bool IRTranslatorImpl::translateCopy(const User &U, Register Src,
auto &Regs = *VMap.getVRegs(U);
if (Regs.empty()) {
Regs.push_back(Src);
- VMap.getOffsets(U)->push_back(0);
} else {
// If we already assigned a vreg for this instruction, we can't change that.
// Emit a copy to satisfy the users we already emitted.
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