[llvm] d6a334d - [AMDGPU][AsmParser]: Use dummy operand for parsing buffer LDS isAsync… (#219459)
via llvm-commits
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Wed Sep 9 02:26:22 PDT 2026
Author: Petr Kurapov
Date: 2026-09-09T11:26:16+02:00
New Revision: d6a334df0889026e0d91d3fc5adf452e0bbf0682
URL: https://github.com/llvm/llvm-project/commit/d6a334df0889026e0d91d3fc5adf452e0bbf0682
DIFF: https://github.com/llvm/llvm-project/commit/d6a334df0889026e0d91d3fc5adf452e0bbf0682.diff
LOG: [AMDGPU][AsmParser]: Use dummy operand for parsing buffer LDS isAsync… (#219459)
… operand.
After the introduction of .async for LDS buffer ops variants, there a
similar mca crash addressed in
https://github.com/llvm/llvm-project/pull/165305. This parses a dummy
operand as a placeholder.
Added:
llvm/test/MC/AMDGPU/buffer-op-lds-operand.s
llvm/test/tools/llvm-mca/AMDGPU/buffer-op-lds-operand.s
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 4db11eace7313..5d62402f12c6e 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -9420,6 +9420,10 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
// Parse a dummy operand as a placeholder for the SWZ operand. This enforces
// agreement between MCInstrDesc.getNumOperands and MCInst.getNumOperands.
Inst.addOperand(MCOperand::createImm(0));
+ // The LDS variants carry a trailing IsAsync operand. Parse a dummy the same
+ // way as the SWZ operand.
+ if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::IsAsync))
+ Inst.addOperand(MCOperand::createImm(0));
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AMDGPU/buffer-op-lds-operand.s b/llvm/test/MC/AMDGPU/buffer-op-lds-operand.s
new file mode 100644
index 0000000000000..9f8f38cad53c6
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/buffer-op-lds-operand.s
@@ -0,0 +1,29 @@
+// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx950 --show-inst < %s | FileCheck %s
+
+// CHECK: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx950"
+buffer_load_dword off, s[8:11], 0 lds
+// CHECK: buffer_load_dword off, s[8:11], 0 lds ; <MCInst #{{[0-9]+}} BUFFER_LOAD_DWORD_LDS_OFFSET
+// CHECK-NEXT: ; <MCOperand Reg:SGPR8_SGPR9_SGPR10_SGPR11>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>>
+buffer_load_dword v18, s[8:11], 0 offen lds
+// CHECK: buffer_load_dword v18, s[8:11], 0 offen lds ; <MCInst #{{[0-9]+}} BUFFER_LOAD_DWORD_LDS_OFFEN
+// CHECK-NEXT: ; <MCOperand Reg:VGPR18>
+// CHECK-NEXT: ; <MCOperand Reg:SGPR8_SGPR9_SGPR10_SGPR11>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>>
+buffer_load_dword v18, s[8:11], 0 idxen lds
+// CHECK: buffer_load_dword v18, s[8:11], 0 idxen lds ; <MCInst #{{[0-9]+}} BUFFER_LOAD_DWORD_LDS_IDXEN
+// CHECK-NEXT: ; <MCOperand Reg:VGPR18>
+// CHECK-NEXT: ; <MCOperand Reg:SGPR8_SGPR9_SGPR10_SGPR11>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>>
diff --git a/llvm/test/tools/llvm-mca/AMDGPU/buffer-op-lds-operand.s b/llvm/test/tools/llvm-mca/AMDGPU/buffer-op-lds-operand.s
new file mode 100644
index 0000000000000..819b668df5132
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AMDGPU/buffer-op-lds-operand.s
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck %s
+
+buffer_load_dword off, s[8:11], 0 lds
+buffer_load_dword v18, s[8:11], 0 offen lds
+buffer_load_dword v18, s[8:11], 0 idxen lds
+buffer_load_dwordx4 v18, s[8:11], 0 offen sc0 nt lds
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 480
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 1
+# CHECK-NEXT: uOps Per Cycle: 0.83
+# CHECK-NEXT: IPC: 0.83
+# CHECK-NEXT: Block RThroughput: 4.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 80 1.00 * * U buffer_load_dword off, s[8:11], 0 lds
+# CHECK-NEXT: 1 80 1.00 * * U buffer_load_dword v18, s[8:11], 0 offen lds
+# CHECK-NEXT: 1 80 1.00 * * U buffer_load_dword v18, s[8:11], 0 idxen lds
+# CHECK-NEXT: 1 80 1.00 * * U buffer_load_dwordx4 v18, s[8:11], 0 offen sc0 nt lds
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - HWBranch
+# CHECK-NEXT: [1] - HWExport
+# CHECK-NEXT: [2] - HWLGKM
+# CHECK-NEXT: [3] - HWSALU
+# CHECK-NEXT: [4] - HWVALU
+# CHECK-NEXT: [5] - HWVMEM
+# CHECK-NEXT: [6] - HWXDL
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6]
+# CHECK-NEXT: - - - - - 4.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - buffer_load_dword off, s[8:11], 0 lds
+# CHECK-NEXT: - - - - - 1.00 - buffer_load_dword v18, s[8:11], 0 offen lds
+# CHECK-NEXT: - - - - - 1.00 - buffer_load_dword v18, s[8:11], 0 idxen lds
+# CHECK-NEXT: - - - - - 1.00 - buffer_load_dwordx4 v18, s[8:11], 0 offen sc0 nt lds
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