[llvm] [LV] Reduce register pressure of RISC-V outer loop reduction. (PR #208621)

[Luke Lau via llvm-commits]

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@@ -3540,6 +3615,9 @@ class VPExpressionRecipe : public VPSingleDefRecipe {
     /// extended vector operands, negating the multiplication, performing a
     /// reduction.add on the result, and adding the scalar result to a chain.
     ExtNegatedMulAccReduction,
+    /// Represent an inloop operations with tail-floded select for the outer
+    /// loop reduction.
+    TailFoldedInLoopOp,
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lukel97 wrote:

Is there anything specific to vp.merge/tail folding with this recipe? Could we make it something more generic like `FoldedOp`, so that it represents any chain of recipes `a(b(c(...)))` where `a` is folded away and not costed?

https://github.com/llvm/llvm-project/pull/208621