[llvm] 7bb9b13 - [AMDGPU] Rework pseudo-scalar transcendental inline constant restriction handling (#208459)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 9 00:05:42 PDT 2026
Author: Frederik Harwath
Date: 2026-09-09T09:05:36+02:00
New Revision: 7bb9b13816ef9616425525651ea629f2138b194f
URL: https://github.com/llvm/llvm-project/commit/7bb9b13816ef9616425525651ea629f2138b194f
DIFF: https://github.com/llvm/llvm-project/commit/7bb9b13816ef9616425525651ea629f2138b194f.diff
LOG: [AMDGPU] Rework pseudo-scalar transcendental inline constant restriction handling (#208459)
The f16 pseudo-scalar transcendental instructions do not support inline
constants on gfx12. The existing handling of this restriction is
incomplete. It involves checking the
hasNoF16PseudoScalarTransInlineConstants function in the right places.
For the SIInstrInfo::isInlineConstant function, for instance, this has
led to a situation where some overloads respect the restriction and
others do not. This approach also relies on completely disabling the
folding of constant operands. The machine code emission does still use
the inline constant encoding if it encounters a suitable operand.
Introduce a new "noinline" operand type and use it for the instruction
variant that is used on gfx12. This does also enable the use of literal
constants.
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
llvm/lib/Target/AMDGPU/SIDefines.h
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
llvm/lib/Target/AMDGPU/VOP3Instructions.td
llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index cdd37237a1dcb..c341f844c2d90 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1,3 +1,4 @@
+
//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
@@ -1270,8 +1271,7 @@ defm PseudoScalarTrans : AMDGPUSubtargetFeature<"pseudo-scalar-trans",
>;
defm NoF16PseudoScalarTransInlineConstants : AMDGPUSubtargetFeature<"no-f16-pseudo-scalar-trans-inline-constants",
- "Inline constants are not supported for F16 pseudo scalar transcendentals",
- /*GenPredicate=*/0
+ "Inline constants are not supported for F16 pseudo scalar transcendentals"
>;
defm RestrictedSOffset : AMDGPUSubtargetFeature<"restricted-soffset",
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index f0719a4dabf6b..4db11eace7313 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -483,6 +483,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isSSrc_f16() const { return isSCSrcB16() || isLiteralImm(MVT::f16); }
+ bool isSSrc_NoInline_f16() const { return isSSrc_f16(); }
+
bool isSSrcV2F16() const {
llvm_unreachable("cannot happen");
return isSSrc_f16();
@@ -2055,6 +2057,7 @@ static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {
case AMDGPU::OPERAND_KIMM64:
return &APFloat::IEEEdouble();
case AMDGPU::OPERAND_REG_IMM_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
case AMDGPU::OPERAND_REG_IMM_V2FP16:
@@ -2450,6 +2453,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val,
case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
case AMDGPU::OPERAND_REG_IMM_INT16:
case AMDGPU::OPERAND_REG_IMM_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
@@ -2557,6 +2561,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val,
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
case AMDGPU::OPERAND_REG_IMM_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_IMM_BF16:
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
@@ -3810,7 +3815,8 @@ bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,
OperandType == AMDGPU::OPERAND_REG_INLINE_C_BF16)
return AMDGPU::isInlinableLiteralBF16(Val, hasInv2PiInlineImm());
- if (OperandType == AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16)
+ if (OperandType == AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16 ||
+ OperandType == AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16)
return false;
llvm_unreachable("invalid operand type");
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index ab62086fdcdd3..098d469bd8505 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -632,6 +632,11 @@ bool AMDGPUDisassembler::decodeImmOperands(MCInst &MI,
if (AMDGPU::EncValues::INLINE_FLOATING_C_MIN <= Imm &&
Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX) {
switch (OpDesc.OperandType) {
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
+ // Inline constant encodings are not allowed for NOINLINE operand types.
+ // Keep the raw encoding value.
+ continue;
case AMDGPU::OPERAND_REG_IMM_BF16:
case AMDGPU::OPERAND_REG_IMM_V2BF16:
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
@@ -1778,6 +1783,7 @@ AMDGPUDisassembler::decodeLiteralConstant(const MCInstrDesc &Desc,
case AMDGPU::OPERAND_REG_IMM_V2FP16_SPLAT:
UseLit = AMDGPU::isPKFMACF16InlineConstant(Val, isGFX11Plus());
break;
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
break;
case AMDGPU::OPERAND_REG_IMM_INT16:
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 782c65ef6e276..12880e6692918 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -893,6 +893,7 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
break;
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
case AMDGPU::OPERAND_REG_IMM_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
printImmediateF16(Op.getImm(), STI, O);
break;
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index e7dbdad46f8dc..18c0919471d6d 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -340,6 +340,9 @@ std::optional<uint64_t> AMDGPUMCCodeEmitter::getLitEncoding(
// which does not have f16 support?
return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
+ return 255;
+
case AMDGPU::OPERAND_REG_IMM_BF16:
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
// We don't actually need to check Inv2Pi here because BF16 instructions can
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 9f2446072bf0b..fa6d809e2de97 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -435,6 +435,7 @@ enum OperandType : unsigned {
OPERAND_REG_IMM_FP64,
OPERAND_REG_IMM_BF16,
OPERAND_REG_IMM_FP16,
+ OPERAND_REG_IMM_NOINLINE_FP16,
OPERAND_REG_IMM_V2BF16,
OPERAND_REG_IMM_V2FP16,
OPERAND_REG_IMM_V2FP16_SPLAT,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index b852be30568bf..a456b2193403c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4982,6 +4982,7 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
case AMDGPU::OPERAND_KIMM32:
case AMDGPU::OPERAND_KIMM16:
case AMDGPU::OPERAND_KIMM64:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
return false;
case AMDGPU::OPERAND_INLINE_C_AV64_PSEUDO:
return isLegalAV64PseudoImm(Imm);
@@ -5442,10 +5443,9 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
case AMDGPU::OPERAND_REG_IMM_V2BF16:
case AMDGPU::OPERAND_REG_IMM_V2FP64:
case AMDGPU::OPERAND_REG_IMM_V2INT64:
- break;
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
break;
- break;
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
@@ -6786,9 +6786,6 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
if (Op.isFI())
return false;
}
- } else if (IsInlineConst && ST.hasNoF16PseudoScalarTransInlineConstants() &&
- isF16PseudoScalarTrans(MI.getOpcode())) {
- return false;
}
if (MO->isReg()) {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index aebfc1436e659..ea91f128f9392 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1191,14 +1191,6 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
Opc == AMDGPU::GLOBAL_WBINV;
}
- static bool isF16PseudoScalarTrans(unsigned Opcode) {
- return Opcode == AMDGPU::V_S_EXP_F16_e64 ||
- Opcode == AMDGPU::V_S_LOG_F16_e64 ||
- Opcode == AMDGPU::V_S_RCP_F16_e64 ||
- Opcode == AMDGPU::V_S_RSQ_F16_e64 ||
- Opcode == AMDGPU::V_S_SQRT_F16_e64;
- }
-
static bool doesNotReadTiedSource(const MachineInstr &MI) {
return SIInstrFlags::isTiedSourceNotRead(MI);
}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index 722178d6cb111..88c63e2f9a7b9 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -1421,6 +1421,7 @@ class SrcRegOrImm9_t16<string operandType, RegisterClass regClass = VS_16>
def SSrc_b16 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_INT16">;
def SSrc_bf16 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_BF16">;
def SSrc_f16 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_FP16">;
+def SSrc_NoInline_f16 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_NOINLINE_FP16">;
def SSrc_b32 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_INT32">;
def SSrc_f32 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_FP32">;
def SSrc_b64 : SrcRegOrImm9 <SReg_64_Encodable, "OPERAND_REG_IMM_INT64">;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 2178bab0cd08b..b6dd07dd26514 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -2825,6 +2825,7 @@ bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
case AMDGPU::OPERAND_REG_IMM_FP32:
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_IMM_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_IMM_V2FP16:
case AMDGPU::OPERAND_REG_IMM_V2FP16_SPLAT:
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
@@ -3271,6 +3272,7 @@ int64_t encode32BitLiteral(int64_t Imm, OperandType Type, bool IsLit) {
break;
case OPERAND_REG_IMM_BF16:
case OPERAND_REG_IMM_FP16:
+ case OPERAND_REG_IMM_NOINLINE_FP16:
case OPERAND_REG_INLINE_C_BF16:
case OPERAND_REG_INLINE_C_FP16:
return Imm & 0xffff;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 664ca91e4e7d4..a073af98cb85c 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -1596,6 +1596,7 @@ inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
case AMDGPU::OPERAND_REG_IMM_INT16:
case AMDGPU::OPERAND_REG_IMM_BF16:
case AMDGPU::OPERAND_REG_IMM_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 05f47f696393b..b8ec4345ff84b 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -1982,19 +1982,34 @@ class VOP_Pseudo_Scalar<RegisterClass Dst, RegisterOperand SrcOp,
def VOP_Pseudo_Scalar_F32 : VOP_Pseudo_Scalar<SReg_32_XEXEC, SSrc_f32, f32>;
def VOP_Pseudo_Scalar_F16 : VOP_Pseudo_Scalar<SReg_32_XEXEC, SSrc_f16, f32, f16>;
+def VOP_Pseudo_Scalar_F16_NoInline : VOP_Pseudo_Scalar<SReg_32_XEXEC, SSrc_NoInline_f16, f32, f16>;
+
+// Define regular and "no inline constant" variant of a F16 pseudo
+// scalar transcendental instruction.
+multiclass VOP3PseudoScalarInst_F16<string opName> {
+ let TRANS = 1, isReMaterializable = 1, SchedRW = [WritePseudoScalarTrans] in {
+ let SubtargetPredicate = Predicate<"Subtarget->hasPseudoScalarTrans() && !Subtarget->hasNoF16PseudoScalarTransInlineConstants()"> in {
+ defm NAME : VOP3PseudoScalarInst<opName, VOP_Pseudo_Scalar_F16>;
+ }
+
+ let SubtargetPredicate = HasNoF16PseudoScalarTransInlineConstants in {
+ defm !strconcat(NAME, "_noinline") : VOP3PseudoScalarInst<opName, VOP_Pseudo_Scalar_F16_NoInline>;
+ }
+ }
+}
let SubtargetPredicate = HasPseudoScalarTrans, TRANS = 1,
isReMaterializable = 1, SchedRW = [WritePseudoScalarTrans] in {
defm V_S_EXP_F32 : VOP3PseudoScalarInst<"v_s_exp_f32", VOP_Pseudo_Scalar_F32, AMDGPUexp>;
- defm V_S_EXP_F16 : VOP3PseudoScalarInst<"v_s_exp_f16", VOP_Pseudo_Scalar_F16>;
+ defm V_S_EXP_F16 : VOP3PseudoScalarInst_F16<"v_s_exp_f16">;
defm V_S_LOG_F32 : VOP3PseudoScalarInst<"v_s_log_f32", VOP_Pseudo_Scalar_F32, AMDGPUlog>;
- defm V_S_LOG_F16 : VOP3PseudoScalarInst<"v_s_log_f16", VOP_Pseudo_Scalar_F16>;
+ defm V_S_LOG_F16 : VOP3PseudoScalarInst_F16<"v_s_log_f16">;
defm V_S_RCP_F32 : VOP3PseudoScalarInst<"v_s_rcp_f32", VOP_Pseudo_Scalar_F32, AMDGPUrcp>;
- defm V_S_RCP_F16 : VOP3PseudoScalarInst<"v_s_rcp_f16", VOP_Pseudo_Scalar_F16>;
+ defm V_S_RCP_F16 : VOP3PseudoScalarInst_F16<"v_s_rcp_f16">;
defm V_S_RSQ_F32 : VOP3PseudoScalarInst<"v_s_rsq_f32", VOP_Pseudo_Scalar_F32, AMDGPUrsq>;
- defm V_S_RSQ_F16 : VOP3PseudoScalarInst<"v_s_rsq_f16", VOP_Pseudo_Scalar_F16>;
+ defm V_S_RSQ_F16 : VOP3PseudoScalarInst_F16<"v_s_rsq_f16">;
defm V_S_SQRT_F32 : VOP3PseudoScalarInst<"v_s_sqrt_f32", VOP_Pseudo_Scalar_F32, any_amdgcn_sqrt>;
- defm V_S_SQRT_F16 : VOP3PseudoScalarInst<"v_s_sqrt_f16", VOP_Pseudo_Scalar_F16>;
+ defm V_S_SQRT_F16 : VOP3PseudoScalarInst_F16<"v_s_sqrt_f16">;
}
class PseudoScalarPatF16<SDPatternOperator node, VOP3_Pseudo inst> : GCNPat <
@@ -2139,16 +2154,24 @@ defm V_MINMAX_NUM_F32 : VOP3_Realtriple_with_name_gfx12_gfx13<0x268,0x268, "
defm V_MAXMIN_NUM_F32 : VOP3_Realtriple_with_name_gfx12_gfx13<0x269, 0x269, "V_MAXMIN_F32", "v_maxmin_num_f32">;
defm V_MINMAX_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12_gfx13<0x26a, 0x26a, "v_minmax_num_f16", "V_MINMAX_F16", "v_minmax_f16">;
defm V_MAXMIN_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12_gfx13<0x26b, 0x26b, "v_maxmin_num_f16", "V_MAXMIN_F16", "v_maxmin_f16">;
+
+// Define regular and "no inline constant" variant (for gfx12) of a
+// F16 pseudo-scalar transcendental instruction.
+multiclass VOP3Only_Real_F16_PseudoScalarTrans<bits<10> op> {
+ defm NAME : VOP3_Real_Base<GFX13Gen, op, NAME, 1>;
+ defm !strconcat(NAME, "_noinline") : VOP3_Real_Base<GFX12Gen, op, !strconcat(NAME, "_noinline"), 1>;
+}
+
defm V_S_EXP_F32 : VOP3Only_Real_Base_gfx12_gfx13<0x280>;
-defm V_S_EXP_F16 : VOP3Only_Real_Base_gfx12_gfx13<0x281>;
+defm V_S_EXP_F16 : VOP3Only_Real_F16_PseudoScalarTrans<0x281>;
defm V_S_LOG_F32 : VOP3Only_Real_Base_gfx12_gfx13<0x282>;
-defm V_S_LOG_F16 : VOP3Only_Real_Base_gfx12_gfx13<0x283>;
+defm V_S_LOG_F16 : VOP3Only_Real_F16_PseudoScalarTrans<0x283>;
defm V_S_RCP_F32 : VOP3Only_Real_Base_gfx12_gfx13<0x284>;
-defm V_S_RCP_F16 : VOP3Only_Real_Base_gfx12_gfx13<0x285>;
+defm V_S_RCP_F16 : VOP3Only_Real_F16_PseudoScalarTrans<0x285>;
defm V_S_RSQ_F32 : VOP3Only_Real_Base_gfx12_gfx13<0x286>;
-defm V_S_RSQ_F16 : VOP3Only_Real_Base_gfx12_gfx13<0x287>;
+defm V_S_RSQ_F16 : VOP3Only_Real_F16_PseudoScalarTrans<0x287>;
defm V_S_SQRT_F32 : VOP3Only_Real_Base_gfx12_gfx13<0x288>;
-defm V_S_SQRT_F16 : VOP3Only_Real_Base_gfx12_gfx13<0x289>;
+defm V_S_SQRT_F16 : VOP3Only_Real_F16_PseudoScalarTrans<0x289>;
defm V_MAD_CO_U64_U32 : VOP3be_Real_with_name_gfx12_NO_DPP_gfx13<0x2fe, 0x2f8, "V_MAD_U64_U32", "v_mad_co_u64_u32">;
defm V_MAD_CO_I64_I32 : VOP3be_Real_with_name_gfx12_NO_DPP_gfx13<0x2ff, 0x2f9, "V_MAD_I64_I32", "v_mad_co_i64_i32">;
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
index 1c03ca70af8c5..5d7a829a2a503 100644
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
@@ -1,9 +1,12 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgpu11.70-amd-amdpal -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
# RUN: llc -mtriple=amdgpu12.00-amd-amdpal -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
+# RUN: llc -mtriple=amdgpu12.50-amd-amdpal -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
-# Do not use inline constants for f16 pseudo scalar transcendentals.
-# But allow literal constants.
+
+# Do not use inline constants for f16 pseudo scalar transcendentals,
+# but the operands should nevertheless be folded. The literal
+# encoding will be used as corresponding MC tests demonstrate.
---
name: exp_f16_imm
@@ -11,8 +14,7 @@ tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: exp_f16_imm
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
- ; GCN-NEXT: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
+ ; GCN: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_EXP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
@@ -34,8 +36,7 @@ tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: log_f16_imm
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
- ; GCN-NEXT: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
+ ; GCN: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_LOG_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
@@ -57,8 +58,7 @@ tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: rcp_f16_imm
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
- ; GCN-NEXT: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
+ ; GCN: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_RCP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
@@ -80,8 +80,7 @@ tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: rsq_f16_imm
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
- ; GCN-NEXT: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
+ ; GCN: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_RSQ_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
@@ -103,8 +102,7 @@ tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: sqrt_f16_imm
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
- ; GCN-NEXT: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
+ ; GCN: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_SQRT_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
index dd480b688fc45..8f9f84a8c0d10 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
@@ -6809,10 +6809,10 @@ v_s_exp_f16 s5, null
// GFX12: v_s_exp_f16 s5, null ; encoding: [0x05,0x00,0x81,0xd6,0x7c,0x00,0x01,0x02]
v_s_exp_f16 s5, -1
-// GFX12: v_s_exp_f16 s5, -1 ; encoding: [0x05,0x00,0x81,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_exp_f16 s5, -1 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_exp_f16 s5, 0.5
-// GFX12: v_s_exp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x81,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_exp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_exp_f16 s5, src_scc
// GFX12: v_s_exp_f16 s5, src_scc ; encoding: [0x05,0x00,0x81,0xd6,0xfd,0x00,0x01,0x02]
@@ -6923,10 +6923,10 @@ v_s_log_f16 s5, null
// GFX12: v_s_log_f16 s5, null ; encoding: [0x05,0x00,0x83,0xd6,0x7c,0x00,0x01,0x02]
v_s_log_f16 s5, -1
-// GFX12: v_s_log_f16 s5, -1 ; encoding: [0x05,0x00,0x83,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_log_f16 s5, -1 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_log_f16 s5, 0.5
-// GFX12: v_s_log_f16 s5, 0.5 ; encoding: [0x05,0x00,0x83,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_log_f16 s5, 0.5 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_log_f16 s5, src_scc
// GFX12: v_s_log_f16 s5, src_scc ; encoding: [0x05,0x00,0x83,0xd6,0xfd,0x00,0x01,0x02]
@@ -7037,10 +7037,10 @@ v_s_rcp_f16 s5, null
// GFX12: v_s_rcp_f16 s5, null ; encoding: [0x05,0x00,0x85,0xd6,0x7c,0x00,0x01,0x02]
v_s_rcp_f16 s5, -1
-// GFX12: v_s_rcp_f16 s5, -1 ; encoding: [0x05,0x00,0x85,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_rcp_f16 s5, -1 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_rcp_f16 s5, 0.5
-// GFX12: v_s_rcp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x85,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_rcp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_rcp_f16 s5, src_scc
// GFX12: v_s_rcp_f16 s5, src_scc ; encoding: [0x05,0x00,0x85,0xd6,0xfd,0x00,0x01,0x02]
@@ -7151,10 +7151,10 @@ v_s_rsq_f16 s5, null
// GFX12: v_s_rsq_f16 s5, null ; encoding: [0x05,0x00,0x87,0xd6,0x7c,0x00,0x01,0x02]
v_s_rsq_f16 s5, -1
-// GFX12: v_s_rsq_f16 s5, -1 ; encoding: [0x05,0x00,0x87,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_rsq_f16 s5, -1 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_rsq_f16 s5, 0.5
-// GFX12: v_s_rsq_f16 s5, 0.5 ; encoding: [0x05,0x00,0x87,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_rsq_f16 s5, 0.5 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_rsq_f16 s5, src_scc
// GFX12: v_s_rsq_f16 s5, src_scc ; encoding: [0x05,0x00,0x87,0xd6,0xfd,0x00,0x01,0x02]
@@ -7265,10 +7265,10 @@ v_s_sqrt_f16 s5, null
// GFX12: v_s_sqrt_f16 s5, null ; encoding: [0x05,0x00,0x89,0xd6,0x7c,0x00,0x01,0x02]
v_s_sqrt_f16 s5, -1
-// GFX12: v_s_sqrt_f16 s5, -1 ; encoding: [0x05,0x00,0x89,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_sqrt_f16 s5, -1 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_sqrt_f16 s5, 0.5
-// GFX12: v_s_sqrt_f16 s5, 0.5 ; encoding: [0x05,0x00,0x89,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_sqrt_f16 s5, 0.5 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_sqrt_f16 s5, src_scc
// GFX12: v_s_sqrt_f16 s5, src_scc ; encoding: [0x05,0x00,0x89,0xd6,0xfd,0x00,0x01,0x02]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
index d0bbf607d3fe2..5e52d4fe42c8c 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
@@ -7178,10 +7178,34 @@ v_s_exp_f16 s5, null
// GFX12: v_s_exp_f16 s5, null ; encoding: [0x05,0x00,0x81,0xd6,0x7c,0x00,0x01,0x02]
v_s_exp_f16 s5, -1
-// GFX12: v_s_exp_f16 s5, -1 ; encoding: [0x05,0x00,0x81,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_exp_f16 s5, -1 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_exp_f16 s5, 0.5
-// GFX12: v_s_exp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x81,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_exp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
+
+v_s_exp_f16 s5, -0.5
+// GFX12: v_s_exp_f16 s5, -0.5 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0x00,0xb8,0x00,0x00]
+
+v_s_exp_f16 s5, 1.0
+// GFX12: v_s_exp_f16 s5, 1.0 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0x00,0x3c,0x00,0x00]
+
+v_s_exp_f16 s5, -1.0
+// GFX12: v_s_exp_f16 s5, -1.0 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0x00,0xbc,0x00,0x00]
+
+v_s_exp_f16 s5, 2.0
+// GFX12: v_s_exp_f16 s5, 2.0 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0x00,0x40,0x00,0x00]
+
+v_s_exp_f16 s5, -2.0
+// GFX12: v_s_exp_f16 s5, -2.0 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0x00,0xc0,0x00,0x00]
+
+v_s_exp_f16 s5, 4.0
+// GFX12: v_s_exp_f16 s5, 4.0 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0x00,0x44,0x00,0x00]
+
+v_s_exp_f16 s5, -4.0
+// GFX12: v_s_exp_f16 s5, -4.0 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0x00,0xc4,0x00,0x00]
+
+v_s_exp_f16 s5, 0.15915494
+// GFX12: v_s_exp_f16 s5, 0.15915494 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0x18,0x31,0x00,0x00]
v_s_exp_f16 s5, src_scc
// GFX12: v_s_exp_f16 s5, src_scc ; encoding: [0x05,0x00,0x81,0xd6,0xfd,0x00,0x01,0x02]
@@ -7292,10 +7316,34 @@ v_s_log_f16 s5, null
// GFX12: v_s_log_f16 s5, null ; encoding: [0x05,0x00,0x83,0xd6,0x7c,0x00,0x01,0x02]
v_s_log_f16 s5, -1
-// GFX12: v_s_log_f16 s5, -1 ; encoding: [0x05,0x00,0x83,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_log_f16 s5, -1 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_log_f16 s5, 0.5
-// GFX12: v_s_log_f16 s5, 0.5 ; encoding: [0x05,0x00,0x83,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_log_f16 s5, 0.5 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
+
+v_s_log_f16 s5, -0.5
+// GFX12: v_s_log_f16 s5, -0.5 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0x00,0xb8,0x00,0x00]
+
+v_s_log_f16 s5, 1.0
+// GFX12: v_s_log_f16 s5, 1.0 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0x00,0x3c,0x00,0x00]
+
+v_s_log_f16 s5, -1.0
+// GFX12: v_s_log_f16 s5, -1.0 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0x00,0xbc,0x00,0x00]
+
+v_s_log_f16 s5, 2.0
+// GFX12: v_s_log_f16 s5, 2.0 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0x00,0x40,0x00,0x00]
+
+v_s_log_f16 s5, -2.0
+// GFX12: v_s_log_f16 s5, -2.0 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0x00,0xc0,0x00,0x00]
+
+v_s_log_f16 s5, 4.0
+// GFX12: v_s_log_f16 s5, 4.0 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0x00,0x44,0x00,0x00]
+
+v_s_log_f16 s5, -4.0
+// GFX12: v_s_log_f16 s5, -4.0 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0x00,0xc4,0x00,0x00]
+
+v_s_log_f16 s5, 0.15915494
+// GFX12: v_s_log_f16 s5, 0.15915494 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0x18,0x31,0x00,0x00]
v_s_log_f16 s5, src_scc
// GFX12: v_s_log_f16 s5, src_scc ; encoding: [0x05,0x00,0x83,0xd6,0xfd,0x00,0x01,0x02]
@@ -7406,10 +7454,34 @@ v_s_rcp_f16 s5, null
// GFX12: v_s_rcp_f16 s5, null ; encoding: [0x05,0x00,0x85,0xd6,0x7c,0x00,0x01,0x02]
v_s_rcp_f16 s5, -1
-// GFX12: v_s_rcp_f16 s5, -1 ; encoding: [0x05,0x00,0x85,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_rcp_f16 s5, -1 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_rcp_f16 s5, 0.5
-// GFX12: v_s_rcp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x85,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_rcp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
+
+v_s_rcp_f16 s5, -0.5
+// GFX12: v_s_rcp_f16 s5, -0.5 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0x00,0xb8,0x00,0x00]
+
+v_s_rcp_f16 s5, 1.0
+// GFX12: v_s_rcp_f16 s5, 1.0 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0x00,0x3c,0x00,0x00]
+
+v_s_rcp_f16 s5, -1.0
+// GFX12: v_s_rcp_f16 s5, -1.0 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0x00,0xbc,0x00,0x00]
+
+v_s_rcp_f16 s5, 2.0
+// GFX12: v_s_rcp_f16 s5, 2.0 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0x00,0x40,0x00,0x00]
+
+v_s_rcp_f16 s5, -2.0
+// GFX12: v_s_rcp_f16 s5, -2.0 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0x00,0xc0,0x00,0x00]
+
+v_s_rcp_f16 s5, 4.0
+// GFX12: v_s_rcp_f16 s5, 4.0 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0x00,0x44,0x00,0x00]
+
+v_s_rcp_f16 s5, -4.0
+// GFX12: v_s_rcp_f16 s5, -4.0 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0x00,0xc4,0x00,0x00]
+
+v_s_rcp_f16 s5, 0.15915494
+// GFX12: v_s_rcp_f16 s5, 0.15915494 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0x18,0x31,0x00,0x00]
v_s_rcp_f16 s5, src_scc
// GFX12: v_s_rcp_f16 s5, src_scc ; encoding: [0x05,0x00,0x85,0xd6,0xfd,0x00,0x01,0x02]
@@ -7520,10 +7592,34 @@ v_s_rsq_f16 s5, null
// GFX12: v_s_rsq_f16 s5, null ; encoding: [0x05,0x00,0x87,0xd6,0x7c,0x00,0x01,0x02]
v_s_rsq_f16 s5, -1
-// GFX12: v_s_rsq_f16 s5, -1 ; encoding: [0x05,0x00,0x87,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_rsq_f16 s5, -1 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_rsq_f16 s5, 0.5
-// GFX12: v_s_rsq_f16 s5, 0.5 ; encoding: [0x05,0x00,0x87,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_rsq_f16 s5, 0.5 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
+
+v_s_rsq_f16 s5, -0.5
+// GFX12: v_s_rsq_f16 s5, -0.5 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0x00,0xb8,0x00,0x00]
+
+v_s_rsq_f16 s5, 1.0
+// GFX12: v_s_rsq_f16 s5, 1.0 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0x00,0x3c,0x00,0x00]
+
+v_s_rsq_f16 s5, -1.0
+// GFX12: v_s_rsq_f16 s5, -1.0 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0x00,0xbc,0x00,0x00]
+
+v_s_rsq_f16 s5, 2.0
+// GFX12: v_s_rsq_f16 s5, 2.0 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0x00,0x40,0x00,0x00]
+
+v_s_rsq_f16 s5, -2.0
+// GFX12: v_s_rsq_f16 s5, -2.0 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0x00,0xc0,0x00,0x00]
+
+v_s_rsq_f16 s5, 4.0
+// GFX12: v_s_rsq_f16 s5, 4.0 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0x00,0x44,0x00,0x00]
+
+v_s_rsq_f16 s5, -4.0
+// GFX12: v_s_rsq_f16 s5, -4.0 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0x00,0xc4,0x00,0x00]
+
+v_s_rsq_f16 s5, 0.15915494
+// GFX12: v_s_rsq_f16 s5, 0.15915494 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0x18,0x31,0x00,0x00]
v_s_rsq_f16 s5, src_scc
// GFX12: v_s_rsq_f16 s5, src_scc ; encoding: [0x05,0x00,0x87,0xd6,0xfd,0x00,0x01,0x02]
@@ -7634,10 +7730,34 @@ v_s_sqrt_f16 s5, null
// GFX12: v_s_sqrt_f16 s5, null ; encoding: [0x05,0x00,0x89,0xd6,0x7c,0x00,0x01,0x02]
v_s_sqrt_f16 s5, -1
-// GFX12: v_s_sqrt_f16 s5, -1 ; encoding: [0x05,0x00,0x89,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_sqrt_f16 s5, -1 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_sqrt_f16 s5, 0.5
-// GFX12: v_s_sqrt_f16 s5, 0.5 ; encoding: [0x05,0x00,0x89,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_sqrt_f16 s5, 0.5 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
+
+v_s_sqrt_f16 s5, -0.5
+// GFX12: v_s_sqrt_f16 s5, -0.5 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0x00,0xb8,0x00,0x00]
+
+v_s_sqrt_f16 s5, 1.0
+// GFX12: v_s_sqrt_f16 s5, 1.0 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0x00,0x3c,0x00,0x00]
+
+v_s_sqrt_f16 s5, -1.0
+// GFX12: v_s_sqrt_f16 s5, -1.0 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0x00,0xbc,0x00,0x00]
+
+v_s_sqrt_f16 s5, 2.0
+// GFX12: v_s_sqrt_f16 s5, 2.0 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0x00,0x40,0x00,0x00]
+
+v_s_sqrt_f16 s5, -2.0
+// GFX12: v_s_sqrt_f16 s5, -2.0 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0x00,0xc0,0x00,0x00]
+
+v_s_sqrt_f16 s5, 4.0
+// GFX12: v_s_sqrt_f16 s5, 4.0 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0x00,0x44,0x00,0x00]
+
+v_s_sqrt_f16 s5, -4.0
+// GFX12: v_s_sqrt_f16 s5, -4.0 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0x00,0xc4,0x00,0x00]
+
+v_s_sqrt_f16 s5, 0.15915494
+// GFX12: v_s_sqrt_f16 s5, 0.15915494 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0x18,0x31,0x00,0x00]
v_s_sqrt_f16 s5, src_scc
// GFX12: v_s_sqrt_f16 s5, src_scc ; encoding: [0x05,0x00,0x89,0xd6,0xfd,0x00,0x01,0x02]
diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
index d53c51b2dfb07..05cf0b553b184 100644
--- a/llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
@@ -7285,6 +7285,30 @@ v_s_exp_f16 s5, -1
v_s_exp_f16 s5, 0.5
// GFX13: v_s_exp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x81,0xd6,0xf0,0x00,0x01,0x02]
+v_s_exp_f16 s5, -0.5
+// GFX13: v_s_exp_f16 s5, -0.5 ; encoding: [0x05,0x00,0x81,0xd6,0xf1,0x00,0x01,0x02]
+
+v_s_exp_f16 s5, 1.0
+// GFX13: v_s_exp_f16 s5, 1.0 ; encoding: [0x05,0x00,0x81,0xd6,0xf2,0x00,0x01,0x02]
+
+v_s_exp_f16 s5, -1.0
+// GFX13: v_s_exp_f16 s5, -1.0 ; encoding: [0x05,0x00,0x81,0xd6,0xf3,0x00,0x01,0x02]
+
+v_s_exp_f16 s5, 2.0
+// GFX13: v_s_exp_f16 s5, 2.0 ; encoding: [0x05,0x00,0x81,0xd6,0xf4,0x00,0x01,0x02]
+
+v_s_exp_f16 s5, -2.0
+// GFX13: v_s_exp_f16 s5, -2.0 ; encoding: [0x05,0x00,0x81,0xd6,0xf5,0x00,0x01,0x02]
+
+v_s_exp_f16 s5, 4.0
+// GFX13: v_s_exp_f16 s5, 4.0 ; encoding: [0x05,0x00,0x81,0xd6,0xf6,0x00,0x01,0x02]
+
+v_s_exp_f16 s5, -4.0
+// GFX13: v_s_exp_f16 s5, -4.0 ; encoding: [0x05,0x00,0x81,0xd6,0xf7,0x00,0x01,0x02]
+
+v_s_exp_f16 s5, 0.15915494
+// GFX13: v_s_exp_f16 s5, 0.15915494 ; encoding: [0x05,0x00,0x81,0xd6,0xf8,0x00,0x01,0x02]
+
v_s_exp_f16 s5, src_scc
// GFX13: v_s_exp_f16 s5, src_scc ; encoding: [0x05,0x00,0x81,0xd6,0xfd,0x00,0x01,0x02]
@@ -7399,6 +7423,30 @@ v_s_log_f16 s5, -1
v_s_log_f16 s5, 0.5
// GFX13: v_s_log_f16 s5, 0.5 ; encoding: [0x05,0x00,0x83,0xd6,0xf0,0x00,0x01,0x02]
+v_s_log_f16 s5, -0.5
+// GFX13: v_s_log_f16 s5, -0.5 ; encoding: [0x05,0x00,0x83,0xd6,0xf1,0x00,0x01,0x02]
+
+v_s_log_f16 s5, 1.0
+// GFX13: v_s_log_f16 s5, 1.0 ; encoding: [0x05,0x00,0x83,0xd6,0xf2,0x00,0x01,0x02]
+
+v_s_log_f16 s5, -1.0
+// GFX13: v_s_log_f16 s5, -1.0 ; encoding: [0x05,0x00,0x83,0xd6,0xf3,0x00,0x01,0x02]
+
+v_s_log_f16 s5, 2.0
+// GFX13: v_s_log_f16 s5, 2.0 ; encoding: [0x05,0x00,0x83,0xd6,0xf4,0x00,0x01,0x02]
+
+v_s_log_f16 s5, -2.0
+// GFX13: v_s_log_f16 s5, -2.0 ; encoding: [0x05,0x00,0x83,0xd6,0xf5,0x00,0x01,0x02]
+
+v_s_log_f16 s5, 4.0
+// GFX13: v_s_log_f16 s5, 4.0 ; encoding: [0x05,0x00,0x83,0xd6,0xf6,0x00,0x01,0x02]
+
+v_s_log_f16 s5, -4.0
+// GFX13: v_s_log_f16 s5, -4.0 ; encoding: [0x05,0x00,0x83,0xd6,0xf7,0x00,0x01,0x02]
+
+v_s_log_f16 s5, 0.15915494
+// GFX13: v_s_log_f16 s5, 0.15915494 ; encoding: [0x05,0x00,0x83,0xd6,0xf8,0x00,0x01,0x02]
+
v_s_log_f16 s5, src_scc
// GFX13: v_s_log_f16 s5, src_scc ; encoding: [0x05,0x00,0x83,0xd6,0xfd,0x00,0x01,0x02]
@@ -7513,6 +7561,30 @@ v_s_rcp_f16 s5, -1
v_s_rcp_f16 s5, 0.5
// GFX13: v_s_rcp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x85,0xd6,0xf0,0x00,0x01,0x02]
+v_s_rcp_f16 s5, -0.5
+// GFX13: v_s_rcp_f16 s5, -0.5 ; encoding: [0x05,0x00,0x85,0xd6,0xf1,0x00,0x01,0x02]
+
+v_s_rcp_f16 s5, 1.0
+// GFX13: v_s_rcp_f16 s5, 1.0 ; encoding: [0x05,0x00,0x85,0xd6,0xf2,0x00,0x01,0x02]
+
+v_s_rcp_f16 s5, -1.0
+// GFX13: v_s_rcp_f16 s5, -1.0 ; encoding: [0x05,0x00,0x85,0xd6,0xf3,0x00,0x01,0x02]
+
+v_s_rcp_f16 s5, 2.0
+// GFX13: v_s_rcp_f16 s5, 2.0 ; encoding: [0x05,0x00,0x85,0xd6,0xf4,0x00,0x01,0x02]
+
+v_s_rcp_f16 s5, -2.0
+// GFX13: v_s_rcp_f16 s5, -2.0 ; encoding: [0x05,0x00,0x85,0xd6,0xf5,0x00,0x01,0x02]
+
+v_s_rcp_f16 s5, 4.0
+// GFX13: v_s_rcp_f16 s5, 4.0 ; encoding: [0x05,0x00,0x85,0xd6,0xf6,0x00,0x01,0x02]
+
+v_s_rcp_f16 s5, -4.0
+// GFX13: v_s_rcp_f16 s5, -4.0 ; encoding: [0x05,0x00,0x85,0xd6,0xf7,0x00,0x01,0x02]
+
+v_s_rcp_f16 s5, 0.15915494
+// GFX13: v_s_rcp_f16 s5, 0.15915494 ; encoding: [0x05,0x00,0x85,0xd6,0xf8,0x00,0x01,0x02]
+
v_s_rcp_f16 s5, src_scc
// GFX13: v_s_rcp_f16 s5, src_scc ; encoding: [0x05,0x00,0x85,0xd6,0xfd,0x00,0x01,0x02]
@@ -7627,6 +7699,30 @@ v_s_rsq_f16 s5, -1
v_s_rsq_f16 s5, 0.5
// GFX13: v_s_rsq_f16 s5, 0.5 ; encoding: [0x05,0x00,0x87,0xd6,0xf0,0x00,0x01,0x02]
+v_s_rsq_f16 s5, -0.5
+// GFX13: v_s_rsq_f16 s5, -0.5 ; encoding: [0x05,0x00,0x87,0xd6,0xf1,0x00,0x01,0x02]
+
+v_s_rsq_f16 s5, 1.0
+// GFX13: v_s_rsq_f16 s5, 1.0 ; encoding: [0x05,0x00,0x87,0xd6,0xf2,0x00,0x01,0x02]
+
+v_s_rsq_f16 s5, -1.0
+// GFX13: v_s_rsq_f16 s5, -1.0 ; encoding: [0x05,0x00,0x87,0xd6,0xf3,0x00,0x01,0x02]
+
+v_s_rsq_f16 s5, 2.0
+// GFX13: v_s_rsq_f16 s5, 2.0 ; encoding: [0x05,0x00,0x87,0xd6,0xf4,0x00,0x01,0x02]
+
+v_s_rsq_f16 s5, -2.0
+// GFX13: v_s_rsq_f16 s5, -2.0 ; encoding: [0x05,0x00,0x87,0xd6,0xf5,0x00,0x01,0x02]
+
+v_s_rsq_f16 s5, 4.0
+// GFX13: v_s_rsq_f16 s5, 4.0 ; encoding: [0x05,0x00,0x87,0xd6,0xf6,0x00,0x01,0x02]
+
+v_s_rsq_f16 s5, -4.0
+// GFX13: v_s_rsq_f16 s5, -4.0 ; encoding: [0x05,0x00,0x87,0xd6,0xf7,0x00,0x01,0x02]
+
+v_s_rsq_f16 s5, 0.15915494
+// GFX13: v_s_rsq_f16 s5, 0.15915494 ; encoding: [0x05,0x00,0x87,0xd6,0xf8,0x00,0x01,0x02]
+
v_s_rsq_f16 s5, src_scc
// GFX13: v_s_rsq_f16 s5, src_scc ; encoding: [0x05,0x00,0x87,0xd6,0xfd,0x00,0x01,0x02]
@@ -7741,6 +7837,30 @@ v_s_sqrt_f16 s5, -1
v_s_sqrt_f16 s5, 0.5
// GFX13: v_s_sqrt_f16 s5, 0.5 ; encoding: [0x05,0x00,0x89,0xd6,0xf0,0x00,0x01,0x02]
+v_s_sqrt_f16 s5, -0.5
+// GFX13: v_s_sqrt_f16 s5, -0.5 ; encoding: [0x05,0x00,0x89,0xd6,0xf1,0x00,0x01,0x02]
+
+v_s_sqrt_f16 s5, 1.0
+// GFX13: v_s_sqrt_f16 s5, 1.0 ; encoding: [0x05,0x00,0x89,0xd6,0xf2,0x00,0x01,0x02]
+
+v_s_sqrt_f16 s5, -1.0
+// GFX13: v_s_sqrt_f16 s5, -1.0 ; encoding: [0x05,0x00,0x89,0xd6,0xf3,0x00,0x01,0x02]
+
+v_s_sqrt_f16 s5, 2.0
+// GFX13: v_s_sqrt_f16 s5, 2.0 ; encoding: [0x05,0x00,0x89,0xd6,0xf4,0x00,0x01,0x02]
+
+v_s_sqrt_f16 s5, -2.0
+// GFX13: v_s_sqrt_f16 s5, -2.0 ; encoding: [0x05,0x00,0x89,0xd6,0xf5,0x00,0x01,0x02]
+
+v_s_sqrt_f16 s5, 4.0
+// GFX13: v_s_sqrt_f16 s5, 4.0 ; encoding: [0x05,0x00,0x89,0xd6,0xf6,0x00,0x01,0x02]
+
+v_s_sqrt_f16 s5, -4.0
+// GFX13: v_s_sqrt_f16 s5, -4.0 ; encoding: [0x05,0x00,0x89,0xd6,0xf7,0x00,0x01,0x02]
+
+v_s_sqrt_f16 s5, 0.15915494
+// GFX13: v_s_sqrt_f16 s5, 0.15915494 ; encoding: [0x05,0x00,0x89,0xd6,0xf8,0x00,0x01,0x02]
+
v_s_sqrt_f16 s5, src_scc
// GFX13: v_s_sqrt_f16 s5, src_scc ; encoding: [0x05,0x00,0x89,0xd6,0xfd,0x00,0x01,0x02]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
index c56b0d7441134..d448a27d32998 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
@@ -9039,10 +9039,34 @@
# GFX12: v_s_exp_f16 s5, null ; encoding: [0x05,0x00,0x81,0xd6,0x7c,0x00,0x01,0x02]
0x05,0x00,0x81,0xd6,0xc1,0x00,0x00,0x00
-# GFX12: v_s_exp_f16 s5, -1 ; encoding: [0x05,0x00,0x81,0xd6,0xc1,0x00,0x01,0x02]
+# GFX12: v_s_exp_f16 s5, -1 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
0x05,0x00,0x81,0xd6,0xf0,0x00,0x00,0x00
-# GFX12: v_s_exp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x81,0xd6,0xf0,0x00,0x01,0x02]
+# GFX12: v_s_exp_f16 s5, 0xf0 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xf0,0x00,0x00,0x00]
+
+0x05,0x00,0x81,0xd6,0xf1,0x00,0x00,0x00
+# GFX12: v_s_exp_f16 s5, 0xf1 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xf1,0x00,0x00,0x00]
+
+0x05,0x00,0x81,0xd6,0xf2,0x00,0x00,0x00
+# GFX12: v_s_exp_f16 s5, 0xf2 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xf2,0x00,0x00,0x00]
+
+0x05,0x00,0x81,0xd6,0xf3,0x00,0x00,0x00
+# GFX12: v_s_exp_f16 s5, 0xf3 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xf3,0x00,0x00,0x00]
+
+0x05,0x00,0x81,0xd6,0xf4,0x00,0x00,0x00
+# GFX12: v_s_exp_f16 s5, 0xf4 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xf4,0x00,0x00,0x00]
+
+0x05,0x00,0x81,0xd6,0xf5,0x00,0x00,0x00
+# GFX12: v_s_exp_f16 s5, 0xf5 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xf5,0x00,0x00,0x00]
+
+0x05,0x00,0x81,0xd6,0xf6,0x00,0x00,0x00
+# GFX12: v_s_exp_f16 s5, 0xf6 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xf6,0x00,0x00,0x00]
+
+0x05,0x00,0x81,0xd6,0xf7,0x00,0x00,0x00
+# GFX12: v_s_exp_f16 s5, 0xf7 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xf7,0x00,0x00,0x00]
+
+0x05,0x00,0x81,0xd6,0xf8,0x00,0x00,0x00
+# GFX12: v_s_exp_f16 s5, 0xf8 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xf8,0x00,0x00,0x00]
0x05,0x00,0x81,0xd6,0xfd,0x00,0x00,0x00
# GFX12: v_s_exp_f16 s5, src_scc ; encoding: [0x05,0x00,0x81,0xd6,0xfd,0x00,0x01,0x02]
@@ -9153,10 +9177,34 @@
# GFX12: v_s_log_f16 s5, null ; encoding: [0x05,0x00,0x83,0xd6,0x7c,0x00,0x01,0x02]
0x05,0x00,0x83,0xd6,0xc1,0x00,0x00,0x00
-# GFX12: v_s_log_f16 s5, -1 ; encoding: [0x05,0x00,0x83,0xd6,0xc1,0x00,0x01,0x02]
+# GFX12: v_s_log_f16 s5, -1 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
0x05,0x00,0x83,0xd6,0xf0,0x00,0x00,0x00
-# GFX12: v_s_log_f16 s5, 0.5 ; encoding: [0x05,0x00,0x83,0xd6,0xf0,0x00,0x01,0x02]
+# GFX12: v_s_log_f16 s5, 0xf0 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xf0,0x00,0x00,0x00]
+
+0x05,0x00,0x83,0xd6,0xf1,0x00,0x00,0x00
+# GFX12: v_s_log_f16 s5, 0xf1 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xf1,0x00,0x00,0x00]
+
+0x05,0x00,0x83,0xd6,0xf2,0x00,0x00,0x00
+# GFX12: v_s_log_f16 s5, 0xf2 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xf2,0x00,0x00,0x00]
+
+0x05,0x00,0x83,0xd6,0xf3,0x00,0x00,0x00
+# GFX12: v_s_log_f16 s5, 0xf3 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xf3,0x00,0x00,0x00]
+
+0x05,0x00,0x83,0xd6,0xf4,0x00,0x00,0x00
+# GFX12: v_s_log_f16 s5, 0xf4 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xf4,0x00,0x00,0x00]
+
+0x05,0x00,0x83,0xd6,0xf5,0x00,0x00,0x00
+# GFX12: v_s_log_f16 s5, 0xf5 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xf5,0x00,0x00,0x00]
+
+0x05,0x00,0x83,0xd6,0xf6,0x00,0x00,0x00
+# GFX12: v_s_log_f16 s5, 0xf6 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xf6,0x00,0x00,0x00]
+
+0x05,0x00,0x83,0xd6,0xf7,0x00,0x00,0x00
+# GFX12: v_s_log_f16 s5, 0xf7 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xf7,0x00,0x00,0x00]
+
+0x05,0x00,0x83,0xd6,0xf8,0x00,0x00,0x00
+# GFX12: v_s_log_f16 s5, 0xf8 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xf8,0x00,0x00,0x00]
0x05,0x00,0x83,0xd6,0xfd,0x00,0x00,0x00
# GFX12: v_s_log_f16 s5, src_scc ; encoding: [0x05,0x00,0x83,0xd6,0xfd,0x00,0x01,0x02]
@@ -9267,10 +9315,34 @@
# GFX12: v_s_rcp_f16 s5, null ; encoding: [0x05,0x00,0x85,0xd6,0x7c,0x00,0x01,0x02]
0x05,0x00,0x85,0xd6,0xc1,0x00,0x00,0x00
-# GFX12: v_s_rcp_f16 s5, -1 ; encoding: [0x05,0x00,0x85,0xd6,0xc1,0x00,0x01,0x02]
+# GFX12: v_s_rcp_f16 s5, -1 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
0x05,0x00,0x85,0xd6,0xf0,0x00,0x00,0x00
-# GFX12: v_s_rcp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x85,0xd6,0xf0,0x00,0x01,0x02]
+# GFX12: v_s_rcp_f16 s5, 0xf0 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xf0,0x00,0x00,0x00]
+
+0x05,0x00,0x85,0xd6,0xf1,0x00,0x00,0x00
+# GFX12: v_s_rcp_f16 s5, 0xf1 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xf1,0x00,0x00,0x00]
+
+0x05,0x00,0x85,0xd6,0xf2,0x00,0x00,0x00
+# GFX12: v_s_rcp_f16 s5, 0xf2 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xf2,0x00,0x00,0x00]
+
+0x05,0x00,0x85,0xd6,0xf3,0x00,0x00,0x00
+# GFX12: v_s_rcp_f16 s5, 0xf3 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xf3,0x00,0x00,0x00]
+
+0x05,0x00,0x85,0xd6,0xf4,0x00,0x00,0x00
+# GFX12: v_s_rcp_f16 s5, 0xf4 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xf4,0x00,0x00,0x00]
+
+0x05,0x00,0x85,0xd6,0xf5,0x00,0x00,0x00
+# GFX12: v_s_rcp_f16 s5, 0xf5 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xf5,0x00,0x00,0x00]
+
+0x05,0x00,0x85,0xd6,0xf6,0x00,0x00,0x00
+# GFX12: v_s_rcp_f16 s5, 0xf6 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xf6,0x00,0x00,0x00]
+
+0x05,0x00,0x85,0xd6,0xf7,0x00,0x00,0x00
+# GFX12: v_s_rcp_f16 s5, 0xf7 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xf7,0x00,0x00,0x00]
+
+0x05,0x00,0x85,0xd6,0xf8,0x00,0x00,0x00
+# GFX12: v_s_rcp_f16 s5, 0xf8 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xf8,0x00,0x00,0x00]
0x05,0x00,0x85,0xd6,0xfd,0x00,0x00,0x00
# GFX12: v_s_rcp_f16 s5, src_scc ; encoding: [0x05,0x00,0x85,0xd6,0xfd,0x00,0x01,0x02]
@@ -9381,10 +9453,34 @@
# GFX12: v_s_rsq_f16 s5, null ; encoding: [0x05,0x00,0x87,0xd6,0x7c,0x00,0x01,0x02]
0x05,0x00,0x87,0xd6,0xc1,0x00,0x00,0x00
-# GFX12: v_s_rsq_f16 s5, -1 ; encoding: [0x05,0x00,0x87,0xd6,0xc1,0x00,0x01,0x02]
+# GFX12: v_s_rsq_f16 s5, -1 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
0x05,0x00,0x87,0xd6,0xf0,0x00,0x00,0x00
-# GFX12: v_s_rsq_f16 s5, 0.5 ; encoding: [0x05,0x00,0x87,0xd6,0xf0,0x00,0x01,0x02]
+# GFX12: v_s_rsq_f16 s5, 0xf0 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xf0,0x00,0x00,0x00]
+
+0x05,0x00,0x87,0xd6,0xf1,0x00,0x00,0x00
+# GFX12: v_s_rsq_f16 s5, 0xf1 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xf1,0x00,0x00,0x00]
+
+0x05,0x00,0x87,0xd6,0xf2,0x00,0x00,0x00
+# GFX12: v_s_rsq_f16 s5, 0xf2 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xf2,0x00,0x00,0x00]
+
+0x05,0x00,0x87,0xd6,0xf3,0x00,0x00,0x00
+# GFX12: v_s_rsq_f16 s5, 0xf3 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xf3,0x00,0x00,0x00]
+
+0x05,0x00,0x87,0xd6,0xf4,0x00,0x00,0x00
+# GFX12: v_s_rsq_f16 s5, 0xf4 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xf4,0x00,0x00,0x00]
+
+0x05,0x00,0x87,0xd6,0xf5,0x00,0x00,0x00
+# GFX12: v_s_rsq_f16 s5, 0xf5 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xf5,0x00,0x00,0x00]
+
+0x05,0x00,0x87,0xd6,0xf6,0x00,0x00,0x00
+# GFX12: v_s_rsq_f16 s5, 0xf6 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xf6,0x00,0x00,0x00]
+
+0x05,0x00,0x87,0xd6,0xf7,0x00,0x00,0x00
+# GFX12: v_s_rsq_f16 s5, 0xf7 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xf7,0x00,0x00,0x00]
+
+0x05,0x00,0x87,0xd6,0xf8,0x00,0x00,0x00
+# GFX12: v_s_rsq_f16 s5, 0xf8 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xf8,0x00,0x00,0x00]
0x05,0x00,0x87,0xd6,0xfd,0x00,0x00,0x00
# GFX12: v_s_rsq_f16 s5, src_scc ; encoding: [0x05,0x00,0x87,0xd6,0xfd,0x00,0x01,0x02]
@@ -9495,10 +9591,34 @@
# GFX12: v_s_sqrt_f16 s5, null ; encoding: [0x05,0x00,0x89,0xd6,0x7c,0x00,0x01,0x02]
0x05,0x00,0x89,0xd6,0xc1,0x00,0x00,0x00
-# GFX12: v_s_sqrt_f16 s5, -1 ; encoding: [0x05,0x00,0x89,0xd6,0xc1,0x00,0x01,0x02]
+# GFX12: v_s_sqrt_f16 s5, -1 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
0x05,0x00,0x89,0xd6,0xf0,0x00,0x00,0x00
-# GFX12: v_s_sqrt_f16 s5, 0.5 ; encoding: [0x05,0x00,0x89,0xd6,0xf0,0x00,0x01,0x02]
+# GFX12: v_s_sqrt_f16 s5, 0xf0 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xf0,0x00,0x00,0x00]
+
+0x05,0x00,0x89,0xd6,0xf1,0x00,0x00,0x00
+# GFX12: v_s_sqrt_f16 s5, 0xf1 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xf1,0x00,0x00,0x00]
+
+0x05,0x00,0x89,0xd6,0xf2,0x00,0x00,0x00
+# GFX12: v_s_sqrt_f16 s5, 0xf2 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xf2,0x00,0x00,0x00]
+
+0x05,0x00,0x89,0xd6,0xf3,0x00,0x00,0x00
+# GFX12: v_s_sqrt_f16 s5, 0xf3 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xf3,0x00,0x00,0x00]
+
+0x05,0x00,0x89,0xd6,0xf4,0x00,0x00,0x00
+# GFX12: v_s_sqrt_f16 s5, 0xf4 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xf4,0x00,0x00,0x00]
+
+0x05,0x00,0x89,0xd6,0xf5,0x00,0x00,0x00
+# GFX12: v_s_sqrt_f16 s5, 0xf5 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xf5,0x00,0x00,0x00]
+
+0x05,0x00,0x89,0xd6,0xf6,0x00,0x00,0x00
+# GFX12: v_s_sqrt_f16 s5, 0xf6 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xf6,0x00,0x00,0x00]
+
+0x05,0x00,0x89,0xd6,0xf7,0x00,0x00,0x00
+# GFX12: v_s_sqrt_f16 s5, 0xf7 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xf7,0x00,0x00,0x00]
+
+0x05,0x00,0x89,0xd6,0xf8,0x00,0x00,0x00
+# GFX12: v_s_sqrt_f16 s5, 0xf8 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xf8,0x00,0x00,0x00]
0x05,0x00,0x89,0xd6,0xfd,0x00,0x00,0x00
# GFX12: v_s_sqrt_f16 s5, src_scc ; encoding: [0x05,0x00,0x89,0xd6,0xfd,0x00,0x01,0x02]
More information about the llvm-commits
mailing list