[llvm] [VPlan] Remove VPInstruction::Not. NFC (PR #222228)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 8 20:57:56 PDT 2026
https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/222228
It can be represented by a canonical `xor x, -1`. The motiviation for this is to help streamline pattern matchers so we can start dispatching combineRecipes based on opcodes.
>From 6a091b94d56b43bec90a552e9c1c37405c99d896 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Tue, 8 Sep 2026 18:21:54 +0800
Subject: [PATCH] [VPlan] Remove VPInstruction::Not. NFC
It can be represented by a canonical `xor x, -1`. The motiviation for this is to help streamline pattern matchers so we can start dispatching combineRecipes based on opcodes.
---
.../Vectorize/LoopVectorizationPlanner.h | 5 +-
llvm/lib/Transforms/Vectorize/VPlan.h | 1 -
.../Vectorize/VPlanConstruction.cpp | 3 +-
.../Transforms/Vectorize/VPlanPatternMatch.h | 3 +-
.../lib/Transforms/Vectorize/VPlanRecipes.cpp | 32 ++++---------
llvm/lib/Transforms/Vectorize/VPlanUtils.cpp | 4 --
.../LoopVectorize/AArch64/arith-costs.ll | 32 ++++++-------
.../LoopVectorize/AArch64/cmp_cost.ll | 6 +--
.../VPlan/AArch64/sve-tail-folding-forced.ll | 2 +-
.../AArch64/vplan-memory-op-decisions.ll | 4 +-
.../AArch64/vplan-printing-alias-mask.ll | 2 +-
.../VPlan/AArch64/vplan-printing.ll | 2 +-
.../VPlan/execution-frequencies-match-bfi.ll | 16 +++----
.../LoopVectorize/VPlan/predicator.ll | 48 +++++++++----------
.../VPlan/vplan-predicate-switch.ll | 2 +-
.../VPlan/vplan-printing-flags.ll | 4 +-
.../LoopVectorize/VPlan/vplan-printing.ll | 2 +-
.../X86/CostModel/vpinstruction-cost.ll | 4 +-
.../Transforms/Vectorize/VPlanHCFGTest.cpp | 4 +-
.../Vectorize/VPlanVerifierTest.cpp | 10 ++--
20 files changed, 83 insertions(+), 103 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
index 972f8f8e642e2..ada06acbc0b62 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
@@ -257,7 +257,10 @@ class VPBuilder {
VPInstruction *createNot(VPValue *Operand,
DebugLoc DL = DebugLoc::getUnknown(),
const Twine &Name = "") {
- return createInstruction(VPInstruction::Not, {Operand}, {}, DL, Name);
+ return createInstruction(
+ Instruction::Xor,
+ {Operand, getPlan().getAllOnesValue(Operand->getScalarType())}, {}, DL,
+ Name);
}
VPInstruction *createAnd(VPValue *LHS, VPValue *RHS,
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h
index e9f18506af7c2..71c224dec73f9 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -1270,7 +1270,6 @@ class LLVM_ABI_FOR_TEST VPInstruction : public VPRecipeWithIRFlags,
FirstOrderRecurrenceSplice =
Instruction::OtherOpsEnd + 1, // Combines the incoming and previous
// values of a first-order recurrence.
- Not,
// Creates a mask where each lane is active (true) whilst the current
// counter (first operand + index) is less than the second operand. i.e.
// mask[i] = icmpt ult (op0 + i), op1
diff --git a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
index a2006ebf4bb4f..66227ce322249 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
@@ -425,8 +425,7 @@ static bool canonicalHeaderAndLatch(VPBlockBase *HeaderVPB,
assert(cast<VPInstruction>(Term)->getOpcode() ==
VPInstruction::BranchOnCond &&
"terminator must be a BranchOnCond");
- auto *Not = new VPInstruction(VPInstruction::Not, {Term->getOperand(0)});
- Not->insertBefore(Term);
+ VPValue *Not = VPBuilder(Term).createNot(Term->getOperand(0));
Term->setOperand(0, Not);
LatchVPBB->swapSuccessors();
diff --git a/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h b/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
index df49dbb3c2289..69e9447855cce 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
@@ -862,8 +862,7 @@ inline auto m_SelectLike(const Op0_t &Op0, const Op1_t &Op1, const Op2_t &Op2) {
}
template <typename Op0_t> inline auto m_Not(const Op0_t &Op0) {
- return m_CombineOr(m_VPInstruction<VPInstruction::Not>(Op0),
- m_c_Binary<Instruction::Xor>(m_AllOnes(), Op0));
+ return m_c_Binary<Instruction::Xor>(m_AllOnes(), Op0);
}
template <typename Op0_t, typename Op1_t, typename Op2_t>
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index ade13eabd9431..fbdf5eb3e7765 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -649,7 +649,6 @@ unsigned VPInstruction::getNumOperandsForOpcode() const {
case VPInstruction::ExtractLastPart:
case VPInstruction::ExtractPenultimateElement:
case VPInstruction::MaskedCond:
- case VPInstruction::Not:
case VPInstruction::Reverse:
case VPInstruction::Unpack:
case VPInstruction::NumActiveLanes:
@@ -721,7 +720,6 @@ bool VPInstruction::canGenerateScalarForFirstLane() const {
case VPInstruction::PtrAdd:
case VPInstruction::ExplicitVectorLength:
case VPInstruction::AnyOf:
- case VPInstruction::Not:
return true;
default:
return false;
@@ -751,11 +749,6 @@ Value *VPInstruction::generate(VPTransformState &State) {
}
switch (getOpcode()) {
- case VPInstruction::Not: {
- bool OnlyFirstLaneUsed = vputils::onlyFirstLaneUsed(this);
- Value *A = State.get(getOperand(0), OnlyFirstLaneUsed);
- return Builder.CreateNot(A, Name);
- }
case Instruction::ExtractElement: {
assert(State.VF.isVector() && "Only extract elements from vectors");
if (auto *Idx = dyn_cast<VPConstantInt>(getOperand(1)))
@@ -1332,12 +1325,19 @@ InstructionCost VPRecipeWithIRFlags::getCostForRecipeWithOpcode(
InstructionCost VPInstruction::computeCost(ElementCount VF,
VPCostContext &Ctx) const {
if (Instruction::isBinaryOp(getOpcode())) {
- if (!getUnderlyingValue() && getOpcode() != Instruction::FMul) {
+ if (!getUnderlyingValue() && getOpcode() != Instruction::FMul &&
+ !match(this, m_Not(m_VPValue()))) {
// TODO: Compute cost for VPInstructions without underlying values once
// the legacy cost model has been retired.
return 0;
}
+ // InstCombine will fold `xor` to the conditional branch.
+ if (match(this, m_Not(m_VPValue())))
+ if (auto *U = const_cast<VPUser *>(getSingleUser()))
+ if (match(U, m_BranchOnCond(m_VPValue())))
+ return 0;
+
assert(!doesGeneratePerAllLanes() &&
"Should only generate a vector value or single scalar, not scalars "
"for all lanes.");
@@ -1467,17 +1467,6 @@ InstructionCost VPInstruction::computeCost(ElementCount VF,
return Ctx.TTI.getIndexedVectorInstrCostFromEnd(Instruction::ExtractElement,
VecTy, Ctx.CostKind, 0);
}
- case VPInstruction::Not: {
- Type *ValTy = this->getScalarType();
- // InstCombine will fold `xor` to the conditional branch.
- if (auto *U = const_cast<VPUser *>(getSingleUser()))
- if (match(U, m_BranchOnCond(m_VPValue())))
- return 0;
- if (!vputils::onlyFirstLaneUsed(this))
- ValTy = toVectorTy(ValTy, VF);
- return Ctx.TTI.getArithmeticInstrCost(Instruction::Xor, ValTy,
- Ctx.CostKind);
- }
case VPInstruction::BranchOnCount: {
// If TC <= VF then this is just a branch.
// FIXME: Removing the branch happens in simplifyBranchConditionForVFAndUF
@@ -1653,7 +1642,6 @@ bool VPInstruction::opcodeMayReadOrWriteFromMemory() const {
case VPInstruction::LogicalAnd:
case VPInstruction::LogicalOr:
case VPInstruction::MaskedCond:
- case VPInstruction::Not:
case VPInstruction::PtrAdd:
case VPInstruction::WideIVStep:
case VPInstruction::WidePtrAdd:
@@ -1694,7 +1682,6 @@ bool VPInstruction::usesFirstLaneOnly(const VPValue *Op) const {
case Instruction::Select:
case Instruction::Or:
case Instruction::Freeze:
- case VPInstruction::Not:
// TODO: Cover additional opcodes.
return vputils::onlyFirstLaneUsed(this);
case Instruction::Load:
@@ -1765,9 +1752,6 @@ void VPInstruction::printRecipe(raw_ostream &O, const Twine &Indent,
}
switch (getOpcode()) {
- case VPInstruction::Not:
- O << "not";
- break;
case VPInstruction::ActiveLaneMask:
O << "active lane mask";
break;
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
index befc2d477aac4..e924b795c72df 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
@@ -413,7 +413,6 @@ static bool preservesUniformity(unsigned Opcode) {
case Instruction::ICmp:
case Instruction::FCmp:
case Instruction::Select:
- case VPInstruction::Not:
case VPInstruction::Broadcast:
case VPInstruction::MaskedCond:
case VPInstruction::PtrAdd:
@@ -1293,9 +1292,6 @@ VPIRValue *vputils::tryToFoldLiveIns(VPSingleDefRecipe &R,
return Folder.FoldCast(static_cast<Instruction::CastOps>(Opcode), Ops[0],
R.getVPSingleValue()->getScalarType());
switch (Opcode) {
- case VPInstruction::Not:
- return Folder.FoldBinOp(Instruction::BinaryOps::Xor, Ops[0],
- Constant::getAllOnesValue(Ops[0]->getType()));
case Instruction::Select:
return Folder.FoldSelect(Ops[0], Ops[1], Ops[2]);
case Instruction::ICmp:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/arith-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/arith-costs.ll
index 9b02fd24c828d..9bb94d8bf4175 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/arith-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/arith-costs.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "[Cc]ost.*(udiv|fneg|fmul|not)"
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "[Cc]ost.*(udiv|fneg|fmul|xor)"
; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize %s -S -o - 2>&1 | FileCheck %s
; REQUIRES: asserts
@@ -71,21 +71,21 @@ exit:
define i32 @test_scalar_and_widen_not_cost(ptr readonly %a, i64 noundef %n) {
; CHECK-LABEL: 'test_scalar_and_widen_not_cost'
-; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP7:%[0-9]+]]> = not ir<%cmp1>
-; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP12:%[0-9]+]]> = not vp<[[VP11:%[0-9]+]]>
-; CHECK: Cost of 1 for VF 4: EMIT vp<[[VP7]]> = not ir<%cmp1>
-; CHECK: Cost of 1 for VF 4: EMIT vp<[[VP12]]> = not vp<[[VP11]]>
-; CHECK: Cost of 1 for VF 8: EMIT vp<[[VP7]]> = not ir<%cmp1>
-; CHECK: Cost of 1 for VF 8: EMIT vp<[[VP12]]> = not vp<[[VP11]]>
-; CHECK: Cost of 1 for VF 16: EMIT vp<[[VP7]]> = not ir<%cmp1>
-; CHECK: Cost of 1 for VF 16: EMIT vp<[[VP12]]> = not vp<[[VP11]]>
-; CHECK: Cost of 2 for VF 32: EMIT vp<[[VP7]]> = not ir<%cmp1>
-; CHECK: Cost of 1 for VF 32: EMIT vp<[[VP12]]> = not vp<[[VP11]]>
-; CHECK: Cost of 4 for VF 64: EMIT vp<[[VP7]]> = not ir<%cmp1>
-; CHECK: Cost of 1 for VF 64: EMIT vp<[[VP12]]> = not vp<[[VP11]]>
-; CHECK: Cost of 8 for VF 128: EMIT vp<[[VP7]]> = not ir<%cmp1>
-; CHECK: Cost of 1 for VF 128: EMIT vp<[[VP12]]> = not vp<[[VP11]]>
-; CHECK: Cost of 1 for VF 16: EMIT vp<[[VP12]]> = not vp<[[VP11]]>
+; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP7:%[0-9]+]]> = xor ir<%cmp1>, ir<true>
+; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP12:%[0-9]+]]> = xor vp<[[VP11:%[0-9]+]]>, ir<true>
+; CHECK: Cost of 1 for VF 4: EMIT vp<[[VP7]]> = xor ir<%cmp1>, ir<true>
+; CHECK: Cost of 1 for VF 4: EMIT vp<[[VP12]]> = xor vp<[[VP11]]>, ir<true>
+; CHECK: Cost of 1 for VF 8: EMIT vp<[[VP7]]> = xor ir<%cmp1>, ir<true>
+; CHECK: Cost of 1 for VF 8: EMIT vp<[[VP12]]> = xor vp<[[VP11]]>, ir<true>
+; CHECK: Cost of 1 for VF 16: EMIT vp<[[VP7]]> = xor ir<%cmp1>, ir<true>
+; CHECK: Cost of 1 for VF 16: EMIT vp<[[VP12]]> = xor vp<[[VP11]]>, ir<true>
+; CHECK: Cost of 2 for VF 32: EMIT vp<[[VP7]]> = xor ir<%cmp1>, ir<true>
+; CHECK: Cost of 1 for VF 32: EMIT vp<[[VP12]]> = xor vp<[[VP11]]>, ir<true>
+; CHECK: Cost of 4 for VF 64: EMIT vp<[[VP7]]> = xor ir<%cmp1>, ir<true>
+; CHECK: Cost of 1 for VF 64: EMIT vp<[[VP12]]> = xor vp<[[VP11]]>, ir<true>
+; CHECK: Cost of 8 for VF 128: EMIT vp<[[VP7]]> = xor ir<%cmp1>, ir<true>
+; CHECK: Cost of 1 for VF 128: EMIT vp<[[VP12]]> = xor vp<[[VP11]]>, ir<true>
+; CHECK: Cost of 1 for VF 16: EMIT vp<[[VP12]]> = xor vp<[[VP11]]>, ir<true>
;
entry:
br label %loop
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/cmp_cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/cmp_cost.ll
index a25edccb60514..37707c3f4d17e 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/cmp_cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/cmp_cost.ll
@@ -37,7 +37,7 @@ define float @fmaxnum_reduction_f32(float %base, i32 %n) {
; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP10]]> = select vp<[[VP5]]>, vp<[[VP3]]>, vp<[[VP2]]>
; CHECK: Cost of 0 for VF 2: EMIT vp<[[VP11]]> = compute-reduction-result (fmaxnum) vp<[[VP9]]>
; CHECK: Cost of 1 for VF 2: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]>
-; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP12:%[0-9]+]]> = not vp<[[VP5]]>
+; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP12:%[0-9]+]]> = xor vp<[[VP5]]>, ir<true>
; CHECK: Cost of 0 for VF 2: EMIT vp<[[VP13:%[0-9]+]]> = and vp<%cmp.n>, vp<[[VP12]]>
; CHECK: Cost of 0 for VF 2: EMIT branch-on-cond vp<[[VP13]]>
; CHECK: Cost of 0 for VF 2: IR %max.next.lcssa = phi float [ %max.next, %loop ] (extra operand: vp<[[VP11]]> from middle.block)
@@ -67,7 +67,7 @@ define float @fmaxnum_reduction_f32(float %base, i32 %n) {
; CHECK: Cost of 1 for VF 4: EMIT vp<[[VP10]]> = select vp<[[VP5]]>, vp<[[VP3]]>, vp<[[VP2]]>
; CHECK: Cost of 0 for VF 4: EMIT vp<[[VP11]]> = compute-reduction-result (fmaxnum) vp<[[VP9]]>
; CHECK: Cost of 1 for VF 4: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]>
-; CHECK: Cost of 1 for VF 4: EMIT vp<[[VP12]]> = not vp<[[VP5]]>
+; CHECK: Cost of 1 for VF 4: EMIT vp<[[VP12]]> = xor vp<[[VP5]]>, ir<true>
; CHECK: Cost of 0 for VF 4: EMIT vp<[[VP13]]> = and vp<%cmp.n>, vp<[[VP12]]>
; CHECK: Cost of 0 for VF 4: EMIT branch-on-cond vp<[[VP13]]>
; CHECK: Cost of 0 for VF 4: IR %max.next.lcssa = phi float [ %max.next, %loop ] (extra operand: vp<[[VP11]]> from middle.block)
@@ -118,7 +118,7 @@ define double @fmaxnum_reduction_f64(double %base, i64 %n) {
; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP10]]> = select vp<[[VP5]]>, vp<[[VP3]]>, vp<[[VP2]]>
; CHECK: Cost of 0 for VF 2: EMIT vp<[[VP11]]> = compute-reduction-result (fmaxnum) vp<[[VP9]]>
; CHECK: Cost of 1 for VF 2: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]>
-; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP12:%[0-9]+]]> = not vp<[[VP5]]>
+; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP12:%[0-9]+]]> = xor vp<[[VP5]]>, ir<true>
; CHECK: Cost of 0 for VF 2: EMIT vp<[[VP13:%[0-9]+]]> = and vp<%cmp.n>, vp<[[VP12]]>
; CHECK: Cost of 0 for VF 2: EMIT branch-on-cond vp<[[VP13]]>
; CHECK: Cost of 0 for VF 2: IR %max.next.lcssa = phi double [ %max.next, %loop ] (extra operand: vp<[[VP11]]> from middle.block)
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve-tail-folding-forced.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve-tail-folding-forced.ll
index ddf757691047d..fb53e330798de 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve-tail-folding-forced.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve-tail-folding-forced.ll
@@ -34,7 +34,7 @@ target triple = "aarch64-unknown-linux-gnu"
; VPLANS-NEXT: EMIT vp<[[INDV_UPDATE:%.+]]> = add vp<[[INDV]]>, vp<[[VFxUF]]>
; VPLANS-NEXT: EMIT vp<[[LANEMASK_LOOP_MASK:%.+]]> = wide active lane mask vp<[[INDV_UPDATE]]>, vp<[[TC]]>, ir<1>
; VPLANS-NEXT: EMIT vp<[[LANEMASK_LOOP]]> = extract-vector-for-part vp<[[LANEMASK_LOOP_MASK]]>, ir<0>
-; VPLANS-NEXT: EMIT vp<[[NOT:%[0-9]+]]> = not vp<[[LANEMASK_LOOP]]>
+; VPLANS-NEXT: EMIT vp<[[NOT:%[0-9]+]]> = xor vp<[[LANEMASK_LOOP]]>, ir<true>
; VPLANS-NEXT: EMIT branch-on-cond vp<[[NOT]]>
; VPLANS-NEXT: No successors
; VPLANS-NEXT: }
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll
index af2978f1bfab4..9662286e4f3b5 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll
@@ -753,7 +753,7 @@ define void @blend_with_identical_incoming_values_address(ptr noalias %A, i1 %c)
; CHECK-NEXT: Successor(s): else
; CHECK-EMPTY:
; CHECK-NEXT: else:
-; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = not ir<%c>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = xor ir<%c>, ir<true>
; CHECK-NEXT: EMIT ir<%idx.else> = add nsw ir<%iv>, ir<-1>, vp<[[VP4]]>
; CHECK-NEXT: Successor(s): then
; CHECK-EMPTY:
@@ -996,7 +996,7 @@ define void @blend_with_different_incoming_values_address(ptr noalias %A, ptr no
; CHECK-NEXT: Successor(s): else
; CHECK-EMPTY:
; CHECK-NEXT: else:
-; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = not ir<%c>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = xor ir<%c>, ir<true>
; CHECK-NEXT: EMIT ir<%idx.else> = add nsw ir<%iv>, ir<-2>, vp<[[VP4]]>
; CHECK-NEXT: Successor(s): then
; CHECK-EMPTY:
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll
index c40aad62202dd..1c822f01bdfd4 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll
@@ -43,7 +43,7 @@ define void @alias_mask(ptr noalias %a, ptr %b, ptr %c, i64 %n) {
; FINAL-NEXT: EMIT vp<%index.next> = add vp<%index>, vp<%num.active.lanes>
; FINAL-NEXT: EMIT vp<%active.lane.mask.next> = wide active lane mask vp<%index.next>, ir<%n>, ir<1>
; FINAL-NEXT: EMIT vp<%extract.next.alm.part> = extract-vector-for-part vp<%active.lane.mask.next>, ir<0>
-; FINAL-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = not vp<%extract.next.alm.part>
+; FINAL-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = xor vp<%extract.next.alm.part>, ir<true>
; FINAL-NEXT: EMIT branch-on-cond vp<[[VP10]]>
; FINAL-NEXT: Successor(s): middle.block, vector.body
; FINAL-EMPTY:
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll
index 8111b770e3c4b..2b320b1f677dd 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll
@@ -127,7 +127,7 @@ define i32 @print_partial_reduction_predication(ptr %a, ptr %b, i64 %N) "target-
; CHECK-NEXT: EMIT vp<%index.next> = add vp<[[VP4]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT vp<%active.lane.mask.next> = wide active lane mask vp<%index.next>, ir<%N>, ir<1>
; CHECK-NEXT: EMIT vp<%extract.next.alm.part> = extract-vector-for-part vp<%active.lane.mask.next>, ir<0>
-; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = not vp<%extract.next.alm.part>
+; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = xor vp<%extract.next.alm.part>, ir<true>
; CHECK-NEXT: EMIT branch-on-cond vp<[[VP11]]>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll b/llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
index 0b0a698b42bf2..925a8c97b88c0 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
@@ -95,7 +95,7 @@ define void @two_preds(ptr noalias %a, ptr noalias %b, ptr noalias %c, ptr noali
; VPLAN-NEXT: Successor(s): else
; VPLAN-EMPTY:
; VPLAN-NEXT: else:
-; VPLAN-NEXT: EMIT vp<[[NOT_C0:%.+]]> = not ir<%c.0>
+; VPLAN-NEXT: EMIT vp<[[NOT_C0:%.+]]> = xor ir<%c.0>, ir<true>
; VPLAN-NEXT: EMIT ir<%gep.c> = getelementptr inbounds ir<%c>, ir<%iv>
; VPLAN-NEXT: EMIT store ir<%i>, ir<%gep.c>, vp<[[NOT_C0]]> (!vplan.execution.frequency 6917529027641081856 (75%))
; VPLAN-NEXT: EMIT ir<%c.1> = icmp slt ir<%i>, ir<-100>, vp<[[NOT_C0]]> (!vplan.execution.frequency 6917529027641081856 (75%))
@@ -319,7 +319,7 @@ define void @switch_common_dest(ptr noalias %a, ptr noalias %b, ptr noalias %c,
; VPLAN-NEXT: EMIT vp<[[C2:%.+]]> = icmp eq ir<%l>, ir<2>
; VPLAN-NEXT: EMIT vp<[[C0_OR_C1:%.+]]> = or vp<[[C0]]>, vp<[[C1]]>
; VPLAN-NEXT: EMIT vp<[[ANY:%.+]]> = or vp<[[C0_OR_C1]]>, vp<[[C2]]>
-; VPLAN-NEXT: EMIT vp<[[DEFAULT:%.+]]> = not vp<[[ANY]]>
+; VPLAN-NEXT: EMIT vp<[[DEFAULT:%.+]]> = xor vp<[[ANY]]>, ir<true>
; VPLAN-NEXT: EMIT ir<%gep.b> = getelementptr inbounds ir<%b>, ir<%iv>
; VPLAN-NEXT: EMIT store ir<2>, ir<%gep.b>, vp<[[C2]]> (!vplan.execution.frequency 1152921504606846976 (12.5%))
; VPLAN-NEXT: Successor(s): if.then
@@ -404,7 +404,7 @@ define void @switch_common_dest_weight_sum_not_a_power_of_two(ptr noalias %a, pt
; VPLAN-NEXT: EMIT vp<[[C0:%.+]]> = icmp eq ir<%l>, ir<0>
; VPLAN-NEXT: EMIT vp<[[C1:%.+]]> = icmp eq ir<%l>, ir<1>
; VPLAN-NEXT: EMIT vp<[[C0_OR_C1:%.+]]> = or vp<[[C0]]>, vp<[[C1]]>
-; VPLAN-NEXT: EMIT vp<[[DEFAULT:%.+]]> = not vp<[[C0_OR_C1]]>
+; VPLAN-NEXT: EMIT vp<[[DEFAULT:%.+]]> = xor vp<[[C0_OR_C1]]>, ir<true>
; VPLAN-NEXT: EMIT ir<%gep.a> = getelementptr inbounds ir<%a>, ir<%iv>
; VPLAN-NEXT: EMIT store ir<1>, ir<%gep.a>, vp<[[C0_OR_C1]]> (!vplan.execution.frequency 6148914689804861440 (66.67%))
; VPLAN-NEXT: Successor(s): default
@@ -477,7 +477,7 @@ define void @switch_common_dest_almost_always_taken(ptr noalias %a, ptr noalias
; VPLAN-NEXT: EMIT vp<[[C0:%.+]]> = icmp eq ir<%l>, ir<0>
; VPLAN-NEXT: EMIT vp<[[C1:%.+]]> = icmp eq ir<%l>, ir<1>
; VPLAN-NEXT: EMIT vp<[[C0_OR_C1:%.+]]> = or vp<[[C0]]>, vp<[[C1]]>
-; VPLAN-NEXT: EMIT vp<[[DEFAULT:%.+]]> = not vp<[[C0_OR_C1]]>
+; VPLAN-NEXT: EMIT vp<[[DEFAULT:%.+]]> = xor vp<[[C0_OR_C1]]>, ir<true>
; VPLAN-NEXT: EMIT ir<%gep.a> = getelementptr inbounds ir<%a>, ir<%iv>
; VPLAN-NEXT: EMIT store ir<1>, ir<%gep.a>, vp<[[C0_OR_C1]]> (!vplan.execution.frequency 9223372032559808512 (100%))
; VPLAN-NEXT: Successor(s): default
@@ -563,7 +563,7 @@ define void @switch_common_dest_almost_never_taken(ptr noalias %a, ptr noalias %
; VPLAN-NEXT: EMIT vp<[[OR_1:%.+]]> = or vp<[[OR_0]]>, vp<[[C3]]>
; VPLAN-NEXT: EMIT vp<[[ANY:%.+]]> = or vp<[[OR_1]]>, vp<[[C4]]>
; VPLAN-NEXT: EMIT vp<[[MASK:%.+]]> = logical-and ir<%c>, vp<[[ANY]]>
-; VPLAN-NEXT: EMIT vp<[[NOT_MASK:%.+]]> = not vp<[[MASK]]>
+; VPLAN-NEXT: EMIT vp<[[NOT_MASK:%.+]]> = xor vp<[[MASK]]>, ir<true>
; VPLAN-NEXT: EMIT vp<[[DEFAULT:%.+]]> = logical-and ir<%c>, vp<[[NOT_MASK]]>
; VPLAN-NEXT: EMIT ir<%gep.a> = getelementptr inbounds ir<%a>, ir<%iv>
; VPLAN-NEXT: EMIT store ir<1>, ir<%gep.a>, vp<[[MASK]]> (!vplan.execution.frequency 3435973836 (3.725e-08%))
@@ -640,7 +640,7 @@ define void @switch_common_dest_many_edges_almost_never_taken(ptr noalias %a, pt
; VPLAN-EMPTY:
; VPLAN-NEXT: if.then:
; VPLAN: EMIT vp<[[MASK:%.+]]> = logical-and ir<%c>, vp<%{{.+}}>
-; VPLAN-NEXT: EMIT vp<[[NOT_MASK:%.+]]> = not vp<[[MASK]]>
+; VPLAN-NEXT: EMIT vp<[[NOT_MASK:%.+]]> = xor vp<[[MASK]]>, ir<true>
; VPLAN-NEXT: EMIT vp<[[DEFAULT:%.+]]> = logical-and ir<%c>, vp<[[NOT_MASK]]>
; VPLAN-NEXT: EMIT ir<%gep.a> = getelementptr inbounds ir<%a>, ir<%iv>
; VPLAN-NEXT: EMIT store ir<1>, ir<%gep.a>, vp<[[MASK]]> (!vplan.execution.frequency 3817748708 (4.139e-08%))
@@ -722,7 +722,7 @@ define void @switch_common_dest_weight_sum_exceeds_32_bits(ptr noalias %a, ptr n
; VPLAN-NEXT: EMIT vp<[[OR1:%.+]]> = or vp<[[OR0]]>, vp<[[C2]]>
; VPLAN-NEXT: EMIT vp<[[OR2:%.+]]> = or vp<[[OR1]]>, vp<[[C3]]>
; VPLAN-NEXT: EMIT vp<[[MASK:%.+]]> = or vp<[[OR2]]>, vp<[[C4]]>
-; VPLAN-NEXT: EMIT vp<{{.+}}> = not vp<[[MASK]]>
+; VPLAN-NEXT: EMIT vp<{{.+}}> = xor vp<[[MASK]]>, ir<true>
; VPLAN-NEXT: EMIT ir<%gep.a> = getelementptr inbounds ir<%a>, ir<%iv>
; VPLAN-NEXT: EMIT store ir<1>, ir<%gep.a>, vp<[[MASK]]> (!vplan.execution.frequency 9223372023969873920 (100%))
; VPLAN-NEXT: Successor(s): latch
@@ -855,7 +855,7 @@ define void @switch_weights_clamped_at_both_ends(ptr noalias %a, ptr noalias %b,
;
; VPLAN-LABEL: VPlan for loop in 'switch_weights_clamped_at_both_ends'
; VPLAN: if.then:
-; VPLAN: EMIT vp<[[DEFAULT:%.+]]> = not vp<[[MASK:%.+]]>
+; VPLAN: EMIT vp<[[DEFAULT:%.+]]> = xor vp<[[MASK:%.+]]>, ir<true>
; VPLAN-NEXT: EMIT ir<%gep.a> = getelementptr inbounds ir<%a>, ir<%iv>
; VPLAN-NEXT: EMIT store ir<1>, ir<%gep.a>, vp<[[MASK]]> (!vplan.execution.frequency 9223372032559808512 (100%))
; VPLAN-NEXT: Successor(s): default
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll b/llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll
index 483ab8ad94b50..d026b8fecb95e 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll
@@ -13,7 +13,7 @@ define void @diamond_phi(ptr %a) {
; CHECK-NEXT: Successor(s): bb2
; CHECK-EMPTY:
; CHECK-NEXT: bb2:
-; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = not ir<%c0>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = xor ir<%c0>, ir<true>
; CHECK-NEXT: EMIT ir<%add2> = add ir<%iv>, ir<2>, vp<[[VP4]]>
; CHECK-NEXT: Successor(s): bb1
; CHECK-EMPTY:
@@ -88,14 +88,14 @@ define void @mask_reuse(ptr %a) {
; CHECK-NEXT: Successor(s): bb3
; CHECK-EMPTY:
; CHECK-NEXT: bb3:
-; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = not ir<%c1>
+; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = xor ir<%c1>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = logical-and ir<%c0>, vp<[[VP5]]>
; CHECK-NEXT: BLEND ir<%phi3> = ir<%add2>/vp<[[VP4]]> ir<%add1>/vp<[[VP6]]>
; CHECK-NEXT: EMIT ir<%add3> = add ir<%phi3>, ir<3>, ir<%c0>
; CHECK-NEXT: Successor(s): bb4
; CHECK-EMPTY:
; CHECK-NEXT: bb4:
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = not ir<%c0>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = xor ir<%c0>, ir<true>
; CHECK-NEXT: BLEND ir<%phi4> = ir<%add3>/ir<%c0> ir<%iv>/vp<[[VP7]]>
; CHECK-NEXT: EMIT store ir<%phi4>, ir<%gep>
; CHECK-NEXT: EMIT ir<%iv.next> = add nuw nsw ir<%iv>, ir<1>
@@ -163,7 +163,7 @@ define void @optimized_mask(ptr %a) {
; CHECK-NEXT: Successor(s): bb6
; CHECK-EMPTY:
; CHECK-NEXT: bb6:
-; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = not ir<%c0>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = xor ir<%c0>, ir<true>
; CHECK-NEXT: EMIT ir<%add6> = add ir<%iv>, ir<6>, vp<[[VP4]]>
; CHECK-NEXT: EMIT ir<%c6> = icmp sle ir<%iv>, ir<6>, vp<[[VP4]]>
; CHECK-NEXT: Successor(s): bb1
@@ -173,7 +173,7 @@ define void @optimized_mask(ptr %a) {
; CHECK-NEXT: Successor(s): bb3
; CHECK-EMPTY:
; CHECK-NEXT: bb3:
-; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = not ir<%c1>
+; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = xor ir<%c1>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = logical-and ir<%c0>, vp<[[VP5]]>
; CHECK-NEXT: EMIT ir<%add3> = add ir<%iv>, ir<3>, vp<[[VP6]]>
; CHECK-NEXT: EMIT ir<%c3> = icmp sle ir<%iv>, ir<3>, vp<[[VP6]]>
@@ -194,7 +194,7 @@ define void @optimized_mask(ptr %a) {
; CHECK-NEXT: bb5:
; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = logical-and vp<[[VP4]]>, ir<%c6>
; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = or vp<[[VP10]]>, vp<[[VP9]]>
-; CHECK-NEXT: EMIT vp<[[VP12:%[0-9]+]]> = not ir<%c3>
+; CHECK-NEXT: EMIT vp<[[VP12:%[0-9]+]]> = xor ir<%c3>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP13:%[0-9]+]]> = logical-and vp<[[VP6]]>, vp<[[VP12]]>
; CHECK-NEXT: EMIT vp<[[VP14:%[0-9]+]]> = or vp<[[VP11]]>, vp<[[VP13]]>
; CHECK-NEXT: BLEND ir<%phi5> = ir<%add6>/vp<[[VP10]]> ir<%add4>/vp<[[VP9]]> ir<%add3>/vp<[[VP13]]>
@@ -202,7 +202,7 @@ define void @optimized_mask(ptr %a) {
; CHECK-NEXT: Successor(s): bb7
; CHECK-EMPTY:
; CHECK-NEXT: bb7:
-; CHECK-NEXT: EMIT vp<[[VP15:%[0-9]+]]> = not ir<%c6>
+; CHECK-NEXT: EMIT vp<[[VP15:%[0-9]+]]> = xor ir<%c6>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP16:%[0-9]+]]> = logical-and vp<[[VP4]]>, vp<[[VP15]]>
; CHECK-NEXT: BLEND ir<%phi7> = ir<%add6>/vp<[[VP16]]> ir<%add5>/vp<[[VP14]]>
; CHECK-NEXT: EMIT store ir<%phi7>, ir<%gep>
@@ -288,7 +288,7 @@ define void @switch(ptr %a) {
; CHECK-NEXT: Successor(s): bb2
; CHECK-EMPTY:
; CHECK-NEXT: bb2:
-; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = not ir<%c0>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = xor ir<%c0>, ir<true>
; CHECK-NEXT: EMIT ir<%add2> = add ir<%iv>, ir<2>, vp<[[VP4]]>
; CHECK-NEXT: EMIT ir<%c2> = icmp sle ir<%iv>, ir<2>, vp<[[VP4]]>
; CHECK-NEXT: Successor(s): bb1
@@ -306,7 +306,7 @@ define void @switch(ptr %a) {
; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = or vp<[[VP7]]>, vp<[[VP8]]>
; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = logical-and ir<%c0>, vp<[[VP10]]>
; CHECK-NEXT: EMIT vp<[[VP12:%[0-9]+]]> = or vp<[[VP9]]>, vp<[[VP11]]>
-; CHECK-NEXT: EMIT vp<[[VP13:%[0-9]+]]> = not vp<[[VP12]]>
+; CHECK-NEXT: EMIT vp<[[VP13:%[0-9]+]]> = xor vp<[[VP12]]>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP14:%[0-9]+]]> = logical-and ir<%c0>, vp<[[VP13]]>
; CHECK-NEXT: EMIT vp<[[VP15:%[0-9]+]]> = or vp<[[VP5]]>, vp<[[VP11]]>
; CHECK-NEXT: BLEND ir<%phi3> = ir<%add2>/vp<[[VP5]]> ir<%add1>/vp<[[VP11]]>
@@ -318,7 +318,7 @@ define void @switch(ptr %a) {
; CHECK-NEXT: Successor(s): bb5
; CHECK-EMPTY:
; CHECK-NEXT: bb5:
-; CHECK-NEXT: EMIT vp<[[VP16:%[0-9]+]]> = not ir<%c2>
+; CHECK-NEXT: EMIT vp<[[VP16:%[0-9]+]]> = xor ir<%c2>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP17:%[0-9]+]]> = logical-and vp<[[VP4]]>, vp<[[VP16]]>
; CHECK-NEXT: BLEND ir<%phi5> = ir<%add4>/vp<[[VP9]]> ir<%add3>/vp<[[VP15]]> ir<%add2>/vp<[[VP17]]> ir<%add1>/vp<[[VP14]]>
; CHECK-NEXT: EMIT store ir<%phi5>, ir<%gep>
@@ -404,7 +404,7 @@ define void @diamond_phi2(ptr %a, i1 %c1, i1 %c2) {
; CHECK-NEXT: Successor(s): bb2
; CHECK-EMPTY:
; CHECK-NEXT: bb2:
-; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = not ir<%c0>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = xor ir<%c0>, ir<true>
; CHECK-NEXT: EMIT ir<%add2> = add ir<%iv>, ir<2>, vp<[[VP4]]>
; CHECK-NEXT: Successor(s): bb1
; CHECK-EMPTY:
@@ -486,19 +486,19 @@ define void @blend_masks(ptr noalias %p, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4)
; CHECK-NEXT: Successor(s): bb2
; CHECK-EMPTY:
; CHECK-NEXT: bb2:
-; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = not ir<%c0>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = xor ir<%c0>, ir<true>
; CHECK-NEXT: Successor(s): bb1
; CHECK-EMPTY:
; CHECK-NEXT: bb1:
; CHECK-NEXT: Successor(s): bb4
; CHECK-EMPTY:
; CHECK-NEXT: bb4:
-; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = not ir<%c1>
+; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = xor ir<%c1>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = logical-and ir<%c0>, vp<[[VP5]]>
; CHECK-NEXT: Successor(s): bb6
; CHECK-EMPTY:
; CHECK-NEXT: bb6:
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = not ir<%c3>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = xor ir<%c3>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = logical-and vp<[[VP6]]>, vp<[[VP7]]>
; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = or vp<[[VP8]]>, vp<[[VP4]]>
; CHECK-NEXT: Successor(s): bb3
@@ -509,7 +509,7 @@ define void @blend_masks(ptr noalias %p, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4)
; CHECK-EMPTY:
; CHECK-NEXT: bb5:
; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = logical-and vp<[[VP6]]>, ir<%c3>
-; CHECK-NEXT: EMIT vp<[[VP12:%[0-9]+]]> = not ir<%c2>
+; CHECK-NEXT: EMIT vp<[[VP12:%[0-9]+]]> = xor ir<%c2>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP13:%[0-9]+]]> = logical-and vp<[[VP10]]>, vp<[[VP12]]>
; CHECK-NEXT: EMIT vp<[[VP14:%[0-9]+]]> = or vp<[[VP11]]>, vp<[[VP13]]>
; CHECK-NEXT: Successor(s): bb7
@@ -595,9 +595,9 @@ define void @blend_masks_triangle_phi(ptr noalias %p, i1 %c0, i1 %c1) {
; CHECK-NEXT: Successor(s): bb2
; CHECK-EMPTY:
; CHECK-NEXT: bb2:
-; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = not ir<%c1>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = xor ir<%c1>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = logical-and ir<%c0>, vp<[[VP4]]>
-; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = not ir<%c0>
+; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = xor ir<%c0>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = or vp<[[VP5]]>, vp<[[VP6]]>
; CHECK-NEXT: Successor(s): bb3
; CHECK-EMPTY:
@@ -665,7 +665,7 @@ define void @blend_chain_non_trivial(ptr noalias %a, ptr noalias %b) {
; CHECK-NEXT: Successor(s): merge.a
; CHECK-EMPTY:
; CHECK-NEXT: merge.a:
-; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = not ir<%c0>
+; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = xor ir<%c0>, ir<true>
; CHECK-NEXT: BLEND ir<%blend.a> = ir<%v1>/ir<%c0> ir<%v1>/vp<[[VP5]]>
; CHECK-NEXT: EMIT ir<%d0> = icmp sgt ir<%iv>, ir<0>
; CHECK-NEXT: Successor(s): if.b
@@ -682,7 +682,7 @@ define void @blend_chain_non_trivial(ptr noalias %a, ptr noalias %b) {
; CHECK-NEXT: Successor(s): merge.b
; CHECK-EMPTY:
; CHECK-NEXT: merge.b:
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = not ir<%d0>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = xor ir<%d0>, ir<true>
; CHECK-NEXT: BLEND ir<%blend.b> = ir<%v2>/ir<%d0> ir<%v2>/vp<[[VP7]]>
; CHECK-NEXT: EMIT ir<%sum> = add ir<%blend.a>, ir<%blend.b>
; CHECK-NEXT: EMIT store ir<%sum>, ir<%gep>
@@ -761,11 +761,11 @@ define void @simplifiable_blend(i1 %c1, i1 %c2, i1 %c3, i32 %x, i32 %y, ptr %p)
; CHECK-NEXT: Successor(s): B
; CHECK-EMPTY:
; CHECK-NEXT: B:
-; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = not ir<%c1>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = xor ir<%c1>, ir<true>
; CHECK-NEXT: Successor(s): E
; CHECK-EMPTY:
; CHECK-NEXT: E:
-; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = not ir<%c3>
+; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = xor ir<%c3>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = logical-and vp<[[VP4]]>, vp<[[VP5]]>
; CHECK-NEXT: Successor(s): F
; CHECK-EMPTY:
@@ -776,7 +776,7 @@ define void @simplifiable_blend(i1 %c1, i1 %c2, i1 %c3, i32 %x, i32 %y, ptr %p)
; CHECK-NEXT: Successor(s): D
; CHECK-EMPTY:
; CHECK-NEXT: D:
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = not ir<%c2>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = xor ir<%c2>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = logical-and ir<%c1>, vp<[[VP7]]>
; CHECK-NEXT: Successor(s): C
; CHECK-EMPTY:
@@ -850,7 +850,7 @@ define void @phi_doesnt_postdom_incoming(i1 %c1, i1 %c2, i32 %x, i32 %y, ptr %p)
; CHECK-NEXT: Successor(s): B
; CHECK-EMPTY:
; CHECK-NEXT: B:
-; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = not ir<%c1>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = xor ir<%c1>, ir<true>
; CHECK-NEXT: Successor(s): A
; CHECK-EMPTY:
; CHECK-NEXT: A:
@@ -921,7 +921,7 @@ define void @phi_switch_same_edge(ptr %p) {
; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = icmp eq ir<%iv>, ir<0>
; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = icmp eq ir<%iv>, ir<1>
; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = or vp<[[VP4]]>, vp<[[VP5]]>
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = not vp<[[VP6]]>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = xor vp<[[VP6]]>, ir<true>
; CHECK-NEXT: EMIT ir<%gep> = getelementptr ir<%p>, ir<%iv>
; CHECK-NEXT: EMIT store ir<0>, ir<%gep>, vp<[[VP6]]>
; CHECK-NEXT: Successor(s): latch
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
index 818930cc93c8f..cb2d1814c9d3a 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
@@ -28,7 +28,7 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = icmp eq ir<%l>, ir<-12>
; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = icmp eq ir<%l>, ir<13>
; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = or vp<[[VP9]]>, vp<[[VP10]]>
-; CHECK-NEXT: EMIT vp<[[VP12:%[0-9]+]]> = not vp<[[VP11]]>
+; CHECK-NEXT: EMIT vp<[[VP12:%[0-9]+]]> = xor vp<[[VP11]]>, ir<true>
; CHECK-NEXT: EMIT vp<[[VP13:%[0-9]+]]> = extractelement vp<[[VP10]]>, ir<0>
; CHECK-NEXT: EMIT branch-on-cond vp<[[VP13]]>
; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-flags.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-flags.ll
index 30d916283d2be..dc235235fc02e 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-flags.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-flags.ll
@@ -25,7 +25,7 @@ define void @cast_flags_mixed(ptr noalias %A, ptr noalias %B) {
; CHECK-NEXT: EMIT store ir<0>, ir<%gep.trunc>
; CHECK-NEXT: EMIT ir<%iv.next> = add nsw ir<%iv>, ir<1>
; CHECK-NEXT: EMIT ir<%ec> = icmp slt ir<%iv.next>, ir<4>
-; CHECK-NEXT: EMIT vp<[[VP1:%[0-9]+]]> = not ir<%ec>
+; CHECK-NEXT: EMIT vp<[[VP1:%[0-9]+]]> = xor ir<%ec>, ir<true>
; CHECK-NEXT: EMIT branch-on-cond vp<[[VP1]]>
; CHECK-NEXT: Successor(s): middle.block, loop
; CHECK-EMPTY:
@@ -74,7 +74,7 @@ define void @cast_flags_single(ptr noalias %A, ptr noalias %B) {
; CHECK-NEXT: EMIT store ir<%zext.plain>, ir<%gep.b>
; CHECK-NEXT: EMIT ir<%iv.next> = add nsw ir<%iv>, ir<1>
; CHECK-NEXT: EMIT ir<%ec> = icmp slt ir<%iv.next>, ir<4>
-; CHECK-NEXT: EMIT vp<[[VP1:%[0-9]+]]> = not ir<%ec>
+; CHECK-NEXT: EMIT vp<[[VP1:%[0-9]+]]> = xor ir<%ec>, ir<true>
; CHECK-NEXT: EMIT branch-on-cond vp<[[VP1]]>
; CHECK-NEXT: Successor(s): middle.block, loop
; CHECK-EMPTY:
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
index bdc7b1f5d29bf..fd882208a39e7 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
@@ -390,7 +390,7 @@ define void @recipe_debug_loc_location(ptr nocapture %src) !dbg !5 {
; CHECK-NEXT: WIDEN ir<%lsd> = load vp<[[VP5]]>, !dbg /tmp/s.c:6:3
; CHECK-NEXT: WIDEN ir<%psd> = add nuw nsw ir<%lsd>, ir<23>, !dbg /tmp/s.c:7:3
; CHECK-NEXT: WIDEN ir<%cmp1> = icmp slt ir<%lsd>, ir<100>, !dbg /tmp/s.c:8:3
-; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = not ir<%cmp1>, !dbg /tmp/s.c:9:3
+; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = xor ir<%cmp1>, ir<true>, !dbg /tmp/s.c:9:3
; CHECK-NEXT: WIDEN ir<%cmp2> = icmp sge ir<%lsd>, ir<200>, !dbg /tmp/s.c:10:3
; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = logical-and vp<[[VP6]]>, ir<%cmp2>, !dbg /tmp/s.c:11:3
; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = or vp<[[VP7]]>, ir<%cmp1>
diff --git a/llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
index 84cc4631202cd..94f69c7867da4 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
@@ -201,7 +201,7 @@ define void @test_vpinstruction_switch_cost(ptr %start, ptr %end) {
; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP11:%[0-9]+]]> = icmp eq ir<%l>, ir<0>
; CHECK: Cost of 0 for VF 2: EMIT vp<[[VP12:%[0-9]+]]> = or vp<[[VP9]]>, vp<[[VP10]]>
; CHECK: Cost of 0 for VF 2: EMIT vp<[[VP13:%[0-9]+]]> = or vp<[[VP12]]>, vp<[[VP11]]>
-; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP14:%[0-9]+]]> = not vp<[[VP13]]>
+; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP14:%[0-9]+]]> = xor vp<[[VP13]]>, ir<true>
; CHECK: Cost of 0 for VF 2: vp<[[VP15:%[0-9]+]]> = vector-pointer i64, vp<%next.gep>, ir<1>
; CHECK: Cost of 1 for VF 2: WIDEN store vp<[[VP15]]>, ir<1>, vp<[[VP11]]>
; CHECK: Cost of 0 for VF 2: vp<[[VP16:%[0-9]+]]> = vector-pointer i64, vp<%next.gep>, ir<1>
@@ -233,7 +233,7 @@ define void @test_vpinstruction_switch_cost(ptr %start, ptr %end) {
; CHECK: Cost of 1 for VF 4: EMIT vp<[[VP11]]> = icmp eq ir<%l>, ir<0>
; CHECK: Cost of 0 for VF 4: EMIT vp<[[VP12]]> = or vp<[[VP9]]>, vp<[[VP10]]>
; CHECK: Cost of 0 for VF 4: EMIT vp<[[VP13]]> = or vp<[[VP12]]>, vp<[[VP11]]>
-; CHECK: Cost of 1 for VF 4: EMIT vp<[[VP14]]> = not vp<[[VP13]]>
+; CHECK: Cost of 1 for VF 4: EMIT vp<[[VP14]]> = xor vp<[[VP13]]>, ir<true>
; CHECK: Cost of 0 for VF 4: vp<[[VP15]]> = vector-pointer i64, vp<%next.gep>, ir<1>
; CHECK: Cost of 1 for VF 4: WIDEN store vp<[[VP15]]>, ir<1>, vp<[[VP11]]>
; CHECK: Cost of 0 for VF 4: vp<[[VP16]]> = vector-pointer i64, vp<%next.gep>, ir<1>
diff --git a/llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
index eaa9c978d6252..ad44c8cecc566 100644
--- a/llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
+++ b/llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
@@ -146,7 +146,7 @@ compound=true
" EMIT store ir\<%res\>, ir\<%arr.idx\>\l" +
" EMIT ir\<%indvars.iv.next\> = add ir\<%indvars.iv\>, ir\<1\>\l" +
" EMIT ir\<%exitcond\> = icmp ne ir\<%indvars.iv.next\>, ir\<%N\>\l" +
- " EMIT vp\<%3\> = not ir\<%exitcond\>\l" +
+ " EMIT vp\<%3\> = xor ir\<%exitcond\>, ir\<true\>\l" +
" EMIT vp\<%index.next\> = add nuw vp\<%2\>, vp\<%0\>\l" +
" EMIT branch-on-count vp\<%index.next\>, vp\<%1\>\l" +
"No successors\l"
@@ -322,7 +322,7 @@ compound=true
" EMIT store ir\<%res\>, ir\<%arr.idx\>\l" +
" EMIT ir\<%iv.next\> = add ir\<%iv\>, ir\<1\>\l" +
" EMIT ir\<%exitcond\> = icmp ne ir\<%iv.next\>, ir\<%N\>\l" +
- " EMIT vp\<%3\> = not ir\<%exitcond\>\l" +
+ " EMIT vp\<%3\> = xor ir\<%exitcond\>, ir\<true\>\l" +
" EMIT vp\<%index.next\> = add nuw vp\<%2\>, vp\<%0\>\l" +
" EMIT branch-on-count vp\<%index.next\>, vp\<%1\>\l" +
"No successors\l"
diff --git a/llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
index 7ce87be841c2d..a7e62663ac3ff 100644
--- a/llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
+++ b/llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
@@ -434,17 +434,17 @@ TEST_F(VPVerifierTest, DerivedIVWithStartInLoopRegions) {
VPBasicBlock *Entry = Plan.getEntry();
VPBasicBlock *Latch = Plan.createVPBasicBlock("latch");
+ VPRegionBlock *LoopR = Plan.createLoopRegion(I32Ty, DebugLoc::getUnknown(),
+ "loop", Latch, Latch);
+ VPBlockUtils::connectBlocks(Entry, LoopR);
+ VPBlockUtils::connectBlocks(LoopR, Plan.getScalarHeader());
+
VPBuilder Builder(Latch);
VPValue *Start = Builder.createNot(Plan.getPoison(I32Ty));
Builder.createDerivedIV(InductionDescriptor::IK_IntInduction, nullptr, Start,
Plan.getPoison(I32Ty), Plan.getPoison(I32Ty));
Builder.createNaryOp(VPInstruction::BranchOnCond, Plan.getTrue());
- VPRegionBlock *LoopR = Plan.createLoopRegion(I32Ty, DebugLoc::getUnknown(),
- "loop", Latch, Latch);
- VPBlockUtils::connectBlocks(Entry, LoopR);
- VPBlockUtils::connectBlocks(LoopR, Plan.getScalarHeader());
-
#if GTEST_HAS_STREAM_REDIRECTION
::testing::internal::CaptureStderr();
#endif
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