[llvm] d1c0cc5 - [AMDGPU] Do not freeze reserved registers in AMDGPUReserveWWMRegs (#222193)

[via llvm-commits]

Author: Michael Halkenhäuser
Date: 2026-09-09T02:58:14+02:00
New Revision: d1c0cc5e760f9cbb68e2acec80a476c4b8b898b7

URL: https://github.com/llvm/llvm-project/commit/d1c0cc5e760f9cbb68e2acec80a476c4b8b898b7
DIFF: https://github.com/llvm/llvm-project/commit/d1c0cc5e760f9cbb68e2acec80a476c4b8b898b7.diff

LOG: [AMDGPU] Do not freeze reserved registers in AMDGPUReserveWWMRegs (#222193)

Refreshing the shared RegisterClassInfo needs an up-to-date reserved set, but
freezing it into MachineRegisterInfo, as #221849 did, publishes it too early:
clearing the per-lane VGPR mask unreserves those registers, and LiveIntervals
does not extend a reserved register's unit ranges to its uses, so those uses
fail verification.

Take the set from TargetRegisterInfo instead. It is the same set, and the
register allocator still freezes it into MachineRegisterInfo itself.

AI-assisted.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
    llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp b/llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
index 54f637e589c87..421ce42b0ec66 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
@@ -108,7 +108,7 @@ bool AMDGPUReserveWWMRegs::run(MachineFunction &MF) {
   // The renamable flag can't be set for reserved registers. Reset the flag for
   // MOs involving wwm-regs as they will be reserved during vgpr-regalloc
   // pipeline.
-  MachineRegisterInfo &MRI = MF.getRegInfo();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
   for (Register Reg : MFI->getWWMReservedRegs()) {
     for (MachineOperand &MO : MRI.reg_operands(Reg))
       MO.setIsRenamable(false);
@@ -117,11 +117,14 @@ bool AMDGPUReserveWWMRegs::run(MachineFunction &MF) {
   // Now clear the PerLaneVGPRMask earlier set during wwm-regalloc.
   MFI->clearPerLaneVGPRAllocMask();
 
-  // Reserving WWM registers and clearing the per-lane mask both change
-  // getReservedRegs(). Update MRI and the shared RegisterClassInfo; the
-  // following register allocator refreshes only its private instance.
-  MRI.freezeReservedRegs();
-  RCI.updateReservedRegs(MRI.getReservedRegs());
+  // reserveWWMRegister() and clearPerLaneVGPRAllocMask() both feed
+  // getReservedRegs(): the WWM registers are now reserved, the per-lane VGPRs
+  // no longer are. Refresh the shared RegisterClassInfo, as the register
+  // allocator refreshes only its own copy. Do not freeze the set into MRI:
+  // LiveIntervals does not extend a reserved register's unit ranges to its
+  // uses, so unreserving the per-lane VGPRs here would fail verification.
+  const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
+  RCI.updateReservedRegs(TRI->getReservedRegs(MF));
 
   return Changed;
 }

diff  --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll b/llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
index 7d1ba484442ff..34260a0e7ea02 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgpu9.00 -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck -check-prefix=GCN %s
 
 ; Make sure there's no verifier error from improperly updated
 ; SlotIndexes if regalloc fast is manually used.