[llvm] [SystemZ][z/OS] Emit alignment in HLASM syntax (PR #222121)
Kai Nacke via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 8 12:53:42 PDT 2026
https://github.com/redstar created https://github.com/llvm/llvm-project/pull/222121
While trying to understand a crash, I noted that the emitted alignment in HLASM is wrong. There are 2 issues:
- The decision which suffix to use looks at `FillLen` instead of `Alignment`
- The label alignment `DS 0H` is hard-coded
This change fixes the issues. To get the correct suffix for the label alignment, the emission of the alignment is postponed in certain cases, and the label definition picks up the alignment suffix.
>From e4c2498f21907d6224d5b71c210d88fe38390d61 Mon Sep 17 00:00:00 2001
From: Kai Nacke <kai.peter.nacke at ibm.com>
Date: Tue, 8 Sep 2026 15:43:34 -0400
Subject: [PATCH] [SystemZ][z/OS] Emit alignment in HLASM syntax
While trying to understand a crash, I noted that the emitted alignment
in HLASM is wrong. There are 2 issues:
- The decision which suffix to use looks at `FillLen` instead of
`Alignment`
- The label alignment `DS 0H` is hard-coded
This change fixes the issues. To get the correct suffix for the
label alignment, the emission of the alignment is postponed in
certain cases, and the label definition picks up the alignment
suffix.
---
.../MCTargetDesc/SystemZHLASMAsmStreamer.cpp | 105 +++++++++++-------
.../MCTargetDesc/SystemZHLASMAsmStreamer.h | 6 +
llvm/test/CodeGen/SystemZ/call-zos-01.ll | 84 +++++++-------
llvm/test/CodeGen/SystemZ/call-zos-02.ll | 2 +-
llvm/test/CodeGen/SystemZ/call-zos-i128.ll | 4 +-
llvm/test/CodeGen/SystemZ/call-zos-vararg.ll | 90 +++++++--------
llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll | 34 +++---
.../CodeGen/SystemZ/zos-ada-relocations.ll | 4 +-
llvm/test/CodeGen/SystemZ/zos-ada.ll | 8 +-
llvm/test/CodeGen/SystemZ/zos-align.ll | 3 +-
llvm/test/CodeGen/SystemZ/zos-frameaddr.ll | 12 +-
llvm/test/CodeGen/SystemZ/zos-func-alias.ll | 4 +-
llvm/test/CodeGen/SystemZ/zos-hlasm-out.ll | 7 +-
llvm/test/CodeGen/SystemZ/zos-jumptable.ll | 6 +-
llvm/test/CodeGen/SystemZ/zos-landingpad.ll | 2 +-
.../CodeGen/SystemZ/zos-no-personality.ll | 4 +-
llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll | 22 ++--
llvm/test/CodeGen/SystemZ/zos-ppa1-name.ll | 10 +-
llvm/test/CodeGen/SystemZ/zos-ppa1.ll | 31 +++---
llvm/test/CodeGen/SystemZ/zos-ppa2.ll | 6 +-
.../CodeGen/SystemZ/zos-prologue-epilog.ll | 70 ++++++------
llvm/test/CodeGen/SystemZ/zos-ret-addr.ll | 6 +-
llvm/test/CodeGen/SystemZ/zos-simple-test.ll | 2 +-
.../CodeGen/SystemZ/zos-stack-protector.ll | 18 +--
llvm/test/CodeGen/SystemZ/zos-stackpointer.ll | 2 +-
llvm/test/CodeGen/SystemZ/zos-symbol-2.ll | 2 +-
.../SystemZ/zos-xplink64-bare-i32-arg.ll | 6 +-
27 files changed, 288 insertions(+), 262 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
index df1b45c381023..aca5a7398fa50 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
@@ -12,6 +12,7 @@
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCSectionGOFF.h"
#include "llvm/MC/MCSymbolGOFF.h"
+#include "llvm/Support/Alignment.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/Signals.h"
#include <sstream>
@@ -180,6 +181,7 @@ static void emitCATTR(raw_ostream &OS, StringRef Name, GOFF::ESDRmode Rmode,
void SystemZHLASMAsmStreamer::changeSection(MCSection *Section,
uint32_t Subsection) {
+ flushPendingAlignment();
auto &Sec = *static_cast<MCSectionGOFF *>(Section);
auto EmitExternalName = [&Sec, this]() {
if (Sec.hasExternalName())
@@ -243,37 +245,6 @@ void SystemZHLASMAsmStreamer::changeSection(MCSection *Section,
EmitEOL();
}
-void SystemZHLASMAsmStreamer::emitAlignmentDS(uint64_t ByteAlignment,
- std::optional<int64_t> Value,
- unsigned ValueSize,
- unsigned MaxBytesToEmit) {
- if (!isPowerOf2_64(ByteAlignment))
- report_fatal_error("Only power-of-two alignments are supported ");
-
- OS << " DS 0";
- switch (ValueSize) {
- default:
- llvm_unreachable("Invalid size for machine code value!");
- case 1:
- OS << "B";
- break;
- case 2:
- OS << "H";
- break;
- case 4:
- OS << "F";
- break;
- case 8:
- OS << "D";
- break;
- case 16:
- OS << "Q";
- break;
- }
-
- EmitEOL();
-}
-
void SystemZHLASMAsmStreamer::emitRawComment(const Twine &T, bool TabPrefix) {
OS << MAI->getCommentString() << T;
EmitEOL();
@@ -310,22 +281,69 @@ void SystemZHLASMAsmStreamer::EmitComment() {
CommentToEmit.clear();
}
+void SystemZHLASMAsmStreamer::flushPendingAlignment() {
+ if (!PendingAlignSuffix)
+ return;
+ OS << " DS 0" << *PendingAlignSuffix;
+ EmitEOL();
+ PendingAlignSuffix.reset();
+}
+
void SystemZHLASMAsmStreamer::emitValueToAlignment(Align Alignment,
int64_t Fill,
uint8_t FillLen,
unsigned MaxBytesToEmit) {
- emitAlignmentDS(Alignment.value(), Fill, FillLen, MaxBytesToEmit);
+ unsigned int A = Log2(Alignment);
+ if (A > 12)
+ return getContext().reportError(SMLoc(), "Alignment > 4096 not supported");
+ if (FillLen > 1)
+ return getContext().reportError(SMLoc(), "Fill length > 1 not supported");
+ if (Fill == 0 && A < 5) {
+ // Simple form: defer so the next emitLabel() can absorb it (e.g. "foo DS
+ // 0H" instead of a standalone "DS 0H" followed by "foo DS 0B").
+ flushPendingAlignment();
+ static const char SUFFIX[5] = {'B', 'H', 'F', 'D', 'Q'};
+ PendingAlignSuffix = SUFFIX[A];
+ } else if (A) {
+ // Non-simple form with a fill value. The HLASM DC duplication factor must
+ // be an absolute expression, so we cannot use the location counter (*)
+ // directly — it is a relocatable term. We also cannot use & as a bitwise
+ // AND operator, as ordinary HLASM expressions only support +, -, *, /.
+ //
+ // The solution is to introduce a temporary EQU symbol P defined as
+ // (*-SECTION), which is the difference of two co-relocatable terms and
+ // therefore absolute. With that absolute offset P and boundary B the
+ // padding count is:
+ //
+ // B - (P - ((P-1)/B)*B)
+ //
+ // which is the integer-division modulo idiom. The (P-1) bias ensures the
+ // count is 0 (not B) when already aligned.
+ unsigned int B = 1 << A;
+ // Retrieve the section name as the relocatable anchor (&POINT equivalent).
+ StringRef Anchor =
+ getCurrentSectionOnly()->getBeginSymbol()
+ ? getCurrentSectionOnly()->getBeginSymbol()->getName()
+ : static_cast<MCSectionGOFF *>(getCurrentSectionOnly())->getName();
+ // Emit the temporary EQU (P = *-Anchor) on its own line.
+ MCSymbol *Pad = getContext().createNamedTempSymbol("PAD");
+ MCStreamer::emitLabel(Pad);
+ StringRef PSym = Pad->getName();
+ OS << PSym << " EQU *-" << Anchor;
+ EmitEOL();
+ // Emit the DC with the fill value and computed duplication factor.
+ OS << " DC (" << B << "-(" << PSym << "-((" << PSym << "-1)/" << B << ")*"
+ << B << "))";
+ // Append the fill constant operand: XL1'xx'.
+ OS << "XL1'" << utohexstr(Fill, /*LowerCase=*/false, 2) << "'";
+ EmitEOL();
+ }
}
void SystemZHLASMAsmStreamer::emitCodeAlignment(Align Alignment,
const MCSubtargetInfo &STI,
unsigned MaxBytesToEmit) {
- // Emit with a text fill value.
- if (MAI->getTextAlignFillValue())
- emitAlignmentDS(Alignment.value(), MAI->getTextAlignFillValue(), 1,
- MaxBytesToEmit);
- else
- emitAlignmentDS(Alignment.value(), std::nullopt, 1, MaxBytesToEmit);
+ emitValueToAlignment(Alignment, 0, 1, MaxBytesToEmit);
}
void SystemZHLASMAsmStreamer::emitBytes(StringRef Data) {
@@ -333,7 +351,7 @@ void SystemZHLASMAsmStreamer::emitBytes(StringRef Data) {
"Cannot emit contents before setting section!");
if (Data.empty())
return;
-
+ flushPendingAlignment();
OS << " DC ";
size_t Len = Data.size();
SmallVector<uint8_t> Chars;
@@ -445,6 +463,7 @@ void SystemZHLASMAsmStreamer::addEncodingComment(const MCInst &Inst,
void SystemZHLASMAsmStreamer::emitInstruction(const MCInst &Inst,
const MCSubtargetInfo &STI) {
+ flushPendingAlignment();
// Show the encoding in a comment if we have a code emitter.
addEncodingComment(Inst, STI);
EmitEOL();
@@ -479,7 +498,9 @@ void SystemZHLASMAsmStreamer::emitLabel(MCSymbol *Symbol, SMLoc Loc) {
}
if (EmitLabelAndEntry) {
- OS << Sym->getName() << " DS 0H";
+ char Suffix = PendingAlignSuffix.value_or('B');
+ PendingAlignSuffix.reset();
+ OS << Sym->getName() << " DS 0" << Suffix;
EmitEOL();
}
}
@@ -502,6 +523,7 @@ void SystemZHLASMAsmStreamer::emitCommonSymbol(MCSymbol *S, uint64_t Size,
}
void SystemZHLASMAsmStreamer::emitRawTextImpl(StringRef String) {
+ flushPendingAlignment();
String.consume_back("\n");
OS << String;
EmitEOL();
@@ -581,7 +603,7 @@ void SystemZHLASMAsmStreamer::emitValueImpl(const MCExpr *Value, unsigned Size,
assert(Size <= 8 && "Invalid size");
assert(getCurrentSectionOnly() &&
"Cannot emit contents before setting section!");
-
+ flushPendingAlignment();
MCStreamer::emitValueImpl(Value, Size, Loc);
OS << " DC ";
emitHLASMValueImpl(Value, Size, true);
@@ -589,6 +611,7 @@ void SystemZHLASMAsmStreamer::emitValueImpl(const MCExpr *Value, unsigned Size,
}
void SystemZHLASMAsmStreamer::finishImpl() {
+ flushPendingAlignment();
for (auto &Symbol : getAssembler().symbols()) {
if (Symbol.isTemporary() || !Symbol.isRegistered() || Symbol.isDefined())
continue;
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.h
index 70f8fb0aede70..8a35771d8dae3 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.h
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.h
@@ -43,6 +43,11 @@ class SystemZHLASMAsmStreamer final : public MCAsmBaseStreamer {
const MCAsmInfo *MAI;
std::unique_ptr<MCInstPrinter> InstPrinter;
bool IsVerboseAsm = false;
+ // Deferred simple alignment suffix (e.g. 'H' for DS 0H). Set by
+ // emitValueToAlignment() and consumed by the next emitLabel() call.
+ // Flushed as a standalone DS statement by flushPendingAlignment() if any
+ // other emission follows first.
+ std::optional<char> PendingAlignSuffix;
public:
SystemZHLASMAsmStreamer(MCContext &Context,
@@ -65,6 +70,7 @@ class SystemZHLASMAsmStreamer final : public MCAsmBaseStreamer {
void EmitEOL();
void EmitComment();
+ void flushPendingAlignment();
/// Add a comment that can be emitted to the generated .s file to make the
/// output of the compiler more readable. This only affects the MCAsmStreamer
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-01.ll b/llvm/test/CodeGen/SystemZ/call-zos-01.ll
index a6006035dcaa1..fa39d8b1c7e98 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-01.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-01.ll
@@ -3,12 +3,12 @@
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
define i8 @call_char(){
-; CHECK-LABEL: call_char DS 0H
+; CHECK-LABEL: call_char DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,8(5)
; CHECK-NEXT: lg 5,0(5)
; CHECK-NEXT: lghi 1,8
@@ -22,12 +22,12 @@ define i8 @call_char(){
}
define i16 @call_short() {
-; CHECK-LABEL: call_short DS 0H
+; CHECK-LABEL: call_short DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,24(5)
; CHECK-NEXT: lg 5,16(5)
; CHECK-NEXT: lghi 1,16
@@ -42,12 +42,12 @@ entry:
}
define i32 @call_int() {
-; CHECK-LABEL: call_int DS 0H
+; CHECK-LABEL: call_int DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,40(5)
; CHECK-NEXT: lg 5,32(5)
; CHECK-NEXT: lghi 1,32
@@ -63,12 +63,12 @@ entry:
}
define i64 @call_long() {
-; CHECK-LABEL: call_long DS 0H
+; CHECK-LABEL: call_long DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,56(5)
; CHECK-NEXT: lg 5,48(5)
; CHECK-NEXT: lghi 1,64
@@ -85,12 +85,12 @@ entry:
}
define i32 @call_ptr(ptr %p1, ptr %p2) {
-; CHECK-LABEL: call_ptr DS 0H
+; CHECK-LABEL: call_ptr DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,72(5)
; CHECK-NEXT: lg 5,64(5)
; CHECK-NEXT: lgr 1,2
@@ -105,12 +105,12 @@ entry:
}
define i64 @call_integrals() {
-; CHECK-LABEL: call_integrals DS 0H
+; CHECK-LABEL: call_integrals DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,88(5)
; CHECK-NEXT: lg 5,80(5)
; CHECK-NEXT: lghi 1,64
@@ -128,7 +128,7 @@ entry:
}
define signext i8 @pass_char(i8 signext %arg) {
-; CHECK-LABEL: pass_char DS 0H
+; CHECK-LABEL: pass_char DS 0B
; CHECK: lgr 3,1
; CHECK-NEXT: b 2(7)
entry:
@@ -136,7 +136,7 @@ entry:
}
define signext i16 @pass_short(i16 signext %arg) {
-; CHECK-LABEL: pass_short DS 0H
+; CHECK-LABEL: pass_short DS 0B
; CHECK: lgr 3,1
; CHECK-NEXT: b 2(7)
entry:
@@ -144,7 +144,7 @@ entry:
}
define signext i32 @pass_int(i32 signext %arg0, i32 signext %arg1) {
-; CHECK-LABEL: pass_int DS 0H
+; CHECK-LABEL: pass_int DS 0B
; CHECK: lgr 3,2
; CHECK-NEXT: b 2(7)
entry:
@@ -152,7 +152,7 @@ entry:
}
define signext i64 @pass_long(i64 signext %arg0, i64 signext %arg1, i64 signext %arg2) {
-; CHECK-LABEL: pass_long DS 0H
+; CHECK-LABEL: pass_long DS 0B
; CHECK: agr 1,2
; CHECK-NEXT: agr 3,1
; CHECK-NEXT: b 2(7)
@@ -163,7 +163,7 @@ entry:
}
define signext i64 @pass_integrals0(i64 signext %arg0, i32 signext %arg1, i16 signext %arg2, i64 signext %arg3) {
-; CHECK-LABEL: pass_integrals0 DS 0H
+; CHECK-LABEL: pass_integrals0 DS 0B
; CHECK: ag 2,2200(4)
; CHECK-NEXT: lgr 3,2
; CHECK-NEXT: b 2(7)
@@ -174,12 +174,12 @@ entry:
}
define float @call_float() {
-; CHECK-LABEL: call_float DS 0H
+; CHECK-LABEL: call_float DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,104(5)
; CHECK-NEXT: lg 5,96(5)
; CHECK-NEXT: larl 1,L#CPI11_0
@@ -195,12 +195,12 @@ entry:
}
define double @call_double() {
-; CHECK-LABEL: call_double DS 0H
+; CHECK-LABEL: call_double DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,120(5)
; CHECK-NEXT: lg 5,112(5)
; CHECK-NEXT: larl 1,L#{{CPI[0-9]+_[0-9]+}}
@@ -216,12 +216,12 @@ entry:
}
define fp128 @call_longdouble() {
-; CHECK-LABEL: call_longdouble DS 0H
+; CHECK-LABEL: call_longdouble DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,136(5)
; CHECK-NEXT: lg 5,128(5)
; CHECK-NEXT: larl 1,L#{{CPI[0-9]+_[0-9]+}}
@@ -238,12 +238,12 @@ entry:
}
define i64 @call_floats0(fp128 %arg0, double %arg1) {
-; CHECK-LABEL: call_floats0 DS 0H
+; CHECK-LABEL: call_floats0 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,152(5)
; CHECK-NEXT: lg 5,144(5)
; CHECK-NEXT: larl 1,L#{{CPI[0-9]+_[0-9]+}}
@@ -264,12 +264,12 @@ entry:
}
define i64 @call_floats1(fp128 %arg0, double %arg1) {
-; CHECK-LABEL: call_floats1 DS 0H
+; CHECK-LABEL: call_floats1 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,168(5)
; CHECK-NEXT: lg 5,160(5)
; CHECK-NEXT: lxr 1,0
@@ -286,7 +286,7 @@ entry:
}
define float @pass_float(float %arg) {
-; CHECK-LABEL: pass_float DS 0H
+; CHECK-LABEL: pass_float DS 0B
; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
; CHECK-NEXT: aeb 0,0(1)
; CHECK-NEXT: b 2(7)
@@ -296,7 +296,7 @@ entry:
}
define double @pass_double(double %arg) {
-; CHECK-LABEL: pass_double DS 0H
+; CHECK-LABEL: pass_double DS 0B
; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
; CHECK-NEXT: adb 0,0(1)
; CHECK-NEXT: b 2(7)
@@ -306,7 +306,7 @@ entry:
}
define fp128 @pass_longdouble(fp128 %arg) {
-; CHECK-LABEL: pass_longdouble DS 0H
+; CHECK-LABEL: pass_longdouble DS 0B
; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
; CHECK-NEXT: lxdb 1,0(1)
; CHECK-NEXT: axbr 0,1
@@ -317,7 +317,7 @@ entry:
}
define i64 @pass_floats0(fp128 %arg0, fp128 %arg1, double %arg2) {
-; CHECK-LABEL: pass_floats0 DS 0H
+; CHECK-LABEL: pass_floats0 DS 0B
; CHECK: lxdb 1,2208(4)
; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
; CHECK-NEXT: ld 5,0(1)
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-02.ll b/llvm/test/CodeGen/SystemZ/call-zos-02.ll
index 7ddfda84ef4f6..ad9b7509136c0 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-02.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-02.ll
@@ -8,7 +8,7 @@ entry:
define hidden signext i32 @caller2() {
entry:
-; CHECK-LABEL: caller2 DS 0H
+; CHECK-LABEL: caller2 DS 0B
; CHECK: * encoding: [0xc0,0x75,A,A,A,A]
; CHECK-NEXT: * fixup A - offset: 2, value: caller+2, kind: FK_390_PC32DBL
; CHECK-NEXT: brasl 7,caller
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-i128.ll b/llvm/test/CodeGen/SystemZ/call-zos-i128.ll
index c12e26184f068..9cb5a16b66001 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-i128.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-i128.ll
@@ -2,7 +2,7 @@
;
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z13 | FileCheck %s
-; CHECK-LABEL: call_i128 DS 0H
+; CHECK-LABEL: call_i128 DS 0B
; CHECK-DAG: larl 1,L#CPI0_0
; CHECK-DAG: vl 0,0(1),3
; CHECK-DAG: vst 0,2256(4),3
@@ -19,7 +19,7 @@ entry:
ret i128 %retval
}
-; CHECK-LABEL: pass_i128 DS 0H
+; CHECK-LABEL: pass_i128 DS 0B
; CHECK: vl 0,0(3),3
; CHECK: vl 1,0(2),3
; CHECK: vaq 0,1,0
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
index 3bcc583adec7f..1b66440f9a546 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
@@ -1,12 +1,12 @@
; Test passing variable argument lists in 64-bit calls on z/OS.
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z14 | FileCheck %s -check-prefix=ARCH12
-; CHECK-LABEL: call_vararg_double0 DS 0H
+; CHECK-LABEL: call_vararg_double0 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,8(5)
; CHECK-NEXT: lg 5,0(5)
; CHECK-NEXT: llihf 3,1074118262
@@ -24,12 +24,12 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_double1 DS 0H
+; CHECK-LABEL: call_vararg_double1 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: llihf 0,1074118262
; CHECK-NEXT: oilf 0,3367254360
; CHECK-NEXT: lg 6,8(5)
@@ -50,12 +50,12 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_double2 DS 0H
+; CHECK-LABEL: call_vararg_double2 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,24(5)
; CHECK-NEXT: lg 5,16(5)
; CHECK-NEXT: llihf 2,1074118262
@@ -72,12 +72,12 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_double3 DS 0H
+; CHECK-LABEL: call_vararg_double3 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: llihf 0,1072703839
; CHECK-NEXT: oilf 0,2861204133
; CHECK-NEXT: lg 6,40(5)
@@ -101,12 +101,12 @@ entry:
}
;; TODO: The extra COPY after LGDR is unnecessary (machine-scheduler introduces the overlap).
-; CHECK-LABEL: call_vararg_both0 DS 0H
+; CHECK-LABEL: call_vararg_both0 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,40(5)
; CHECK-NEXT: lg 5,32(5)
; CHECK-NEXT: lgdr 0,0
@@ -122,12 +122,12 @@ define i64 @call_vararg_both0(i64 %arg0, double %arg1) {
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_long_double0 DS 0H
+; CHECK-LABEL: call_vararg_long_double0 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: larl 1,L#CPI5_0
; CHECK-NEXT: ld 0,0(1)
; CHECK-NEXT: ld 2,8(1)
@@ -149,12 +149,12 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_long_double1 DS 0H
+; CHECK-LABEL: call_vararg_long_double1 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,8(5)
; CHECK-NEXT: lg 5,0(5)
; CHECK-NEXT: lgdr 3,0
@@ -173,12 +173,12 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_long_double2 DS 0H
+; CHECK-LABEL: call_vararg_long_double2 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: std 4,2208(4)
; CHECK-NEXT: std 6,2216(4)
; CHECK-NEXT: lg 6,8(5)
@@ -199,12 +199,12 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_long_double3 DS 0H
+; CHECK-LABEL: call_vararg_long_double3 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,40(5)
; CHECK-NEXT: lg 5,32(5)
; CHECK-NEXT: lgdr 3,2
@@ -220,7 +220,7 @@ entry:
ret i64 %retval
}
-; ARCH12-LABEL: call_vec_vararg_test0 DS 0H
+; ARCH12-LABEL: call_vec_vararg_test0 DS 0B
; ARCH12: vlgvg 3,24,1
; ARCH12: vlgvg 2,24,0
; ARCH12: lghi 1,1
@@ -229,7 +229,7 @@ define void @call_vec_vararg_test0(<2 x double> %v) {
ret void
}
-; ARCH12-LABEL: call_vec_vararg_test1 DS 0H
+; ARCH12-LABEL: call_vec_vararg_test1 DS 0B
; ARCH12: larl 1,L#CPI10_0
; ARCH12: vl 0,0(1),3
; ARCH12: vlgvg 3,24,0
@@ -241,7 +241,7 @@ define void @call_vec_vararg_test1(<4 x i32> %v, <2 x i64> %w) {
ret void
}
-; ARCH12-LABEL: call_vec_char_vararg_straddle DS 0H
+; ARCH12-LABEL: call_vec_char_vararg_straddle DS 0B
; ARCH12: vlgvg 3,24,0
; ARCH12: lghi 1,1
; ARCH12: lghi 2,2
@@ -251,7 +251,7 @@ define void @call_vec_char_vararg_straddle(<16 x i8> %v) {
ret void
}
-; ARCH12-LABEL: call_vec_short_vararg_straddle DS 0H
+; ARCH12-LABEL: call_vec_short_vararg_straddle DS 0B
; ARCH12: vlgvg 3,24,0
; ARCH12: lghi 1,1
; ARCH12: lghi 2,2
@@ -261,7 +261,7 @@ define void @call_vec_short_vararg_straddle(<8 x i16> %v) {
ret void
}
-; ARCH12-LABEL: call_vec_int_vararg_straddle DS 0H
+; ARCH12-LABEL: call_vec_int_vararg_straddle DS 0B
; ARCH12: vlgvg 3,24,0
; ARCH12: lghi 1,1
; ARCH12: lghi 2,2
@@ -271,7 +271,7 @@ define void @call_vec_int_vararg_straddle(<4 x i32> %v) {
ret void
}
-; ARCH12-LABEL: call_vec_double_vararg_straddle DS 0H
+; ARCH12-LABEL: call_vec_double_vararg_straddle DS 0B
; ARCH12: vlgvg 3,24,0
; ARCH12: lghi 1,1
; ARCH12: lghi 2,2
@@ -281,12 +281,12 @@ define void @call_vec_double_vararg_straddle(<2 x double> %v) {
ret void
}
-; CHECK-LABEL: call_vararg_integral0 DS 0H
+; CHECK-LABEL: call_vararg_integral0 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 0,2392(4)
; CHECK-NEXT: lg 6,40(5)
; CHECK-NEXT: lg 5,32(5)
@@ -302,12 +302,12 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_float0 DS 0H
+; CHECK-LABEL: call_vararg_float0 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,24(5)
; CHECK-NEXT: lg 5,16(5)
; CHECK-NEXT: lghi 1,1
@@ -323,12 +323,12 @@ entry:
ret i64 %retval
}
-; CHECK-LABEL: call_vararg_float1 DS 0H
+; CHECK-LABEL: call_vararg_float1 DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lg 6,72(5)
; CHECK-NEXT: lg 5,64(5)
; CHECK-NEXT: larl 1,L#CPI17_0
@@ -360,14 +360,14 @@ entry:
; return ret;
; }
;
-; CHECK-LABEL: pass_vararg DS 0H
+; CHECK-LABEL: pass_vararg DS 0B
; CHECK: stmg 6,7,1904(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-160
; CHECK-NEXT: stg 2,2344(4)
; CHECK-NEXT: stg 3,2352(4)
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: la 0,2352(4)
; CHECK-NEXT: stg 0,2200(4)
; CHECK-NEXT: lg 3,2344(4)
diff --git a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
index cae54638c3191..1350550f49a9a 100644
--- a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
+++ b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
@@ -103,7 +103,7 @@ declare void @use_foo(ptr)
define void @ptr32_to_ptr(ptr %f, ptr addrspace(1) %i) {
entry:
-; CHECK-LABEL: ptr32_to_ptr DS 0H
+; CHECK-LABEL: ptr32_to_ptr DS 0B
; CHECK: llgtr 0,2
; CHECK-NEXT: stg 0,8(1)
%0 = addrspacecast ptr addrspace(1) %i to ptr
@@ -115,7 +115,7 @@ entry:
define void @ptr_to_ptr32(ptr %f, ptr %i) {
entry:
-; CHECK-LABEL: ptr_to_ptr32 DS 0H
+; CHECK-LABEL: ptr_to_ptr32 DS 0B
; CHECK: nilh 2,32767
; CHECK-NEXT: st 2,0(1)
%0 = addrspacecast ptr %i to ptr addrspace(1)
@@ -127,7 +127,7 @@ entry:
define void @ptr32_to_ptr32(ptr %f, ptr addrspace(1) %i) {
entry:
-; CHECK-LABEL: ptr32_to_ptr32 DS 0H
+; CHECK-LABEL: ptr32_to_ptr32 DS 0B
; CHECK: st 2,0(1)
%p32 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 0
store ptr addrspace(1) %i, ptr %p32, align 8
@@ -136,7 +136,7 @@ entry:
}
define void @ptr_to_ptr(ptr %f, ptr %i) {
-; CHECK-LABEL: ptr_to_ptr DS 0H
+; CHECK-LABEL: ptr_to_ptr DS 0B
; CHECK: stg 2,8(1)
%p64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 1
store ptr %i, ptr %p64, align 8
@@ -146,7 +146,7 @@ define void @ptr_to_ptr(ptr %f, ptr %i) {
define void @test_indexing(ptr %f) {
entry:
-; CHECK-LABEL: test_indexing DS 0H
+; CHECK-LABEL: test_indexing DS 0B
; CHECK: l 0,1032
; CHECK: llgtr 0,0
; CHECK: stg 0,16(1)
@@ -160,7 +160,7 @@ entry:
define void @test_indexing_2(ptr %f) {
entry:
-; CHECK-LABEL: test_indexing_2 DS 0H
+; CHECK-LABEL: test_indexing_2 DS 0B
; CHECK: lhi 0,16
; CHECK-NEXT: a 0,1032
; CHECK-NEXT: llgtr 2,0
@@ -181,7 +181,7 @@ entry:
define ptr @test_misc() {
entry:
-; CHECK-LABEL: test_misc DS 0H
+; CHECK-LABEL: test_misc DS 0B
; CHECK: lhi 0,88
; CHECK-NEXT: a 0,1208
; CHECK-NEXT: llgtr 1,0
@@ -204,7 +204,7 @@ entry:
define ptr addrspace(1) @test_misc_2() {
entry:
-; CHECK-LABEL: test_misc_2 DS 0H
+; CHECK-LABEL: test_misc_2 DS 0B
; CHECK: lhi 0,544
; CHECK: a 0,16
; CHECK: llgtr 1,0
@@ -221,7 +221,7 @@ entry:
define zeroext i16 @test_misc_3() {
entry:
-; CHECK-LABEL: test_misc_3 DS 0H
+; CHECK-LABEL: test_misc_3 DS 0B
; CHECK: a 0,548
; CHECK-NEXT: llgtr 1,0
; CHECK-NEXT: llgh 3,0(1)
@@ -235,7 +235,7 @@ entry:
define signext i32 @test_misc_4() {
entry:
-; CHECK-LABEL: test_misc_4 DS 0H
+; CHECK-LABEL: test_misc_4 DS 0B
; CHECK: lhi 0,88
; CHECK-NEXT: a 0,1208
; CHECK-NEXT: llgtr 1,0
@@ -261,7 +261,7 @@ entry:
define void @test_misc_5(ptr %f) {
entry:
-; CHECK-LABEL: test_misc_5 DS 0H
+; CHECK-LABEL: test_misc_5 DS 0B
; CHECK: l 0,548
; CHECK-NEXT: lg 6,8(5)
; CHECK-NEXT: lg 5,0(5)
@@ -277,7 +277,7 @@ entry:
define signext i32 @get_processor_count() {
entry:
-; CHECK-LABEL: get_processor_count DS 0H
+; CHECK-LABEL: get_processor_count DS 0B
; CHECK: lhi 0,660
; CHECK-NEXT: a 0,16
; CHECK-NEXT: llgtr 1,0
@@ -296,12 +296,12 @@ entry:
define void @spill_ptr32_args_to_registers(i8 addrspace(1)* %p) {
entry:
-; CHECK-LABEL: spill_ptr32_args_to_registers DS 0H
+; CHECK-LABEL: spill_ptr32_args_to_registers DS 0B
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update7 DS 0H
+; CHECK-NEXT: L#stack_update7 DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue7 DS 0H
+; CHECK-NEXT: L#end_of_prologue7 DS 0B
; CHECK-NEXT: lgr 2,1
; CHECK-NEXT: lg 6,24(5)
; CHECK-NEXT: lg 5,16(5)
@@ -330,7 +330,7 @@ declare void @g(i32 signext, ...)
; cast to __ptr32, setting the upper 32 bit to zero.
;
define signext i32 @setlength() {
-; CHECK-LABEL: setlength DS 0H
+; CHECK-LABEL: setlength DS 0B
; CHECK: basr 7,6
; CHECK: lgr [[MALLOC:[0-9]+]],3
; CHECK: basr 7,6
@@ -354,7 +354,7 @@ entry:
; the function now returns a __ptr32.
;
define signext i32 @setlength2() {
-; CHECK-LABEL: setlength2 DS 0H
+; CHECK-LABEL: setlength2 DS 0B
; CHECK: basr 7,6
; CHECK: lgr [[MALLOC:[0-9]+]],3
; CHECK: basr 7,6
diff --git a/llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll b/llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll
index a79e3b67ac3d1..f0baeea167e47 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll
@@ -2,7 +2,7 @@
;
; RUN: llc < %s -mtriple=s390x-ibm-zos | FileCheck %s
-; CHECK-LABEL: DoIt DS 0H
+; CHECK-LABEL: DoIt DS 0B
; CHECK: stmg 6,7,1840(4)
; CHECK: aghi 4,-224
; CHECK: lg 1,0(5)
@@ -25,7 +25,7 @@ entry:
declare void @DoFunc()
declare void @Caller(ptr noundef)
-; CHECK-LABEL: get_i DS 0H
+; CHECK-LABEL: get_i DS 0B
; CHECK: stmg 6,8,1872(4)
; CHECK: aghi 4,-192
; CHECK: lg 1,24(5)
diff --git a/llvm/test/CodeGen/SystemZ/zos-ada.ll b/llvm/test/CodeGen/SystemZ/zos-ada.ll
index fb99f318b57f9..bfab56a515d47 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ada.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ada.ll
@@ -3,12 +3,12 @@
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
define i64 @caller() {
-; CHECK-LABEL: caller DS 0H
+; CHECK-LABEL: caller DS 0B
; CHECK: stmg 6,8,1872(4)
-; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK-NEXT: lgr 8,5
; CHECK-NEXT: brasl 7,callee_internal
; CHECK-NEXT: bcr 0,3
@@ -28,7 +28,7 @@ define i64 @caller() {
}
define internal i64 @callee_internal() {
-; CHECK-LABEL: callee_internal DS 0H
+; CHECK-LABEL: callee_internal DS 0B
; CHECK: lghi 3,10
; CHECK-NEXT: b 2(7)
ret i64 10
diff --git a/llvm/test/CodeGen/SystemZ/zos-align.ll b/llvm/test/CodeGen/SystemZ/zos-align.ll
index 59827dec16079..57b404e1a3928 100644
--- a/llvm/test/CodeGen/SystemZ/zos-align.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-align.ll
@@ -9,7 +9,8 @@
; CHECK-NEXT: C_WSA64 CATTR ALIGN(12),FILL(0),DEFLOAD,NOTEXECUTABLE,RMODE(64),PART(dat
; CHECK-NEXT: ta)
; CHECK-NEXT: data XATTR LINKAGE(XPLINK),REFERENCE(DATA),SCOPE(EXPORT)
-; CHECK-NEXT: DS 0B
+; CHECK-NEXT: L#PAD0 EQU *-data
+; CHECK-NEXT: DC (4096-(L#PAD0-((L#PAD0-1)/4096)*4096))XL1'00'
; CHECK-NEXT: * 0x0
; CHECK-NEXT: DC XL4'00000000'
; CHECK-NEXT: * 0x1
diff --git a/llvm/test/CodeGen/SystemZ/zos-frameaddr.ll b/llvm/test/CodeGen/SystemZ/zos-frameaddr.ll
index 66177d56eb6d5..0c5c2b5352639 100644
--- a/llvm/test/CodeGen/SystemZ/zos-frameaddr.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-frameaddr.ll
@@ -4,7 +4,7 @@
; The current function's frame address is the address of
; the optional back chain slot.
define ptr @fp0() nounwind {
-; CHECK-LABEL: fp0 DS 0H
+; CHECK-LABEL: fp0 DS 0B
; CHECK: la 3,2048(4)
; CHECK-NEXT: b 2(7)
entry:
@@ -15,12 +15,12 @@ entry:
; Check that the frame address is correct in a presence
; of a stack frame.
define ptr @fp0f() nounwind {
-; CHECK-LABEL: fp0f DS 0H
+; CHECK-LABEL: fp0f DS 0B
; CHECK: stmg 6,7,1904(4)
-; CHECK-NEXT: L#stack_update0 DS 0H
+; CHECK-NEXT: L#stack_update0 DS 0B
; CHECK-NEXT: aghi 4,-160
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue0 DS 0H
+; CHECK-NEXT: L#end_of_prologue0 DS 0B
; CHECK-NEXT: la 3,2048(4)
; CHECK-NEXT: lg 7,2072(4)
; CHECK-NEXT: aghi 4,160
@@ -33,7 +33,7 @@ entry:
; Check the caller's frame address.
define ptr @fpcaller() nounwind "backchain" {
-; CHECK-LABEL: fpcaller DS 0H
+; CHECK-LABEL: fpcaller DS 0B
; CHECK: stmg 4,7,2048(4)
; CHECK-NEXT: lg 3,2048(4)
; CHECK-NEXT: lmg 4,7,2048(4)
@@ -45,7 +45,7 @@ entry:
; Check the caller's frame address.
define ptr @fpcallercaller() nounwind "backchain" {
-; CHECK-LABEL: fpcallercaller DS 0H
+; CHECK-LABEL: fpcallercaller DS 0B
; CHECK: stmg 4,7,2048(4)
; CHECK-NEXT: lg 1,2048(4)
; CHECK-NEXT: lg 3,0(1)
diff --git a/llvm/test/CodeGen/SystemZ/zos-func-alias.ll b/llvm/test/CodeGen/SystemZ/zos-func-alias.ll
index a0c4d3fdece2a..7b5f3a3ff28f5 100644
--- a/llvm/test/CodeGen/SystemZ/zos-func-alias.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-func-alias.ll
@@ -4,10 +4,10 @@
; CHECK: ENTRY foo
; CHECK-NEXT: foo XATTR LINKAGE(XPLINK),REFERENCE(CODE),PSECT(stdin#S),SCOPE(LIBRARY)
-; CHECK-NEXT: foo DS 0H
+; CHECK-NEXT: foo DS 0B
; CHECK-NEXT: ENTRY foo
; CHECK-NEXT: foo1 XATTR LINKAGE(XPLINK),REFERENCE(CODE),SCOPE(LIBRARY)
-; CHECK-NEXT: foo1 DS 0H
+; CHECK-NEXT: foo1 DS 0B
@foo1 = hidden alias i32 (i32), ptr @foo
diff --git a/llvm/test/CodeGen/SystemZ/zos-hlasm-out.ll b/llvm/test/CodeGen/SystemZ/zos-hlasm-out.ll
index 554c2388da631..bdf694d001e54 100644
--- a/llvm/test/CodeGen/SystemZ/zos-hlasm-out.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-hlasm-out.ll
@@ -8,7 +8,7 @@
; Function Attrs: noinline nounwind optnone
define void @foo() {
-; CHECK-LABEL: L#PPA2 DS 0H
+; CHECK-LABEL: L#PPA2 DS 0B
; CHECK: DC XL1'03'
; CHECK: DC XL1'E7'
; CHECK: DC XL1'22'
@@ -23,12 +23,11 @@ define void @foo() {
; CHECK-LABEL: L#.str DS 0H
; CHECK: DC XL10'48656C6C6F2025730A00'
; CHECK: Greeting XATTR LINKAGE(XPLINK),REFERENCE(DATA),SCOPE(EXPORT)
-; CHECK: DS 0B
+; CHECK: DS 0D
; CHECK: DC AD(L#.str)
-; CHECK: DS 0B
; CHECK-LABEL: L#.str.1 DS 0H
; CHECK: DC XL6'576F726C6400'
-; CHECK-LABEL: L#PPA1_foo_0 DS 0H
+; CHECK-LABEL: L#PPA1_foo_0 DS 0B
; CHECK: DC XL1'02'
; CHECK: DC XL1'CE'
; CHECK: DC XL2'0300'
diff --git a/llvm/test/CodeGen/SystemZ/zos-jumptable.ll b/llvm/test/CodeGen/SystemZ/zos-jumptable.ll
index 93aedcc39d97f..3e611a5233a04 100644
--- a/llvm/test/CodeGen/SystemZ/zos-jumptable.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-jumptable.ll
@@ -1,10 +1,10 @@
; RUN: llc -mtriple s390x-zos < %s | FileCheck %s
define void @jumptable(i32 signext %in, ptr %out) {
-; CHECK-LABEL: jumptable DS 0H
+; CHECK-LABEL: jumptable DS 0B
; CHECK: larl 3,L#JTI0_0
-; CHECK: L#jumptable_end_0 DS 0H
-; CHECK: L#JTI0_0 DS 0H
+; CHECK: L#jumptable_end_0 DS 0B
+; CHECK: L#JTI0_0 DS 0D
; CHECK: DC AD(L#BB0_2)
; CHECK: DC AD(L#BB0_5)
; CHECK: DC AD(L#BB0_3)
diff --git a/llvm/test/CodeGen/SystemZ/zos-landingpad.ll b/llvm/test/CodeGen/SystemZ/zos-landingpad.ll
index 3253376645eaa..c8a275215baa9 100644
--- a/llvm/test/CodeGen/SystemZ/zos-landingpad.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-landingpad.ll
@@ -19,7 +19,7 @@ done:
lpad:
%0 = landingpad { ptr, i32 } cleanup
; The Exception Pointer is %r1; the Exception Selector, %r2.
-; CHECK: L#BB{{[^%]*}} DS 0H
+; CHECK: L#BB{{[^%]*}} DS 0B
; CHECK-DAG: stg 1,{{.*}}
; CHECK-DAG: st 2,{{.*}}
%1 = extractvalue { ptr, i32 } %0, 0
diff --git a/llvm/test/CodeGen/SystemZ/zos-no-personality.ll b/llvm/test/CodeGen/SystemZ/zos-no-personality.ll
index d8212dc3c1e70..0ab42be8e92bc 100644
--- a/llvm/test/CodeGen/SystemZ/zos-no-personality.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-no-personality.ll
@@ -13,7 +13,7 @@ define { ptr, i32 } @foo() personality ptr null {
ret { ptr, i32 } %3
}
-; CHECK: foo DS 0H
+; CHECK: foo DS 0B
; CHECK-NOT: .gcc_exception_table.foo
-; CHECK: L#PPA1_foo_0 DS 0H
+; CHECK: L#PPA1_foo_0 DS 0B
; CHECK-NOT: * Bit 3: 1 = C++ EH block
diff --git a/llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll b/llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll
index 610c851798614..1f33352cd0c31 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll
@@ -6,21 +6,21 @@
; === Check that function with small frame does not emit PPA1 Argument Area Length.
define void @fSmallOutArgArea() {
-; CHECK-LABEL: L#EPM_fSmallOutArgArea_0 DS 0H
+; CHECK-LABEL: L#EPM_fSmallOutArgArea_0 DS 0Q
; CHECK: * Bit 1: 1 = Leaf function
; CHECK: * Bit 2: 0 = Does not use alloca
; CHECK: DC XL4'00000008'
-; CHECK: fSmallOutArgArea DS 0H
+; CHECK: fSmallOutArgArea DS 0B
ret void
}
; === Check that function with large frame does emit PPA1 Argument Area Length.
define void @fLargeOutArgArea() {
-; CHECK-LABEL: L#EPM_fLargeOutArgArea_0 DS 0H
+; CHECK-LABEL: L#EPM_fLargeOutArgArea_0 DS 0Q
; CHECK: * Bit 1: 0 = Non-leaf function
; CHECK: * Bit 2: 0 = Does not use alloca
; CHECK: DC XL4'00000220'
-; CHECK: fLargeOutArgArea DS 0H
+; CHECK: fLargeOutArgArea DS 0B
%1 = load [33 x i32], ptr @GlobLargeS, align 4
call void @fLargeParm([33 x i32] inreg %1)
ret void
@@ -28,7 +28,7 @@ define void @fLargeOutArgArea() {
; === Check that function with parameter does emit PPA1 Length/4 of parms
define void @fLargeParm([33 x i64] inreg %arr) {
-; CHECK-LABEL: L#EPM_fLargeParm_0 DS 0H
+; CHECK-LABEL: L#EPM_fLargeParm_0 DS 0Q
%1 = extractvalue [33 x i64] %arr, 1
call void @foo(i64 %1)
ret void
@@ -36,9 +36,9 @@ define void @fLargeParm([33 x i64] inreg %arr) {
; === Check that function with alloca call does emit PPA1 Argument Area Length.
define hidden void @fHasAlloca() {
-; CHECK-LABEL: L#EPM_fHasAlloca_0 DS 0H
+; CHECK-LABEL: L#EPM_fHasAlloca_0 DS 0Q
; CHECK: * Bit 2: 1 = Uses alloca
-; CHECK: fHasAlloca DS 0H
+; CHECK: fHasAlloca DS 0B
%p = alloca ptr, align 4
%1 = load i32, ptr @GlobInt, align 4
%2 = alloca i8, i32 %1, align 8
@@ -48,22 +48,22 @@ define hidden void @fHasAlloca() {
declare void @foo(i64)
-; CHECK-LABEL: L#PPA1_fSmallOutArgArea_0 DS 0H
+; CHECK-LABEL: L#PPA1_fSmallOutArgArea_0 DS 0B
; CHECK: * PPA1 Flags 3
; CHECK: DC XL1'00'
-; CHECK-LABEL: L#PPA1_fLargeOutArgArea_0 DS 0H
+; CHECK-LABEL: L#PPA1_fLargeOutArgArea_0 DS 0B
; CHECK: * PPA1 Flags 3
; CHECK: * Bit 1: 1 = Argument Area Length is in optional area
; CHECK: DC XL1'40'
; CHECK: * Argument Area Length
; CHECK: DC XL4'00000140'
-; CHECK-LABEL: L#PPA1_fLargeParm_0 DS 0H
+; CHECK-LABEL: L#PPA1_fLargeParm_0 DS 0B
; CHECK: * Length/4 of Parms
; CHECK: DC XL2'0042'
-; CHECK-LABEL: L#PPA1_fHasAlloca_0 DS 0H
+; CHECK-LABEL: L#PPA1_fHasAlloca_0 DS 0B
; CHECK: * PPA1 Flags 3
; CHECK: * Bit 1: 1 = Argument Area Length is in optional area
; CHECK: DC XL1'40'
diff --git a/llvm/test/CodeGen/SystemZ/zos-ppa1-name.ll b/llvm/test/CodeGen/SystemZ/zos-ppa1-name.ll
index aaecf5fc0ad05..2d5facd455bb8 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ppa1-name.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ppa1-name.ll
@@ -2,16 +2,16 @@
; This tests needs updating when the new external name is emitted into asm output.
-; CHECK: L#EPM_sourcename_0 DS 0H
+; CHECK: L#EPM_sourcename_0 DS 0Q
; CHECK-NEXT: DC XL7'00C300C500C500'
; CHECK-NEXT: DC XL1'F1'
; CHECK-NEXT: DC AD(L#PPA1_sourcename_0-L#EPM_sourcename_0)
; CHECK-NEXT: DC XL4'00000008'
; CHECK-NEXT: ENTRY sourcename
-; CHECK:sourcename DS 0H
+; CHECK:sourcename DS 0B
;CHECK-NEXT: b 2(7)
-;CHECK-NEXT: L#sourcename_end_0 DS 0H
-;CHECK-NEXT: L#func_end0 DS 0H
+;CHECK-NEXT: L#sourcename_end_0 DS 0B
+;CHECK-NEXT: L#func_end0 DS 0B
define void @sourcename() #0 {
entry:
@@ -19,7 +19,7 @@ entry:
}
attributes #0 = { "zos-ppa1-name"="name" }
-; CHECK:L#PPA1_sourcename_0 DS 0H
+; CHECK:L#PPA1_sourcename_0 DS 0B
; CHECK-NEXT: DC XL1'02'
; CHECK-NEXT: DC XL1'CE'
; CHECK-NEXT: DC XL2'0000'
diff --git a/llvm/test/CodeGen/SystemZ/zos-ppa1.ll b/llvm/test/CodeGen/SystemZ/zos-ppa1.ll
index 89a4f9db117fb..12a5cfa8b28e8 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ppa1.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ppa1.ll
@@ -1,10 +1,9 @@
; RUN: llc -mtriple s390x-ibm-zos < %s | FileCheck %s
define i32 @leaf(i32 signext %arg) {
-; CHECK: DS 0B
-; CHECK-NEXT: * @leaf
+; CHECK: * @leaf
; CHECK-NEXT: * XPLINK Routine Layout Entry
-; CHECK-NEXT: L#EPM_leaf_0 DS 0H
+; CHECK-NEXT: L#EPM_leaf_0 DS 0Q
; CHECK-NEXT: * Eyecatcher 0x00C300C500C500
; CHECK-NEXT: DC XL7'00C300C500C500'
; CHECK-NEXT: * Mark Type C'1'
@@ -27,10 +26,9 @@ entry:
}
define i32 @nonleaf(i32 signext %arg) {
-; CHECK: DS 0B
-; CHECK-NEXT: * @nonleaf
+; CHECK: * @nonleaf
; CHECK-NEXT: * XPLINK Routine Layout Entry
-; CHECK-NEXT: L#EPM_nonleaf_0 DS 0H
+; CHECK-NEXT: L#EPM_nonleaf_0 DS 0Q
; CHECK-NEXT: * Eyecatcher 0x00C300C500C500
; CHECK-NEXT: DC XL7'00C300C500C500'
; CHECK-NEXT: * Mark Type C'1'
@@ -45,20 +43,19 @@ define i32 @nonleaf(i32 signext %arg) {
; CHECK-NEXT: ENTRY nonleaf
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: L#stack_update0 DS 0H
+; CHECK-NEXT: L#stack_update0 DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue0 DS 0H
+; CHECK-NEXT: L#end_of_prologue0 DS 0B
entry:
%res = call i32 @leaf(i32 %arg)
ret i32 %res
}
define i32 @withalloca(i32 signext %arg) {
-; CHECK: DS 0B
-; CHECK-NEXT: * @withalloca
+; CHECK: * @withalloca
; CHECK-NEXT: * XPLINK Routine Layout Entry
-; CHECK-NEXT: L#EPM_withalloca_0 DS 0H
+; CHECK-NEXT: L#EPM_withalloca_0 DS 0Q
; CHECK-NEXT: * Eyecatcher 0x00C300C500C500
; CHECK-NEXT: DC XL7'00C300C500C500'
; CHECK-NEXT: * Mark Type C'1'
@@ -73,11 +70,11 @@ define i32 @withalloca(i32 signext %arg) {
; CHECK-NEXT: ENTRY withalloca
; CHECK: stmg 4,10,1856(4)
-; CHECK-NEXT: L#stack_update1 DS 0H
+; CHECK-NEXT: L#stack_update1 DS 0B
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: lgr 8,4
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: L#end_of_prologue1 DS 0H
+; CHECK-NEXT: L#end_of_prologue1 DS 0B
entry:
%p = alloca i8, i32 %arg
%res = call i32 @other(ptr %p, i32 %arg)
@@ -87,7 +84,7 @@ entry:
declare i32 @other(ptr, i32)
; CHECK: * PPA1
-; CHECK-NEXT: L#PPA1_leaf_0 DS 0H
+; CHECK-NEXT: L#PPA1_leaf_0 DS 0B
; CHECK-NEXT: * Version
; CHECK-NEXT: DC XL1'02'
; CHECK-NEXT: * LE Signature X'CE'
@@ -125,7 +122,7 @@ declare i32 @other(ptr, i32)
; CHECK-NEXT: DC AD(L#EPM_leaf_0-L#PPA1_leaf_0)
; CHECK-NEXT: * PPA1
-; CHECK-NEXT: L#PPA1_nonleaf_0 DS 0H
+; CHECK-NEXT: L#PPA1_nonleaf_0 DS 0B
; CHECK-NEXT: * Version
; CHECK-NEXT: DC XL1'02'
; CHECK-NEXT: * LE Signature X'CE'
@@ -165,7 +162,7 @@ declare i32 @other(ptr, i32)
; CHECK-NEXT: DC AD(L#EPM_nonleaf_0-L#PPA1_nonleaf_0)
; CHECK-NEXT: * PPA1
-; CHECK-NEXT: L#PPA1_withalloca_0 DS 0H
+; CHECK-NEXT: L#PPA1_withalloca_0 DS 0B
; CHECK-NEXT: * Version
; CHECK-NEXT: DC XL1'02'
; CHECK-NEXT: * LE Signature X'CE'
@@ -209,7 +206,7 @@ declare i32 @other(ptr, i32)
; Attribute "zos-ppa1-name"="" removes the function name from PPA1.
; CHECK: * PPA1
-; CHECK-NEXT: L#PPA1_no_name_0 DS 0H
+; CHECK-NEXT: L#PPA1_no_name_0 DS 0B
; CHECK: * PPA1 Flags 4
; CHECK-NEXT: DC XL1'80'
; CHECK-NEXT: * Length/4 of Parms
diff --git a/llvm/test/CodeGen/SystemZ/zos-ppa2.ll b/llvm/test/CodeGen/SystemZ/zos-ppa2.ll
index b1d8d47356b97..05ae4a9d0126d 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ppa2.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ppa2.ll
@@ -7,7 +7,7 @@
; RUN: FileCheck %t.ebcdic.ll
; CHECK: C_CODE64 CATTR
-; CHECK: L#PPA2 DS 0H
+; CHECK: L#PPA2 DS 0B
; CHECK: DC XL1'03'
; CHECK: DC XL1'E7'
; CHECK: DC XL1'22'
@@ -19,7 +19,7 @@
; CHECK: DC XL1'BYTE'
; CHECK: DC XL1'00'
; CHECK: DC XL2'0000'
-; CHECK: L#DVS DS 0H
+; CHECK: L#DVS DS 0B
; CHECK: DC XL14'F1F9F7F0F0F1F0F1F0F0F0F0F0F0'
; CHECK: DC XL6'{{((F[[:digit:]]){6})}}'
; CHECK: DC XL2'0000'
@@ -31,7 +31,7 @@
; CHECK: * A(PPA2-CELQSTRT)
; CHECK: DC AD(L#PPA2-CELQSTRT)
-; CHECK: L#EPM_void_test_0 DS 0H
+; CHECK: L#EPM_void_test_0 DS 0Q
; CHECK: * Offset to PPA1
; CHECK: DC AD(L#PPA1_void_test_0-L#EPM_void_test_0)
diff --git a/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll b/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
index 11be550e7bfd1..7919fc9cbcac8 100644
--- a/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
@@ -5,14 +5,14 @@
; Test prolog/epilog for non-XPLEAF.
; Small stack frame.
-; CHECK-LABEL: func0 DS 0H
+; CHECK-LABEL: func0 DS 0B
; CHECK64: stmg 6,7,1872(4)
; stmg instruction's displacement field must be 2064-dsa_size
; as per ABI
-; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64: L#stack_update{{[0-9]+}} DS 0B
; CHECK64-NEXT: aghi 4,-192
; CHECK64-NEXT: *FENCE
-; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK64: lg 7,2072(4)
; CHECK64: aghi 4,192
@@ -24,12 +24,12 @@ define void @func0() {
}
; Spill all GPR CSRs
-; CHECK-LABEL: func1 DS 0H
+; CHECK-LABEL: func1 DS 0B
; CHECK64: stmg 6,15,1904(4)
-; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64: L#stack_update{{[0-9]+}} DS 0B
; CHECK64-NEXT: aghi 4,-160
; CHECK64-NEXT: *FENCE
-; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK64: lmg 7,15,2072(4)
; CHECK64: aghi 4,160
@@ -86,12 +86,12 @@ define void @func1(ptr %ptr) {
; Spill all FPRs and VRs
-; CHECK-LABEL: func2 DS 0H
+; CHECK-LABEL: func2 DS 0B
; CHECK64: stmg 6,7,1744(4)
-; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64: L#stack_update{{[0-9]+}} DS 0B
; CHECK64-NEXT: aghi 4,-320
; CHECK64-NEXT: *FENCE
-; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK64: vst 16,{{[0-9]+}}(4),4
; CHECK64: vst 17,{{[0-9]+}}(4),4
; CHECK64: vst 18,{{[0-9]+}}(4),4
@@ -281,11 +281,11 @@ define void @func2(ptr %ptr, ptr %vec_ptr) {
; Big stack frame, force the use of agfi before stmg
; despite not requiring stack extension routine.
; CHECK-LABEL: func3
-; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64: L#stack_update{{[0-9]+}} DS 0B
; CHECK64-NEXT: agfi 4,-1040768
; CHECK64-NEXT: stmg 6,7,2064(4)
; CHECK64-NEXT: *FENCE
-; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK64: agfi 4,1040768
define void @func3() {
%arr = alloca [130070 x i64], align 8
@@ -297,11 +297,11 @@ define void @func3() {
; object in stack frame. (Eg: VLA) Sets up frame pointer in r8
; CHECK-LABEL: func4
; CHECK64: stmg 4,10,1856(4)
-; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64: L#stack_update{{[0-9]+}} DS 0B
; CHECK64-NEXT: aghi 4,-192
; CHECK64-NEXT: lgr 8,4
; CHECK64-NEXT: *FENCE
-; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK64: lmg 4,10,2048(4)
; CHECK64-NEXT: b 2(7)
define i64 @func4(i64 %n) {
@@ -314,13 +314,13 @@ define i64 @func4(i64 %n) {
; to force use of agfi before stmg.
; CHECK-LABEL: func5
; CHECK64: lgr 0,4
-; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64: L#stack_update{{[0-9]+}} DS 0B
; CHECK64-NEXT: agfi 4,-1040224
; CHECK64-NEXT: stmg 4,10,2048(4)
; CHECK64-NEXT: stg 0,2048(4)
; CHECK64-NEXT: lgr 8,4
; CHECK64-NEXT: *FENCE
-; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK64: lmg 4,10,2048(4)
define i64 @func5(i64 %n) {
%vla = alloca i64, i64 %n, align 8
@@ -331,10 +331,10 @@ define i64 @func5(i64 %n) {
; Require saving of r5, which is not restored.
; CHECK64: stmg 5,9,1864(4)
-; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64: L#stack_update{{[0-9]+}} DS 0B
; CHECK64-NEXT: aghi 4,-192
; CHECK64-NEXT: *FENCE
-; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
; CHECK64: lmg 7,9,2072(4)
; CHECK64-NEXT: aghi 4,192
declare i32 @personality(...)
@@ -354,7 +354,7 @@ bb3:
}
; CHECK-LABEL: large_stack
-; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64: L#stack_update{{[0-9]+}} DS 0B
; CHECK64-NEXT: agfi 4,-1048800
; CHECK64-NEXT: llgt 3,1208
; CHECK64-NEXT: cg 4,64(3)
@@ -362,18 +362,18 @@ bb3:
; CHECK64: lg 3,72(3)
; CHECK64-NEXT: basr 3,3
; CHECK64-NEXT: bcr 0,7
-; CHECK64-NEXT: L#BB7_2 DS 0H
+; CHECK64-NEXT: L#BB7_2 DS 0B
; CHECK64-NEXT: stmg 6,7,2064(4)
; CHECK64-NEXT: *FENCE
-; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
define void @large_stack0() {
%arr = alloca [131072 x i64], align 8
call i64 (ptr) @fun1(ptr %arr)
ret void
}
-; CHECK-LABEL: large_stack1 DS 0H
-; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-LABEL: large_stack1 DS 0B
+; CHECK64: L#stack_update{{[0-9]+}} DS 0B
; CHECK64-NEXT: agfi 4,-1048800
; CHECK64-NEXT: lgr 0,3
; CHECK64-NEXT: llgt 3,1208
@@ -382,11 +382,11 @@ define void @large_stack0() {
; CHECK64: lg 3,72(3)
; CHECK64-NEXT: basr 3,3
; CHECK64-NEXT: bcr 0,7
-; CHECK64-NEXT: L#BB8_2 DS 0H
+; CHECK64-NEXT: L#BB8_2 DS 0B
; CHECK64-NEXT: stmg 6,7,2064(4)
; CHECK64-NEXT: lgr 3,0
; CHECK64-NEXT: *FENCE
-; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
define void @large_stack1(i64 %n1, i64 %n2, i64 %n3) {
%arr = alloca [131072 x i64], align 8
@@ -399,7 +399,7 @@ define void @large_stack1(i64 %n1, i64 %n2, i64 %n3) {
; CHECK-LABEL: large_stack2
; CHECK64: lgr 0,4
; CHECK64: stg 3,2192(4)
-; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64: L#stack_update{{[0-9]+}} DS 0B
; CHECK64-NEXT: agfi 4,-1048800
; CHECK64-NEXT: llgt 3,1208
; CHECK64-NEXT: cg 4,64(3)
@@ -407,14 +407,14 @@ define void @large_stack1(i64 %n1, i64 %n2, i64 %n3) {
; CHECK64: lg 3,72(3)
; CHECK64-NEXT: basr 3,3
; CHECK64-NEXT: bcr 0,7
-; CHECK64-NEXT: L#BB9_2 DS 0H
+; CHECK64-NEXT: L#BB9_2 DS 0B
; CHECK64-NEXT: lgr 3,0
; CHECK64-NEXT: lg 3,2192(3)
; CHECK64-NEXT: stmg 4,12,2048(4)
; CHECK64-NEXT: stg 0,2048(4)
; CHECK64-NEXT: lgr 8,4
; CHECK64-NEXT: *FENCE
-; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0B
define void @large_stack2(i64 %n1, i64 %n2, i64 %n3) {
%arr0 = alloca [131072 x i64], align 8
%arr1 = alloca i64, i64 %n1, align 8
@@ -435,13 +435,13 @@ define void @large_stack3() {
ret void
}
-; CHECK-LABEL: L#EPM_leaf_func0_0 DS 0H
+; CHECK-LABEL: L#EPM_leaf_func0_0 DS 0Q
; CHECK: * DSA Size 0x0
; CHECK: * Entry Flags
; CHECK: * Bit 1: 1 = Leaf function
; CHECK: * Bit 2: 0 = Does not use alloca
; CHECK: DC XL4'00000008'
-; CHECK-LABEL: leaf_func0 DS 0H
+; CHECK-LABEL: leaf_func0 DS 0B
; CHECK-NOT: aghi 4,
; CHECK-NOT: stmg
; CHECK: agr 1,2
@@ -449,7 +449,7 @@ define void @large_stack3() {
; CHECK: aghik 3,1,-4
; CHECK-NOT: aghi 4,
; CHECK-NOT: lmg
-; CHECK-LABEL: L#leaf_func0_end_0 DS 0H
+; CHECK-LABEL: L#leaf_func0_end_0 DS 0B
define i64 @leaf_func0(i64 %a, i64 %b, i64 %c) {
%n = add i64 %a, %b
%m = mul i64 %n, %c
@@ -478,23 +478,23 @@ declare i64 @fun4(ptr %ptr0, ptr %ptr1, i64 %n1, i64 %n2, i64 %n3)
; Tests for PPA1 Fields
; =============================
-; CHECK64: L#PPA1_func0_0 DS 0H
+; CHECK64: L#PPA1_func0_0 DS 0B
; CHECK64: * Length/4 of Parms
; CHECK64: DC XL2'0000'
-; CHECK64: L#PPA1_func1_0 DS 0H
+; CHECK64: L#PPA1_func1_0 DS 0B
; CHECK64: * Length/4 of Parms
; CHECK64: DC XL2'0002'
-; CHECK64: L#PPA1_large_stack1_0 DS 0H
+; CHECK64: L#PPA1_large_stack1_0 DS 0B
; CHECK64: * Length/4 of Parms
; CHECK64: DC XL2'0006'
-; CHECK-LABEL: L#PPA1_named_func_0 DS 0H
+; CHECK-LABEL: L#PPA1_named_func_0 DS 0B
; CHECK: * PPA1 Flags 4
; CHECK-NEXT: * Bit 7: 1 = Name Length and Name
; CHECK-NEXT: DC XL1'81'
-; CHECK-LABEL: L#PPA1_0 DS 0H
+; CHECK-LABEL: L#PPA1_0 DS 0B
; CHECK: * PPA1 Flags 4
; CHECK-NEXT: DC XL1'80'
diff --git a/llvm/test/CodeGen/SystemZ/zos-ret-addr.ll b/llvm/test/CodeGen/SystemZ/zos-ret-addr.ll
index ce59020dda4b2..5079b9f38fc4e 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ret-addr.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ret-addr.ll
@@ -3,7 +3,7 @@
; The current function's return address is in the link register.
define ptr @rt0() norecurse nounwind readnone {
-; CHECK-LABEL: rt0 DS 0H
+; CHECK-LABEL: rt0 DS 0B
; CHECK: lgr 3,7
; CHECK-NEXT: b 2(7)
entry:
@@ -13,7 +13,7 @@ entry:
; Check the caller's return address.
define ptr @rtcaller() nounwind "backchain" {
-; CHECK-LABEL: rtcaller DS 0H
+; CHECK-LABEL: rtcaller DS 0B
; CHECK: stmg 4,7,2048(4)
; CHECK-NEXT: lg 1,2048(4)
; CHECK-NEXT: lg 3,24(1)
@@ -26,7 +26,7 @@ entry:
; Check the caller's caller's return address.
define ptr @rtcallercaller() nounwind "backchain" {
-; CHECK-LABEL: rtcallercaller DS 0H
+; CHECK-LABEL: rtcallercaller DS 0B
; CHECK: stmg 4,7,2048(4)
; CHECK-NEXT: lg 1,2048(4)
; CHECK-NEXT: lg 1,0(1)
diff --git a/llvm/test/CodeGen/SystemZ/zos-simple-test.ll b/llvm/test/CodeGen/SystemZ/zos-simple-test.ll
index 381d058e8d82e..427692f65367d 100644
--- a/llvm/test/CodeGen/SystemZ/zos-simple-test.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-simple-test.ll
@@ -7,7 +7,7 @@
define signext i32 @main() {
; CHECK: stdin#C CSECT
; CHECK-NEXT: C_CODE64 CATTR ALIGN(3),FILL(0),READONLY,RMODE(64)
-; CHECK: main DS 0H
+; CHECK: main DS 0B
; CHECK: a CSECT
; CHECK-NEXT: C_WSA64 CATTR ALIGN(2),FILL(0),DEFLOAD,NOTEXECUTABLE,RMODE(64),PART(a)
; CHECK-NEXT: a XATTR LINKAGE(XPLINK),REFERENCE(DATA),SCOPE(EXPORT)
diff --git a/llvm/test/CodeGen/SystemZ/zos-stack-protector.ll b/llvm/test/CodeGen/SystemZ/zos-stack-protector.ll
index e4b0ab6431a0c..fa1c3d744008d 100644
--- a/llvm/test/CodeGen/SystemZ/zos-stack-protector.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-stack-protector.ll
@@ -18,7 +18,7 @@
; CHECK: aghi 4,[[#%u,mul(div(DSA_SIZE,32),32)]]
; CHECK: b 2(7)
; failure block
-; CHECK: [[FAIL_LABEL]] DS 0H
+; CHECK: [[FAIL_LABEL]] DS 0B
; invoke __stack_chk_fail
; CHECK: lg 6,[[#CHK_FAIL_OFF:]]({{[0-9]+}})
; CHECK: lg 5,[[#CHK_FAIL_OFF-8]]({{[0-9]+}})
@@ -49,7 +49,7 @@ define void @func0() sspreq {
; CHECK: agfi 4,[[#%u,mul(div(DSA_SIZE,32),32)]]
; CHECK: b 2(7)
; failure block
-; CHECK: [[FAIL_LABEL]] DS 0H
+; CHECK: [[FAIL_LABEL]] DS 0B
; invoke __stack_chk_fail
; CHECK: lg 6,[[#CHK_FAIL_OFF:]]({{[0-9]+}})
; CHECK: lg 5,[[#CHK_FAIL_OFF-8]]({{[0-9]+}})
@@ -105,7 +105,7 @@ entry:
; CHECK: lmg 4,[[SPILLHI]],2048(4)
; CHECK: b 2(7)
; failure block
-; CHECK: [[FAIL_LABEL]] DS 0H
+; CHECK: [[FAIL_LABEL]] DS 0B
; invoke __stack_chk_fail
; CHECK: lg 6,[[#CHK_FAIL_OFF:]]({{[0-9]+}})
; CHECK: lg 5,[[#CHK_FAIL_OFF-8]]({{[0-9]+}})
@@ -130,32 +130,32 @@ declare i64 @fun(i64 %arg0)
declare i64 @fun1(ptr %ptr)
declare i64 @fun2(i64 %n, ptr %arr0, ptr %arr1)
-; CHECK-LABEL: L#PPA1_func0_0 DS 0H
+; CHECK-LABEL: L#PPA1_func0_0 DS 0B
; CHECK: * PPA1 Flags 2
; CHECK-NOT: * PPA1 Flags 3
; CHECK: * Bit 3: 1 = STACKPROTECT is enabled
-; CHECK-LABEL: L#PPA1_func1_0 DS 0H
+; CHECK-LABEL: L#PPA1_func1_0 DS 0B
; CHECK: * PPA1 Flags 2
; CHECK-NOT: * PPA1 Flags 3
; CHECK: * Bit 3: 1 = STACKPROTECT is enabled
-; CHECK-LABEL: L#PPA1_func2_64_0 DS 0H
+; CHECK-LABEL: L#PPA1_func2_64_0 DS 0B
; CHECK: * PPA1 Flags 2
; CHECK-NOT: * PPA1 Flags 3
; CHECK: * Bit 3: 1 = STACKPROTECT is enabled
-; CHECK-LABEL: L#PPA1_func3_0 DS 0H
+; CHECK-LABEL: L#PPA1_func3_0 DS 0B
; CHECK: * PPA1 Flags 2
; CHECK-NOT: * PPA1 Flags 3
; CHECK: * Bit 3: 1 = STACKPROTECT is enabled
-; CHECK-LABEL: L#PPA1_func4_0 DS 0H
+; CHECK-LABEL: L#PPA1_func4_0 DS 0B
; CHECK: * PPA1 Flags 2
; CHECK-NOT: * PPA1 Flags 3
; CHECK: * Bit 3: 1 = STACKPROTECT is enabled
-; CHECK-LABEL: L#PPA1_func5_0 DS 0H
+; CHECK-LABEL: L#PPA1_func5_0 DS 0B
; CHECK: * PPA1 Flags 2
; CHECK-NOT: * PPA1 Flags 3
; CHECK: * Bit 3: 0 = STACKPROTECT is not enabled
diff --git a/llvm/test/CodeGen/SystemZ/zos-stackpointer.ll b/llvm/test/CodeGen/SystemZ/zos-stackpointer.ll
index d40933cd8d1d8..d2c65cab692f0 100644
--- a/llvm/test/CodeGen/SystemZ/zos-stackpointer.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-stackpointer.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=s390x-ibm-zos | FileCheck %s
-; CHECK-LABEL: get_stack DS 0H
+; CHECK-LABEL: get_stack DS 0B
; CHECK: lgr 3,4
; CHECK: b 2(7)
diff --git a/llvm/test/CodeGen/SystemZ/zos-symbol-2.ll b/llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
index c06a33f5fcb23..b7c397f742c30 100644
--- a/llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
@@ -20,7 +20,7 @@ entry:
; Check the attributes on the function
; CHECK: ENTRY calc
; CHECK-NEXT: calc XATTR LINKAGE(XPLINK),REFERENCE(CODE),PSECT(stdin#S),SCOPE(EXPORT)
-; CHECK-NEXT: calc DS 0H
+; CHECK-NEXT: calc DS 0B
; Check the definition of the variable
; CHECK: a CSECT
diff --git a/llvm/test/CodeGen/SystemZ/zos-xplink64-bare-i32-arg.ll b/llvm/test/CodeGen/SystemZ/zos-xplink64-bare-i32-arg.ll
index ee77cfac4bec6..c9893914d398d 100644
--- a/llvm/test/CodeGen/SystemZ/zos-xplink64-bare-i32-arg.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-xplink64-bare-i32-arg.ll
@@ -13,7 +13,7 @@
; Bare i32 passed to sitofp. Correct: cefbr 0,1 (R1 is the source).
; Without the i32 rule: l 0,<offset>(4) then cefbr 0,0 (stack load).
define float @sitofp_bare_i32(i32 %x) {
-; CHECK-LABEL: sitofp_bare_i32 DS 0H
+; CHECK-LABEL: sitofp_bare_i32 DS 0B
; CHECK: cefbr 0,1
%r = sitofp i32 %x to float
ret float %r
@@ -21,7 +21,7 @@ define float @sitofp_bare_i32(i32 %x) {
; Bare i32 passed to sitofp (double). Correct: cdfbr 0,1.
define double @sitofp_bare_i32_double(i32 %x) {
-; CHECK-LABEL: sitofp_bare_i32_double DS 0H
+; CHECK-LABEL: sitofp_bare_i32_double DS 0B
; CHECK: cdfbr 0,1
%r = sitofp i32 %x to double
ret double %r
@@ -30,7 +30,7 @@ define double @sitofp_bare_i32_double(i32 %x) {
; Two bare i32 arguments compared. Correct: cr 1,2 (register compare).
; Without the i32 rule: two stack loads then a memory/register compare.
define i1 @cmp_bare_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: cmp_bare_i32 DS 0H
+; CHECK-LABEL: cmp_bare_i32 DS 0B
; CHECK: cr 1,2
%r = icmp eq i32 %a, %b
ret i1 %r
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