[llvm] [AArch64] Regenerate and update arm64-big-endian-bitconverts.ll. NFC (PR #222107)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 8 12:14:02 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/222107
None
>From af57c87a2c9d1c6f71dad5cd3e5660288946af63 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Tue, 8 Sep 2026 20:13:50 +0100
Subject: [PATCH] [AArch64] Regenerate and update
arm64-big-endian-bitconverts.ll. NFC
---
.../AArch64/arm64-big-endian-bitconverts.ll | 1730 +++++++++++++----
llvm/test/CodeGen/AArch64/arm64-popcnt.ll | 2 +-
2 files changed, 1300 insertions(+), 432 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll b/llvm/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
index f5aa4c666a568..20902fae97275 100644
--- a/llvm/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
@@ -1,10 +1,16 @@
-; RUN: llc -mtriple aarch64_be < %s -aarch64-enable-ldst-opt=false -O1 -o - | FileCheck %s
-; RUN: llc -mtriple aarch64_be < %s -aarch64-enable-ldst-opt=false -O0 -fast-isel=true -o - | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple aarch64_be < %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple aarch64_be < %s -O0 -fast-isel=true -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FI
-; CHECK-LABEL: test_i64_f64:
define void @test_i64_f64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: str
+; CHECK-LABEL: test_i64_f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: add x8, x8, x8
+; CHECK-NEXT: str x8, [x1]
+; CHECK-NEXT: ret
%1 = load double, ptr %p
%2 = fadd double %1, %1
%3 = bitcast double %2 to i64
@@ -13,10 +19,15 @@ define void @test_i64_f64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_i64_v1i64:
define void @test_i64_v1i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: str
+; CHECK-LABEL: test_i64_v1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: add x8, x8, x8
+; CHECK-NEXT: str x8, [x1]
+; CHECK-NEXT: ret
%1 = load <1 x i64>, ptr %p
%2 = add <1 x i64> %1, %1
%3 = bitcast <1 x i64> %2 to i64
@@ -25,11 +36,28 @@ define void @test_i64_v1i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_i64_v2f32:
define void @test_i64_v2f32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: rev64 v{{[0-9]+}}.2s
-; CHECK: str
+; CHECK-SD-LABEL: test_i64_v2f32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-SD-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-SD-NEXT: rev64 v0.2s, v0.2s
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: add x8, x8, x8
+; CHECK-SD-NEXT: str x8, [x1]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_i64_v2f32:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-FI-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-FI-NEXT: fmov x8, d0
+; CHECK-FI-NEXT: fmov d0, x8
+; CHECK-FI-NEXT: rev64 v0.2s, v0.2s
+; CHECK-FI-NEXT: fmov x8, d0
+; CHECK-FI-NEXT: add x8, x8, x8
+; CHECK-FI-NEXT: str x8, [x1]
+; CHECK-FI-NEXT: ret
%1 = load <2 x float>, ptr %p
%2 = fadd <2 x float> %1, %1
%3 = bitcast <2 x float> %2 to i64
@@ -38,11 +66,28 @@ define void @test_i64_v2f32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_i64_v2i32:
define void @test_i64_v2i32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: rev64 v{{[0-9]+}}.2s
-; CHECK: str
+; CHECK-SD-LABEL: test_i64_v2i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-SD-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-SD-NEXT: rev64 v0.2s, v0.2s
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: add x8, x8, x8
+; CHECK-SD-NEXT: str x8, [x1]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_i64_v2i32:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-FI-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-FI-NEXT: fmov x8, d0
+; CHECK-FI-NEXT: fmov d0, x8
+; CHECK-FI-NEXT: rev64 v0.2s, v0.2s
+; CHECK-FI-NEXT: fmov x8, d0
+; CHECK-FI-NEXT: add x8, x8, x8
+; CHECK-FI-NEXT: str x8, [x1]
+; CHECK-FI-NEXT: ret
%1 = load <2 x i32>, ptr %p
%2 = add <2 x i32> %1, %1
%3 = bitcast <2 x i32> %2 to i64
@@ -51,13 +96,32 @@ define void @test_i64_v2i32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_i64_v4f16:
define void @test_i64_v4f16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4h }
-; CHECK-NOT: rev
-; CHECK: fadd
-; CHECK: rev64 v{{[0-9]+}}.4h
-; CHECK: str
+; CHECK-SD-LABEL: test_i64_v4f16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-SD-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-SD-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: rev64 v0.4h, v0.4h
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: add x8, x8, x8
+; CHECK-SD-NEXT: str x8, [x1]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_i64_v4f16:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-FI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FI-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-FI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-FI-NEXT: fmov x8, d0
+; CHECK-FI-NEXT: fmov d0, x8
+; CHECK-FI-NEXT: rev64 v0.4h, v0.4h
+; CHECK-FI-NEXT: fmov x8, d0
+; CHECK-FI-NEXT: add x8, x8, x8
+; CHECK-FI-NEXT: str x8, [x1]
+; CHECK-FI-NEXT: ret
%1 = load <4 x half>, ptr %p
%2 = fadd <4 x half> %1, %1
%3 = bitcast <4 x half> %2 to i64
@@ -66,11 +130,28 @@ define void @test_i64_v4f16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_i64_v4i16:
define void @test_i64_v4i16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4h }
-; CHECK: rev64 v{{[0-9]+}}.4h
-; CHECK: str
+; CHECK-SD-LABEL: test_i64_v4i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-SD-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: rev64 v0.4h, v0.4h
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: add x8, x8, x8
+; CHECK-SD-NEXT: str x8, [x1]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_i64_v4i16:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-FI-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-FI-NEXT: fmov x8, d0
+; CHECK-FI-NEXT: fmov d0, x8
+; CHECK-FI-NEXT: rev64 v0.4h, v0.4h
+; CHECK-FI-NEXT: fmov x8, d0
+; CHECK-FI-NEXT: add x8, x8, x8
+; CHECK-FI-NEXT: str x8, [x1]
+; CHECK-FI-NEXT: ret
%1 = load <4 x i16>, ptr %p
%2 = add <4 x i16> %1, %1
%3 = bitcast <4 x i16> %2 to i64
@@ -79,11 +160,28 @@ define void @test_i64_v4i16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_i64_v8i8:
define void @test_i64_v8i8(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8b }
-; CHECK: rev64 v{{[0-9]+}}.8b
-; CHECK: str
+; CHECK-SD-LABEL: test_i64_v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ld1 { v0.8b }, [x0]
+; CHECK-SD-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-SD-NEXT: rev64 v0.8b, v0.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: add x8, x8, x8
+; CHECK-SD-NEXT: str x8, [x1]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_i64_v8i8:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: ld1 { v0.8b }, [x0]
+; CHECK-FI-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-FI-NEXT: fmov x8, d0
+; CHECK-FI-NEXT: fmov d0, x8
+; CHECK-FI-NEXT: rev64 v0.8b, v0.8b
+; CHECK-FI-NEXT: fmov x8, d0
+; CHECK-FI-NEXT: add x8, x8, x8
+; CHECK-FI-NEXT: str x8, [x1]
+; CHECK-FI-NEXT: ret
%1 = load <8 x i8>, ptr %p
%2 = add <8 x i8> %1, %1
%3 = bitcast <8 x i8> %2 to i64
@@ -92,10 +190,15 @@ define void @test_i64_v8i8(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_f64_i64:
define void @test_f64_i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: str
+; CHECK-LABEL: test_f64_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: add x8, x8, x8
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load i64, ptr %p
%2 = add i64 %1, %1
%3 = bitcast i64 %2 to double
@@ -104,10 +207,14 @@ define void @test_f64_i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_f64_v1i64:
define void @test_f64_v1i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: str
+; CHECK-LABEL: test_f64_v1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load <1 x i64>, ptr %p
%2 = add <1 x i64> %1, %1
%3 = bitcast <1 x i64> %2 to double
@@ -116,11 +223,15 @@ define void @test_f64_v1i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_f64_v2f32:
define void @test_f64_v2f32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: rev64 v{{[0-9]+}}.2s
-; CHECK: str
+; CHECK-LABEL: test_f64_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x float>, ptr %p
%2 = fadd <2 x float> %1, %1
%3 = bitcast <2 x float> %2 to double
@@ -129,11 +240,15 @@ define void @test_f64_v2f32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_f64_v2i32:
define void @test_f64_v2i32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: rev64 v{{[0-9]+}}.2s
-; CHECK: str
+; CHECK-LABEL: test_f64_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x i32>, ptr %p
%2 = add <2 x i32> %1, %1
%3 = bitcast <2 x i32> %2 to double
@@ -142,11 +257,15 @@ define void @test_f64_v2i32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_f64_v4i16:
define void @test_f64_v4i16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4h }
-; CHECK: rev64 v{{[0-9]+}}.4h
-; CHECK: str
+; CHECK-LABEL: test_f64_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x i16>, ptr %p
%2 = add <4 x i16> %1, %1
%3 = bitcast <4 x i16> %2 to double
@@ -155,14 +274,17 @@ define void @test_f64_v4i16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_f64_v4f16:
define void @test_f64_v4f16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4h }
-; CHECK-NOT: rev
-; CHECK: fadd
-; CHECK: rev64 v{{[0-9]+}}.4h
-; CHECK: fadd
-; CHECK: str
+; CHECK-LABEL: test_f64_v4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x half>, ptr %p
%2 = fadd <4 x half> %1, %1
%3 = bitcast <4 x half> %2 to double
@@ -171,11 +293,15 @@ define void @test_f64_v4f16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_f64_v8i8:
define void @test_f64_v8i8(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8b }
-; CHECK: rev64 v{{[0-9]+}}.8b
-; CHECK: str
+; CHECK-LABEL: test_f64_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.8b }, [x0]
+; CHECK-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load <8 x i8>, ptr %p
%2 = add <8 x i8> %1, %1
%3 = bitcast <8 x i8> %2 to double
@@ -184,10 +310,15 @@ define void @test_f64_v8i8(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v1i64_i64:
define void @test_v1i64_i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: str
+; CHECK-LABEL: test_v1i64_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: add x8, x8, x8
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load i64, ptr %p
%2 = add i64 %1, %1
%3 = bitcast i64 %2 to <1 x i64>
@@ -196,10 +327,14 @@ define void @test_v1i64_i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v1i64_f64:
define void @test_v1i64_f64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: str
+; CHECK-LABEL: test_v1i64_f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load double, ptr %p
%2 = fadd double %1, %1
%3 = bitcast double %2 to <1 x i64>
@@ -208,11 +343,15 @@ define void @test_v1i64_f64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v1i64_v2f32:
define void @test_v1i64_v2f32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: rev64 v{{[0-9]+}}.2s
-; CHECK: str
+; CHECK-LABEL: test_v1i64_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x float>, ptr %p
%2 = fadd <2 x float> %1, %1
%3 = bitcast <2 x float> %2 to <1 x i64>
@@ -221,11 +360,15 @@ define void @test_v1i64_v2f32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v1i64_v2i32:
define void @test_v1i64_v2i32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: rev64 v{{[0-9]+}}.2s
-; CHECK: str
+; CHECK-LABEL: test_v1i64_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x i32>, ptr %p
%2 = add <2 x i32> %1, %1
%3 = bitcast <2 x i32> %2 to <1 x i64>
@@ -234,13 +377,17 @@ define void @test_v1i64_v2i32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v1i64_v4f16:
define void @test_v1i64_v4f16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4h }
-; CHECK-NOT: rev
-; CHECK: fadd
-; CHECK: rev64 v{{[0-9]+}}.4h
-; CHECK: str
+; CHECK-LABEL: test_v1i64_v4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x half>, ptr %p
%2 = fadd <4 x half> %1, %1
%3 = bitcast <4 x half> %2 to <1 x i64>
@@ -249,11 +396,15 @@ define void @test_v1i64_v4f16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v1i64_v4i16:
define void @test_v1i64_v4i16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4h }
-; CHECK: rev64 v{{[0-9]+}}.4h
-; CHECK: str
+; CHECK-LABEL: test_v1i64_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x i16>, ptr %p
%2 = add <4 x i16> %1, %1
%3 = bitcast <4 x i16> %2 to <1 x i64>
@@ -262,11 +413,15 @@ define void @test_v1i64_v4i16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v1i64_v8i8:
define void @test_v1i64_v8i8(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8b }
-; CHECK: rev64 v{{[0-9]+}}.8b
-; CHECK: str
+; CHECK-LABEL: test_v1i64_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.8b }, [x0]
+; CHECK-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%1 = load <8 x i8>, ptr %p
%2 = add <8 x i8> %1, %1
%3 = bitcast <8 x i8> %2 to <1 x i64>
@@ -275,11 +430,16 @@ define void @test_v1i64_v8i8(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2f32_i64:
define void @test_v2f32_i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.2s
-; CHECK: st1 { v{{[0-9]+}}.2s }
+; CHECK-LABEL: test_v2f32_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: add x8, x8, x8
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: st1 { v0.2s }, [x1]
+; CHECK-NEXT: ret
%1 = load i64, ptr %p
%2 = add i64 %1, %1
%3 = bitcast i64 %2 to <2 x float>
@@ -288,11 +448,15 @@ define void @test_v2f32_i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2f32_f64:
define void @test_v2f32_f64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.2s
-; CHECK: st1 { v{{[0-9]+}}.2s }
+; CHECK-LABEL: test_v2f32_f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: st1 { v0.2s }, [x1]
+; CHECK-NEXT: ret
%1 = load double, ptr %p
%2 = fadd double %1, %1
%3 = bitcast double %2 to <2 x float>
@@ -301,11 +465,15 @@ define void @test_v2f32_f64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2f32_v1i64:
define void @test_v2f32_v1i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.2s
-; CHECK: st1 { v{{[0-9]+}}.2s }
+; CHECK-LABEL: test_v2f32_v1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: st1 { v0.2s }, [x1]
+; CHECK-NEXT: ret
%1 = load <1 x i64>, ptr %p
%2 = add <1 x i64> %1, %1
%3 = bitcast <1 x i64> %2 to <2 x float>
@@ -314,10 +482,14 @@ define void @test_v2f32_v1i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2f32_v2i32:
define void @test_v2f32_v2i32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: st1 { v{{[0-9]+}}.2s }
+; CHECK-LABEL: test_v2f32_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: st1 { v0.2s }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x i32>, ptr %p
%2 = add <2 x i32> %1, %1
%3 = bitcast <2 x i32> %2 to <2 x float>
@@ -326,11 +498,15 @@ define void @test_v2f32_v2i32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2f32_v4i16:
define void @test_v2f32_v4i16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4h }
-; CHECK: rev32 v{{[0-9]+}}.4h
-; CHECK: st1 { v{{[0-9]+}}.2s }
+; CHECK-LABEL: test_v2f32_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: rev32 v0.4h, v0.4h
+; CHECK-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: st1 { v0.2s }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x i16>, ptr %p
%2 = add <4 x i16> %1, %1
%3 = bitcast <4 x i16> %2 to <2 x float>
@@ -339,13 +515,17 @@ define void @test_v2f32_v4i16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2f32_v4f16:
define void @test_v2f32_v4f16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4h }
-; CHECK-NOT: rev
-; CHECK: fadd
-; CHECK: rev32 v{{[0-9]+}}.4h
-; CHECK: st1 { v{{[0-9]+}}.2s }
+; CHECK-LABEL: test_v2f32_v4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: rev32 v0.4h, v0.4h
+; CHECK-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: st1 { v0.2s }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x half>, ptr %p
%2 = fadd <4 x half> %1, %1
%3 = bitcast <4 x half> %2 to <2 x float>
@@ -354,11 +534,15 @@ define void @test_v2f32_v4f16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2f32_v8i8:
define void @test_v2f32_v8i8(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8b }
-; CHECK: rev32 v{{[0-9]+}}.8b
-; CHECK: st1 { v{{[0-9]+}}.2s }
+; CHECK-LABEL: test_v2f32_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.8b }, [x0]
+; CHECK-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: rev32 v0.8b, v0.8b
+; CHECK-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: st1 { v0.2s }, [x1]
+; CHECK-NEXT: ret
%1 = load <8 x i8>, ptr %p
%2 = add <8 x i8> %1, %1
%3 = bitcast <8 x i8> %2 to <2 x float>
@@ -367,11 +551,16 @@ define void @test_v2f32_v8i8(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2i32_i64:
define void @test_v2i32_i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.2s
-; CHECK: st1 { v{{[0-9]+}}.2s }
+; CHECK-LABEL: test_v2i32_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: add x8, x8, x8
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: st1 { v0.2s }, [x1]
+; CHECK-NEXT: ret
%1 = load i64, ptr %p
%2 = add i64 %1, %1
%3 = bitcast i64 %2 to <2 x i32>
@@ -380,11 +569,15 @@ define void @test_v2i32_i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2i32_f64:
define void @test_v2i32_f64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.2s
-; CHECK: st1 { v{{[0-9]+}}.2s }
+; CHECK-LABEL: test_v2i32_f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: st1 { v0.2s }, [x1]
+; CHECK-NEXT: ret
%1 = load double, ptr %p
%2 = fadd double %1, %1
%3 = bitcast double %2 to <2 x i32>
@@ -393,11 +586,15 @@ define void @test_v2i32_f64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2i32_v1i64:
define void @test_v2i32_v1i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.2s
-; CHECK: st1 { v{{[0-9]+}}.2s }
+; CHECK-LABEL: test_v2i32_v1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: st1 { v0.2s }, [x1]
+; CHECK-NEXT: ret
%1 = load <1 x i64>, ptr %p
%2 = add <1 x i64> %1, %1
%3 = bitcast <1 x i64> %2 to <2 x i32>
@@ -406,10 +603,14 @@ define void @test_v2i32_v1i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2i32_v2f32:
define void @test_v2i32_v2f32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: st1 { v{{[0-9]+}}.2s }
+; CHECK-LABEL: test_v2i32_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: st1 { v0.2s }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x float>, ptr %p
%2 = fadd <2 x float> %1, %1
%3 = bitcast <2 x float> %2 to <2 x i32>
@@ -418,11 +619,15 @@ define void @test_v2i32_v2f32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2i32_v4i16:
define void @test_v2i32_v4i16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4h }
-; CHECK: rev32 v{{[0-9]+}}.4h
-; CHECK: st1 { v{{[0-9]+}}.2s }
+; CHECK-LABEL: test_v2i32_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: rev32 v0.4h, v0.4h
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: st1 { v0.2s }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x i16>, ptr %p
%2 = add <4 x i16> %1, %1
%3 = bitcast <4 x i16> %2 to <2 x i32>
@@ -431,11 +636,15 @@ define void @test_v2i32_v4i16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2i32_v8i8:
define void @test_v2i32_v8i8(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8b }
-; CHECK: rev32 v{{[0-9]+}}.8b
-; CHECK: st1 { v{{[0-9]+}}.2s }
+; CHECK-LABEL: test_v2i32_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.8b }, [x0]
+; CHECK-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: rev32 v0.8b, v0.8b
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: st1 { v0.2s }, [x1]
+; CHECK-NEXT: ret
%1 = load <8 x i8>, ptr %p
%2 = add <8 x i8> %1, %1
%3 = bitcast <8 x i8> %2 to <2 x i32>
@@ -444,11 +653,16 @@ define void @test_v2i32_v8i8(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4i16_i64:
define void @test_v4i16_i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.4h
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4i16_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: add x8, x8, x8
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load i64, ptr %p
%2 = add i64 %1, %1
%3 = bitcast i64 %2 to <4 x i16>
@@ -457,11 +671,15 @@ define void @test_v4i16_i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4i16_f64:
define void @test_v4i16_f64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.4h
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4i16_f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load double, ptr %p
%2 = fadd double %1, %1
%3 = bitcast double %2 to <4 x i16>
@@ -470,11 +688,15 @@ define void @test_v4i16_f64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4i16_v1i64:
define void @test_v4i16_v1i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.4h
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4i16_v1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load <1 x i64>, ptr %p
%2 = add <1 x i64> %1, %1
%3 = bitcast <1 x i64> %2 to <4 x i16>
@@ -483,11 +705,15 @@ define void @test_v4i16_v1i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4i16_v2f32:
define void @test_v4i16_v2f32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: rev32 v{{[0-9]+}}.4h
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4i16_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: rev32 v0.4h, v0.4h
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x float>, ptr %p
%2 = fadd <2 x float> %1, %1
%3 = bitcast <2 x float> %2 to <4 x i16>
@@ -496,11 +722,15 @@ define void @test_v4i16_v2f32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4i16_v2i32:
define void @test_v4i16_v2i32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: rev32 v{{[0-9]+}}.4h
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4i16_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: rev32 v0.4h, v0.4h
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x i32>, ptr %p
%2 = add <2 x i32> %1, %1
%3 = bitcast <2 x i32> %2 to <4 x i16>
@@ -509,11 +739,16 @@ define void @test_v4i16_v2i32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4i16_v4f16:
define void @test_v4i16_v4f16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4h }
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4i16_v4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x half>, ptr %p
%2 = fadd <4 x half> %1, %1
%3 = bitcast <4 x half> %2 to <4 x i16>
@@ -522,11 +757,15 @@ define void @test_v4i16_v4f16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4i16_v8i8:
define void @test_v4i16_v8i8(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8b }
-; CHECK: rev16 v{{[0-9]+}}.8b
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4i16_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.8b }, [x0]
+; CHECK-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: rev16 v0.8b, v0.8b
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load <8 x i8>, ptr %p
%2 = add <8 x i8> %1, %1
%3 = bitcast <8 x i8> %2 to <4 x i16>
@@ -535,13 +774,18 @@ define void @test_v4i16_v8i8(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f16_i64:
define void @test_v4f16_i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.4h
-; CHECK: fadd
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4f16_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: add x8, x8, x8
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load i64, ptr %p
%2 = add i64 %1, %1
%3 = bitcast i64 %2 to <4 x half>
@@ -550,13 +794,17 @@ define void @test_v4f16_i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f16_f64:
define void @test_v4f16_f64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.4h
-; CHECK: fadd
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4f16_f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load double, ptr %p
%2 = fadd double %1, %1
%3 = bitcast double %2 to <4 x half>
@@ -565,13 +813,17 @@ define void @test_v4f16_f64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f16_v1i64:
define void @test_v4f16_v1i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.4h
-; CHECK: fadd
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4f16_v1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load <1 x i64>, ptr %p
%2 = add <1 x i64> %1, %1
%3 = bitcast <1 x i64> %2 to <4 x half>
@@ -580,13 +832,17 @@ define void @test_v4f16_v1i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f16_v2f32:
define void @test_v4f16_v2f32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: rev32 v{{[0-9]+}}.4h
-; CHECK: fadd
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4f16_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: rev32 v0.4h, v0.4h
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x float>, ptr %p
%2 = fadd <2 x float> %1, %1
%3 = bitcast <2 x float> %2 to <4 x half>
@@ -595,13 +851,17 @@ define void @test_v4f16_v2f32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f16_v2i32:
define void @test_v4f16_v2i32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: rev32 v{{[0-9]+}}.4h
-; CHECK: fadd
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4f16_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: rev32 v0.4h, v0.4h
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x i32>, ptr %p
%2 = add <2 x i32> %1, %1
%3 = bitcast <2 x i32> %2 to <4 x half>
@@ -610,11 +870,16 @@ define void @test_v4f16_v2i32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f16_v4i16:
define void @test_v4f16_v4i16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4h }
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4f16_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x i16>, ptr %p
%2 = add <4 x i16> %1, %1
%3 = bitcast <4 x i16> %2 to <4 x half>
@@ -623,13 +888,17 @@ define void @test_v4f16_v4i16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f16_v8i8:
define void @test_v4f16_v8i8(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8b }
-; CHECK: rev16 v{{[0-9]+}}.8b
-; CHECK: fadd
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4h }
+; CHECK-LABEL: test_v4f16_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.8b }, [x0]
+; CHECK-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: rev16 v0.8b, v0.8b
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: st1 { v0.4h }, [x1]
+; CHECK-NEXT: ret
%1 = load <8 x i8>, ptr %p
%2 = add <8 x i8> %1, %1
%3 = bitcast <8 x i8> %2 to <4 x half>
@@ -638,11 +907,16 @@ define void @test_v4f16_v8i8(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v8i8_i64:
define void @test_v8i8_i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.8b
-; CHECK: st1 { v{{[0-9]+}}.8b }
+; CHECK-LABEL: test_v8i8_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: add x8, x8, x8
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: st1 { v0.8b }, [x1]
+; CHECK-NEXT: ret
%1 = load i64, ptr %p
%2 = add i64 %1, %1
%3 = bitcast i64 %2 to <8 x i8>
@@ -651,11 +925,15 @@ define void @test_v8i8_i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v8i8_f64:
define void @test_v8i8_f64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.8b
-; CHECK: st1 { v{{[0-9]+}}.8b }
+; CHECK-LABEL: test_v8i8_f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: fadd d0, d0, d0
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: st1 { v0.8b }, [x1]
+; CHECK-NEXT: ret
%1 = load double, ptr %p
%2 = fadd double %1, %1
%3 = bitcast double %2 to <8 x i8>
@@ -664,11 +942,15 @@ define void @test_v8i8_f64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v8i8_v1i64:
define void @test_v8i8_v1i64(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.8b
-; CHECK: st1 { v{{[0-9]+}}.8b }
+; CHECK-LABEL: test_v8i8_v1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: add d0, d0, d0
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: st1 { v0.8b }, [x1]
+; CHECK-NEXT: ret
%1 = load <1 x i64>, ptr %p
%2 = add <1 x i64> %1, %1
%3 = bitcast <1 x i64> %2 to <8 x i8>
@@ -677,11 +959,15 @@ define void @test_v8i8_v1i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v8i8_v2f32:
define void @test_v8i8_v2f32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: rev32 v{{[0-9]+}}.8b
-; CHECK: st1 { v{{[0-9]+}}.8b }
+; CHECK-LABEL: test_v8i8_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-NEXT: fadd v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: rev32 v0.8b, v0.8b
+; CHECK-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: st1 { v0.8b }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x float>, ptr %p
%2 = fadd <2 x float> %1, %1
%3 = bitcast <2 x float> %2 to <8 x i8>
@@ -690,11 +976,15 @@ define void @test_v8i8_v2f32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v8i8_v2i32:
define void @test_v8i8_v2i32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2s }
-; CHECK: rev32 v{{[0-9]+}}.8b
-; CHECK: st1 { v{{[0-9]+}}.8b }
+; CHECK-LABEL: test_v8i8_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2s }, [x0]
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: rev32 v0.8b, v0.8b
+; CHECK-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: st1 { v0.8b }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x i32>, ptr %p
%2 = add <2 x i32> %1, %1
%3 = bitcast <2 x i32> %2 to <8 x i8>
@@ -703,11 +993,15 @@ define void @test_v8i8_v2i32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v8i8_v4i16:
define void @test_v8i8_v4i16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4h }
-; CHECK: rev16 v{{[0-9]+}}.8b
-; CHECK: st1 { v{{[0-9]+}}.8b }
+; CHECK-LABEL: test_v8i8_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: rev16 v0.8b, v0.8b
+; CHECK-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: st1 { v0.8b }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x i16>, ptr %p
%2 = add <4 x i16> %1, %1
%3 = bitcast <4 x i16> %2 to <8 x i8>
@@ -716,11 +1010,40 @@ define void @test_v8i8_v4i16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_f128_v2f64:
define void @test_f128_v2f64(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2d }
-; CHECK: ext
-; CHECK: str
+; CHECK-SD-LABEL: test_f128_v2f64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w30, -16
+; CHECK-SD-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-SD-NEXT: mov x19, x1
+; CHECK-SD-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: bl __addtf3
+; CHECK-SD-NEXT: str q0, [x19]
+; CHECK-SD-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_f128_v2f64:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: sub sp, sp, #32
+; CHECK-FI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-FI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FI-NEXT: .cfi_offset w30, -16
+; CHECK-FI-NEXT: str x1, [sp, #8] // 8-byte Spill
+; CHECK-FI-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-FI-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-FI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FI-NEXT: mov v0.16b, v1.16b
+; CHECK-FI-NEXT: bl __addtf3
+; CHECK-FI-NEXT: ldr x1, [sp, #8] // 8-byte Reload
+; CHECK-FI-NEXT: str q0, [x1]
+; CHECK-FI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-FI-NEXT: add sp, sp, #32
+; CHECK-FI-NEXT: ret
%1 = load <2 x double>, ptr %p
%2 = fadd <2 x double> %1, %1
%3 = bitcast <2 x double> %2 to fp128
@@ -729,11 +1052,40 @@ define void @test_f128_v2f64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_f128_v2i64:
define void @test_f128_v2i64(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2d }
-; CHECK: ext
-; CHECK: str
+; CHECK-SD-LABEL: test_f128_v2i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w30, -16
+; CHECK-SD-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-SD-NEXT: mov x19, x1
+; CHECK-SD-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: bl __addtf3
+; CHECK-SD-NEXT: str q0, [x19]
+; CHECK-SD-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_f128_v2i64:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: sub sp, sp, #32
+; CHECK-FI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-FI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FI-NEXT: .cfi_offset w30, -16
+; CHECK-FI-NEXT: str x1, [sp, #8] // 8-byte Spill
+; CHECK-FI-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-FI-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-FI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FI-NEXT: mov v0.16b, v1.16b
+; CHECK-FI-NEXT: bl __addtf3
+; CHECK-FI-NEXT: ldr x1, [sp, #8] // 8-byte Reload
+; CHECK-FI-NEXT: str q0, [x1]
+; CHECK-FI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-FI-NEXT: add sp, sp, #32
+; CHECK-FI-NEXT: ret
%1 = load <2 x i64>, ptr %p
%2 = add <2 x i64> %1, %1
%3 = bitcast <2 x i64> %2 to fp128
@@ -742,14 +1094,42 @@ define void @test_f128_v2i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_f128_v4f32:
define void @test_f128_v4f32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4s }
-; CHECK-NOT: rev
-; CHECK: fadd
-; CHECK: rev64 v{{[0-9]+}}.4s
-; CHECK: ext
-; CHECK: str q
+; CHECK-SD-LABEL: test_f128_v4f32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w30, -16
+; CHECK-SD-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-SD-NEXT: mov x19, x1
+; CHECK-SD-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-SD-NEXT: rev64 v0.4s, v0.4s
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: bl __addtf3
+; CHECK-SD-NEXT: str q0, [x19]
+; CHECK-SD-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_f128_v4f32:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: sub sp, sp, #32
+; CHECK-FI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-FI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FI-NEXT: .cfi_offset w30, -16
+; CHECK-FI-NEXT: str x1, [sp, #8] // 8-byte Spill
+; CHECK-FI-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-FI-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-FI-NEXT: rev64 v0.4s, v0.4s
+; CHECK-FI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FI-NEXT: mov v0.16b, v1.16b
+; CHECK-FI-NEXT: bl __addtf3
+; CHECK-FI-NEXT: ldr x1, [sp, #8] // 8-byte Reload
+; CHECK-FI-NEXT: str q0, [x1]
+; CHECK-FI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-FI-NEXT: add sp, sp, #32
+; CHECK-FI-NEXT: ret
%1 = load <4 x float>, ptr %p
%2 = fadd <4 x float> %1, %1
%3 = bitcast <4 x float> %2 to fp128
@@ -758,12 +1138,42 @@ define void @test_f128_v4f32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_f128_v4i32:
define void @test_f128_v4i32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4s }
-; CHECK: rev64 v{{[0-9]+}}.4s
-; CHECK: ext
-; CHECK: str
+; CHECK-SD-LABEL: test_f128_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w30, -16
+; CHECK-SD-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-SD-NEXT: mov x19, x1
+; CHECK-SD-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-SD-NEXT: rev64 v0.4s, v0.4s
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: bl __addtf3
+; CHECK-SD-NEXT: str q0, [x19]
+; CHECK-SD-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_f128_v4i32:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: sub sp, sp, #32
+; CHECK-FI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-FI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FI-NEXT: .cfi_offset w30, -16
+; CHECK-FI-NEXT: str x1, [sp, #8] // 8-byte Spill
+; CHECK-FI-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-FI-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-FI-NEXT: rev64 v0.4s, v0.4s
+; CHECK-FI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FI-NEXT: mov v0.16b, v1.16b
+; CHECK-FI-NEXT: bl __addtf3
+; CHECK-FI-NEXT: ldr x1, [sp, #8] // 8-byte Reload
+; CHECK-FI-NEXT: str q0, [x1]
+; CHECK-FI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-FI-NEXT: add sp, sp, #32
+; CHECK-FI-NEXT: ret
%1 = load <4 x i32>, ptr %p
%2 = add <4 x i32> %1, %1
%3 = bitcast <4 x i32> %2 to fp128
@@ -772,12 +1182,42 @@ define void @test_f128_v4i32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_f128_v8i16:
define void @test_f128_v8i16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8h }
-; CHECK: rev64 v{{[0-9]+}}.8h
-; CHECK: ext
-; CHECK: str
+; CHECK-SD-LABEL: test_f128_v8i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w30, -16
+; CHECK-SD-NEXT: ld1 { v0.8h }, [x0]
+; CHECK-SD-NEXT: mov x19, x1
+; CHECK-SD-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-SD-NEXT: rev64 v0.8h, v0.8h
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: bl __addtf3
+; CHECK-SD-NEXT: str q0, [x19]
+; CHECK-SD-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_f128_v8i16:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: sub sp, sp, #32
+; CHECK-FI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-FI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FI-NEXT: .cfi_offset w30, -16
+; CHECK-FI-NEXT: str x1, [sp, #8] // 8-byte Spill
+; CHECK-FI-NEXT: ld1 { v0.8h }, [x0]
+; CHECK-FI-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-FI-NEXT: rev64 v0.8h, v0.8h
+; CHECK-FI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FI-NEXT: mov v0.16b, v1.16b
+; CHECK-FI-NEXT: bl __addtf3
+; CHECK-FI-NEXT: ldr x1, [sp, #8] // 8-byte Reload
+; CHECK-FI-NEXT: str q0, [x1]
+; CHECK-FI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-FI-NEXT: add sp, sp, #32
+; CHECK-FI-NEXT: ret
%1 = load <8 x i16>, ptr %p
%2 = add <8 x i16> %1, %1
%3 = bitcast <8 x i16> %2 to fp128
@@ -786,11 +1226,42 @@ define void @test_f128_v8i16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_f128_v16i8:
define void @test_f128_v16i8(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.16b }
-; CHECK: ext
-; CHECK: str q
+; CHECK-SD-LABEL: test_f128_v16i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w30, -16
+; CHECK-SD-NEXT: ld1 { v0.16b }, [x0]
+; CHECK-SD-NEXT: mov x19, x1
+; CHECK-SD-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-SD-NEXT: rev64 v0.16b, v0.16b
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: bl __addtf3
+; CHECK-SD-NEXT: str q0, [x19]
+; CHECK-SD-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_f128_v16i8:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: sub sp, sp, #32
+; CHECK-FI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-FI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FI-NEXT: .cfi_offset w30, -16
+; CHECK-FI-NEXT: str x1, [sp, #8] // 8-byte Spill
+; CHECK-FI-NEXT: ld1 { v0.16b }, [x0]
+; CHECK-FI-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-FI-NEXT: rev64 v0.16b, v0.16b
+; CHECK-FI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FI-NEXT: mov v0.16b, v1.16b
+; CHECK-FI-NEXT: bl __addtf3
+; CHECK-FI-NEXT: ldr x1, [sp, #8] // 8-byte Reload
+; CHECK-FI-NEXT: str q0, [x1]
+; CHECK-FI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-FI-NEXT: add sp, sp, #32
+; CHECK-FI-NEXT: ret
%1 = load <16 x i8>, ptr %p
%2 = add <16 x i8> %1, %1
%3 = bitcast <16 x i8> %2 to fp128
@@ -799,11 +1270,40 @@ define void @test_f128_v16i8(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2f64_f128:
define void @test_v2f64_f128(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: ext
-; CHECK: st1 { v{{[0-9]+}}.2d }
+; CHECK-SD-LABEL: test_v2f64_f128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w30, -16
+; CHECK-SD-NEXT: ldr q0, [x0]
+; CHECK-SD-NEXT: mov x19, x1
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: bl __addtf3
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-SD-NEXT: st1 { v0.2d }, [x19]
+; CHECK-SD-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_v2f64_f128:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: sub sp, sp, #32
+; CHECK-FI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-FI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FI-NEXT: .cfi_offset w30, -16
+; CHECK-FI-NEXT: str x1, [sp, #8] // 8-byte Spill
+; CHECK-FI-NEXT: ldr q1, [x0]
+; CHECK-FI-NEXT: mov v0.16b, v1.16b
+; CHECK-FI-NEXT: bl __addtf3
+; CHECK-FI-NEXT: ldr x1, [sp, #8] // 8-byte Reload
+; CHECK-FI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-FI-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-FI-NEXT: st1 { v0.2d }, [x1]
+; CHECK-FI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-FI-NEXT: add sp, sp, #32
+; CHECK-FI-NEXT: ret
%1 = load fp128, ptr %p
%2 = fadd fp128 %1, %1
%3 = bitcast fp128 %2 to <2 x double>
@@ -812,10 +1312,14 @@ define void @test_v2f64_f128(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2f64_v2i64:
define void @test_v2f64_v2i64(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2d }
-; CHECK: st1 { v{{[0-9]+}}.2d }
+; CHECK-LABEL: test_v2f64_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: st1 { v0.2d }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x i64>, ptr %p
%2 = add <2 x i64> %1, %1
%3 = bitcast <2 x i64> %2 to <2 x double>
@@ -824,13 +1328,15 @@ define void @test_v2f64_v2i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2f64_v4f32:
define void @test_v2f64_v4f32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4s }
-; CHECK-NOT: rev
-; CHECK: fadd
-; CHECK: rev64 v{{[0-9]+}}.4s
-; CHECK: st1 { v{{[0-9]+}}.2d }
+; CHECK-LABEL: test_v2f64_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: st1 { v0.2d }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x float>, ptr %p
%2 = fadd <4 x float> %1, %1
%3 = bitcast <4 x float> %2 to <2 x double>
@@ -839,11 +1345,15 @@ define void @test_v2f64_v4f32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2f64_v4i32:
define void @test_v2f64_v4i32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4s }
-; CHECK: rev64 v{{[0-9]+}}.4s
-; CHECK: st1 { v{{[0-9]+}}.2d }
+; CHECK-LABEL: test_v2f64_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: st1 { v0.2d }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x i32>, ptr %p
%2 = add <4 x i32> %1, %1
%3 = bitcast <4 x i32> %2 to <2 x double>
@@ -852,11 +1362,15 @@ define void @test_v2f64_v4i32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2f64_v8i16:
define void @test_v2f64_v8i16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8h }
-; CHECK: rev64 v{{[0-9]+}}.8h
-; CHECK: st1 { v{{[0-9]+}}.2d }
+; CHECK-LABEL: test_v2f64_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.8h }, [x0]
+; CHECK-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: st1 { v0.2d }, [x1]
+; CHECK-NEXT: ret
%1 = load <8 x i16>, ptr %p
%2 = add <8 x i16> %1, %1
%3 = bitcast <8 x i16> %2 to <2 x double>
@@ -865,11 +1379,15 @@ define void @test_v2f64_v8i16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2f64_v16i8:
define void @test_v2f64_v16i8(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.16b }
-; CHECK: rev64 v{{[0-9]+}}.16b
-; CHECK: st1 { v{{[0-9]+}}.2d }
+; CHECK-LABEL: test_v2f64_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.16b }, [x0]
+; CHECK-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: st1 { v0.2d }, [x1]
+; CHECK-NEXT: ret
%1 = load <16 x i8>, ptr %p
%2 = add <16 x i8> %1, %1
%3 = bitcast <16 x i8> %2 to <2 x double>
@@ -878,11 +1396,40 @@ define void @test_v2f64_v16i8(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2i64_f128:
define void @test_v2i64_f128(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: ext
-; CHECK: st1 { v{{[0-9]+}}.2d }
+; CHECK-SD-LABEL: test_v2i64_f128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w30, -16
+; CHECK-SD-NEXT: ldr q0, [x0]
+; CHECK-SD-NEXT: mov x19, x1
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: bl __addtf3
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-SD-NEXT: st1 { v0.2d }, [x19]
+; CHECK-SD-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_v2i64_f128:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: sub sp, sp, #32
+; CHECK-FI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-FI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FI-NEXT: .cfi_offset w30, -16
+; CHECK-FI-NEXT: str x1, [sp, #8] // 8-byte Spill
+; CHECK-FI-NEXT: ldr q1, [x0]
+; CHECK-FI-NEXT: mov v0.16b, v1.16b
+; CHECK-FI-NEXT: bl __addtf3
+; CHECK-FI-NEXT: ldr x1, [sp, #8] // 8-byte Reload
+; CHECK-FI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-FI-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-FI-NEXT: st1 { v0.2d }, [x1]
+; CHECK-FI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-FI-NEXT: add sp, sp, #32
+; CHECK-FI-NEXT: ret
%1 = load fp128, ptr %p
%2 = fadd fp128 %1, %1
%3 = bitcast fp128 %2 to <2 x i64>
@@ -891,10 +1438,14 @@ define void @test_v2i64_f128(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2i64_v2f64:
define void @test_v2i64_v2f64(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2d }
-; CHECK: st1 { v{{[0-9]+}}.2d }
+; CHECK-LABEL: test_v2i64_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: st1 { v0.2d }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x double>, ptr %p
%2 = fadd <2 x double> %1, %1
%3 = bitcast <2 x double> %2 to <2 x i64>
@@ -903,14 +1454,15 @@ define void @test_v2i64_v2f64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2i64_v4f32:
define void @test_v2i64_v4f32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4s }
-; CHECK-NOT: rev
-; CHECK: fadd
-; CHECK: rev64 v{{[0-9]+}}.4s
-; CHECK: add
-; CHECK: st1 { v{{[0-9]+}}.2d }
+; CHECK-LABEL: test_v2i64_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: st1 { v0.2d }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x float>, ptr %p
%2 = fadd <4 x float> %1, %1
%3 = bitcast <4 x float> %2 to <2 x i64>
@@ -919,11 +1471,15 @@ define void @test_v2i64_v4f32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2i64_v4i32:
define void @test_v2i64_v4i32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4s }
-; CHECK: rev64 v{{[0-9]+}}.4s
-; CHECK: st1 { v{{[0-9]+}}.2d }
+; CHECK-LABEL: test_v2i64_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: st1 { v0.2d }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x i32>, ptr %p
%2 = add <4 x i32> %1, %1
%3 = bitcast <4 x i32> %2 to <2 x i64>
@@ -932,11 +1488,15 @@ define void @test_v2i64_v4i32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2i64_v8i16:
define void @test_v2i64_v8i16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8h }
-; CHECK: rev64 v{{[0-9]+}}.8h
-; CHECK: st1 { v{{[0-9]+}}.2d }
+; CHECK-LABEL: test_v2i64_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.8h }, [x0]
+; CHECK-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: st1 { v0.2d }, [x1]
+; CHECK-NEXT: ret
%1 = load <8 x i16>, ptr %p
%2 = add <8 x i16> %1, %1
%3 = bitcast <8 x i16> %2 to <2 x i64>
@@ -945,11 +1505,15 @@ define void @test_v2i64_v8i16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v2i64_v16i8:
define void @test_v2i64_v16i8(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.16b }
-; CHECK: rev64 v{{[0-9]+}}.16b
-; CHECK: st1 { v{{[0-9]+}}.2d }
+; CHECK-LABEL: test_v2i64_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.16b }, [x0]
+; CHECK-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: st1 { v0.2d }, [x1]
+; CHECK-NEXT: ret
%1 = load <16 x i8>, ptr %p
%2 = add <16 x i8> %1, %1
%3 = bitcast <16 x i8> %2 to <2 x i64>
@@ -958,13 +1522,42 @@ define void @test_v2i64_v16i8(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f32_f128:
define void @test_v4f32_f128(ptr %p, ptr %q) {
-; CHECK: ldr q
-; CHECK: rev64 v{{[0-9]+}}.4s
-; CHECK: ext
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4s }
+; CHECK-SD-LABEL: test_v4f32_f128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w30, -16
+; CHECK-SD-NEXT: ldr q0, [x0]
+; CHECK-SD-NEXT: mov x19, x1
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: bl __addtf3
+; CHECK-SD-NEXT: rev64 v0.4s, v0.4s
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-SD-NEXT: st1 { v0.4s }, [x19]
+; CHECK-SD-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_v4f32_f128:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: sub sp, sp, #32
+; CHECK-FI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-FI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FI-NEXT: .cfi_offset w30, -16
+; CHECK-FI-NEXT: str x1, [sp, #8] // 8-byte Spill
+; CHECK-FI-NEXT: ldr q1, [x0]
+; CHECK-FI-NEXT: mov v0.16b, v1.16b
+; CHECK-FI-NEXT: bl __addtf3
+; CHECK-FI-NEXT: ldr x1, [sp, #8] // 8-byte Reload
+; CHECK-FI-NEXT: rev64 v0.4s, v0.4s
+; CHECK-FI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-FI-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-FI-NEXT: st1 { v0.4s }, [x1]
+; CHECK-FI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-FI-NEXT: add sp, sp, #32
+; CHECK-FI-NEXT: ret
%1 = load fp128, ptr %p
%2 = fadd fp128 %1, %1
%3 = bitcast fp128 %2 to <4 x float>
@@ -973,12 +1566,15 @@ define void @test_v4f32_f128(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f32_v2f64:
define void @test_v4f32_v2f64(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2d }
-; CHECK: rev64 v{{[0-9]+}}.4s
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4s }
+; CHECK-LABEL: test_v4f32_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: st1 { v0.4s }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x double>, ptr %p
%2 = fadd <2 x double> %1, %1
%3 = bitcast <2 x double> %2 to <4 x float>
@@ -987,13 +1583,15 @@ define void @test_v4f32_v2f64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f32_v2i64:
define void @test_v4f32_v2i64(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2d }
-; CHECK: rev64 v{{[0-9]+}}.4s
-; CHECK: fadd
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4s }
+; CHECK-LABEL: test_v4f32_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: st1 { v0.4s }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x i64>, ptr %p
%2 = add <2 x i64> %1, %1
%3 = bitcast <2 x i64> %2 to <4 x float>
@@ -1002,11 +1600,14 @@ define void @test_v4f32_v2i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f32_v4i32:
define void @test_v4f32_v4i32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4s }
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4s }
+; CHECK-LABEL: test_v4f32_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: st1 { v0.4s }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x i32>, ptr %p
%2 = add <4 x i32> %1, %1
%3 = bitcast <4 x i32> %2 to <4 x float>
@@ -1015,12 +1616,15 @@ define void @test_v4f32_v4i32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f32_v8i16:
define void @test_v4f32_v8i16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8h }
-; CHECK: rev32 v{{[0-9]+}}.8h
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4s }
+; CHECK-LABEL: test_v4f32_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.8h }, [x0]
+; CHECK-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: rev32 v0.8h, v0.8h
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: st1 { v0.4s }, [x1]
+; CHECK-NEXT: ret
%1 = load <8 x i16>, ptr %p
%2 = add <8 x i16> %1, %1
%3 = bitcast <8 x i16> %2 to <4 x float>
@@ -1029,12 +1633,15 @@ define void @test_v4f32_v8i16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f32_v16i8:
define void @test_v4f32_v16i8(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.16b }
-; CHECK: rev32 v{{[0-9]+}}.16b
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4s }
+; CHECK-LABEL: test_v4f32_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.16b }, [x0]
+; CHECK-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-NEXT: rev32 v0.16b, v0.16b
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: st1 { v0.4s }, [x1]
+; CHECK-NEXT: ret
%1 = load <16 x i8>, ptr %p
%2 = add <16 x i8> %1, %1
%3 = bitcast <16 x i8> %2 to <4 x float>
@@ -1043,12 +1650,42 @@ define void @test_v4f32_v16i8(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4i32_f128:
define void @test_v4i32_f128(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.4s
-; CHECK: ext
-; CHECK: st1 { v{{[0-9]+}}.4s }
+; CHECK-SD-LABEL: test_v4i32_f128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w30, -16
+; CHECK-SD-NEXT: ldr q0, [x0]
+; CHECK-SD-NEXT: mov x19, x1
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: bl __addtf3
+; CHECK-SD-NEXT: rev64 v0.4s, v0.4s
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-SD-NEXT: st1 { v0.4s }, [x19]
+; CHECK-SD-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_v4i32_f128:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: sub sp, sp, #32
+; CHECK-FI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-FI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FI-NEXT: .cfi_offset w30, -16
+; CHECK-FI-NEXT: str x1, [sp, #8] // 8-byte Spill
+; CHECK-FI-NEXT: ldr q1, [x0]
+; CHECK-FI-NEXT: mov v0.16b, v1.16b
+; CHECK-FI-NEXT: bl __addtf3
+; CHECK-FI-NEXT: ldr x1, [sp, #8] // 8-byte Reload
+; CHECK-FI-NEXT: rev64 v0.4s, v0.4s
+; CHECK-FI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-FI-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-FI-NEXT: st1 { v0.4s }, [x1]
+; CHECK-FI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-FI-NEXT: add sp, sp, #32
+; CHECK-FI-NEXT: ret
%1 = load fp128, ptr %p
%2 = fadd fp128 %1, %1
%3 = bitcast fp128 %2 to <4 x i32>
@@ -1057,11 +1694,15 @@ define void @test_v4i32_f128(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4i32_v2f64:
define void @test_v4i32_v2f64(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2d }
-; CHECK: rev64 v{{[0-9]+}}.4s
-; CHECK: st1 { v{{[0-9]+}}.4s }
+; CHECK-LABEL: test_v4i32_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: st1 { v0.4s }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x double>, ptr %p
%2 = fadd <2 x double> %1, %1
%3 = bitcast <2 x double> %2 to <4 x i32>
@@ -1070,11 +1711,15 @@ define void @test_v4i32_v2f64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4i32_v2i64:
define void @test_v4i32_v2i64(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2d }
-; CHECK: rev64 v{{[0-9]+}}.4s
-; CHECK: st1 { v{{[0-9]+}}.4s }
+; CHECK-LABEL: test_v4i32_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: st1 { v0.4s }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x i64>, ptr %p
%2 = add <2 x i64> %1, %1
%3 = bitcast <2 x i64> %2 to <4 x i32>
@@ -1083,11 +1728,14 @@ define void @test_v4i32_v2i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4i32_v4f32:
define void @test_v4i32_v4f32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4s }
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.4s }
+; CHECK-LABEL: test_v4i32_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: st1 { v0.4s }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x float>, ptr %p
%2 = fadd <4 x float> %1, %1
%3 = bitcast <4 x float> %2 to <4 x i32>
@@ -1096,11 +1744,15 @@ define void @test_v4i32_v4f32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4i32_v8i16:
define void @test_v4i32_v8i16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8h }
-; CHECK: rev32 v{{[0-9]+}}.8h
-; CHECK: st1 { v{{[0-9]+}}.4s }
+; CHECK-LABEL: test_v4i32_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.8h }, [x0]
+; CHECK-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: rev32 v0.8h, v0.8h
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: st1 { v0.4s }, [x1]
+; CHECK-NEXT: ret
%1 = load <8 x i16>, ptr %p
%2 = add <8 x i16> %1, %1
%3 = bitcast <8 x i16> %2 to <4 x i32>
@@ -1109,11 +1761,15 @@ define void @test_v4i32_v8i16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4i32_v16i8:
define void @test_v4i32_v16i8(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.16b }
-; CHECK: rev32 v{{[0-9]+}}.16b
-; CHECK: st1 { v{{[0-9]+}}.4s }
+; CHECK-LABEL: test_v4i32_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.16b }, [x0]
+; CHECK-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-NEXT: rev32 v0.16b, v0.16b
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: st1 { v0.4s }, [x1]
+; CHECK-NEXT: ret
%1 = load <16 x i8>, ptr %p
%2 = add <16 x i8> %1, %1
%3 = bitcast <16 x i8> %2 to <4 x i32>
@@ -1122,12 +1778,42 @@ define void @test_v4i32_v16i8(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v8i16_f128:
define void @test_v8i16_f128(ptr %p, ptr %q) {
-; CHECK: ldr
-; CHECK: rev64 v{{[0-9]+}}.8h
-; CHECK: ext
-; CHECK: st1 { v{{[0-9]+}}.8h }
+; CHECK-SD-LABEL: test_v8i16_f128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w30, -16
+; CHECK-SD-NEXT: ldr q0, [x0]
+; CHECK-SD-NEXT: mov x19, x1
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: bl __addtf3
+; CHECK-SD-NEXT: rev64 v0.8h, v0.8h
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-SD-NEXT: st1 { v0.8h }, [x19]
+; CHECK-SD-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_v8i16_f128:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: sub sp, sp, #32
+; CHECK-FI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-FI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FI-NEXT: .cfi_offset w30, -16
+; CHECK-FI-NEXT: str x1, [sp, #8] // 8-byte Spill
+; CHECK-FI-NEXT: ldr q1, [x0]
+; CHECK-FI-NEXT: mov v0.16b, v1.16b
+; CHECK-FI-NEXT: bl __addtf3
+; CHECK-FI-NEXT: ldr x1, [sp, #8] // 8-byte Reload
+; CHECK-FI-NEXT: rev64 v0.8h, v0.8h
+; CHECK-FI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-FI-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-FI-NEXT: st1 { v0.8h }, [x1]
+; CHECK-FI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-FI-NEXT: add sp, sp, #32
+; CHECK-FI-NEXT: ret
%1 = load fp128, ptr %p
%2 = fadd fp128 %1, %1
%3 = bitcast fp128 %2 to <8 x i16>
@@ -1136,11 +1822,15 @@ define void @test_v8i16_f128(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v8i16_v2f64:
define void @test_v8i16_v2f64(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2d }
-; CHECK: rev64 v{{[0-9]+}}.8h
-; CHECK: st1 { v{{[0-9]+}}.8h }
+; CHECK-LABEL: test_v8i16_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: st1 { v0.8h }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x double>, ptr %p
%2 = fadd <2 x double> %1, %1
%3 = bitcast <2 x double> %2 to <8 x i16>
@@ -1149,11 +1839,15 @@ define void @test_v8i16_v2f64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v8i16_v2i64:
define void @test_v8i16_v2i64(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2d }
-; CHECK: rev64 v{{[0-9]+}}.8h
-; CHECK: st1 { v{{[0-9]+}}.8h }
+; CHECK-LABEL: test_v8i16_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: st1 { v0.8h }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x i64>, ptr %p
%2 = add <2 x i64> %1, %1
%3 = bitcast <2 x i64> %2 to <8 x i16>
@@ -1162,12 +1856,15 @@ define void @test_v8i16_v2i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v8i16_v4f32:
define void @test_v8i16_v4f32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4s }
-; CHECK: rev32 v{{[0-9]+}}.8h
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.8h }
+; CHECK-LABEL: test_v8i16_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: rev32 v0.8h, v0.8h
+; CHECK-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: st1 { v0.8h }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x float>, ptr %p
%2 = fadd <4 x float> %1, %1
%3 = bitcast <4 x float> %2 to <8 x i16>
@@ -1176,11 +1873,15 @@ define void @test_v8i16_v4f32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v8i16_v4i32:
define void @test_v8i16_v4i32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4s }
-; CHECK: rev32 v{{[0-9]+}}.8h
-; CHECK: st1 { v{{[0-9]+}}.8h }
+; CHECK-LABEL: test_v8i16_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: rev32 v0.8h, v0.8h
+; CHECK-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: st1 { v0.8h }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x i32>, ptr %p
%2 = add <4 x i32> %1, %1
%3 = bitcast <4 x i32> %2 to <8 x i16>
@@ -1189,11 +1890,37 @@ define void @test_v8i16_v4i32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v8i16_v8f16:
define void @test_v8i16_v8f16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8h }
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.8h }
+; CHECK-SD-LABEL: test_v8i16_v8f16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ld1 { v0.8h }, [x0]
+; CHECK-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-SD-NEXT: mov d0, v0.d[1]
+; CHECK-SD-NEXT: fadd v1.4s, v1.4s, v1.4s
+; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-SD-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-SD-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-SD-NEXT: fcvtn2 v1.8h, v0.4s
+; CHECK-SD-NEXT: add v0.8h, v1.8h, v1.8h
+; CHECK-SD-NEXT: st1 { v0.8h }, [x1]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_v8i16_v8f16:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: ld1 { v1.8h }, [x0]
+; CHECK-FI-NEXT: fmov d0, d1
+; CHECK-FI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FI-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-FI-NEXT: fcvtn v2.4h, v0.4s
+; CHECK-FI-NEXT: // implicit-def: $q0
+; CHECK-FI-NEXT: fmov d0, d2
+; CHECK-FI-NEXT: mov d1, v1.d[1]
+; CHECK-FI-NEXT: fcvtl v1.4s, v1.4h
+; CHECK-FI-NEXT: fadd v1.4s, v1.4s, v1.4s
+; CHECK-FI-NEXT: fcvtn2 v0.8h, v1.4s
+; CHECK-FI-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-FI-NEXT: st1 { v0.8h }, [x1]
+; CHECK-FI-NEXT: ret
%1 = load <8 x half>, ptr %p
%2 = fadd <8 x half> %1, %1
%3 = bitcast <8 x half> %2 to <8 x i16>
@@ -1202,11 +1929,15 @@ define void @test_v8i16_v8f16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v8i16_v16i8:
define void @test_v8i16_v16i8(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.16b }
-; CHECK: rev16 v{{[0-9]+}}.16b
-; CHECK: st1 { v{{[0-9]+}}.8h }
+; CHECK-LABEL: test_v8i16_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.16b }, [x0]
+; CHECK-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-NEXT: rev16 v0.16b, v0.16b
+; CHECK-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: st1 { v0.8h }, [x1]
+; CHECK-NEXT: ret
%1 = load <16 x i8>, ptr %p
%2 = add <16 x i8> %1, %1
%3 = bitcast <16 x i8> %2 to <8 x i16>
@@ -1215,12 +1946,42 @@ define void @test_v8i16_v16i8(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v16i8_f128:
define void @test_v16i8_f128(ptr %p, ptr %q) {
-; CHECK: ldr q
-; CHECK: rev64 v{{[0-9]+}}.16b
-; CHECK: ext
-; CHECK: st1 { v{{[0-9]+}}.16b }
+; CHECK-SD-LABEL: test_v16i8_f128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w30, -16
+; CHECK-SD-NEXT: ldr q0, [x0]
+; CHECK-SD-NEXT: mov x19, x1
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: bl __addtf3
+; CHECK-SD-NEXT: rev64 v0.16b, v0.16b
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-SD-NEXT: st1 { v0.16b }, [x19]
+; CHECK-SD-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_v16i8_f128:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: sub sp, sp, #32
+; CHECK-FI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-FI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FI-NEXT: .cfi_offset w30, -16
+; CHECK-FI-NEXT: str x1, [sp, #8] // 8-byte Spill
+; CHECK-FI-NEXT: ldr q1, [x0]
+; CHECK-FI-NEXT: mov v0.16b, v1.16b
+; CHECK-FI-NEXT: bl __addtf3
+; CHECK-FI-NEXT: ldr x1, [sp, #8] // 8-byte Reload
+; CHECK-FI-NEXT: rev64 v0.16b, v0.16b
+; CHECK-FI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-FI-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-FI-NEXT: st1 { v0.16b }, [x1]
+; CHECK-FI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-FI-NEXT: add sp, sp, #32
+; CHECK-FI-NEXT: ret
%1 = load fp128, ptr %p
%2 = fadd fp128 %1, %1
%3 = bitcast fp128 %2 to <16 x i8>
@@ -1229,11 +1990,15 @@ define void @test_v16i8_f128(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v16i8_v2f64:
define void @test_v16i8_v2f64(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2d }
-; CHECK: rev64 v{{[0-9]+}}.16b
-; CHECK: st1 { v{{[0-9]+}}.16b }
+; CHECK-LABEL: test_v16i8_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-NEXT: fadd v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-NEXT: st1 { v0.16b }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x double>, ptr %p
%2 = fadd <2 x double> %1, %1
%3 = bitcast <2 x double> %2 to <16 x i8>
@@ -1242,11 +2007,15 @@ define void @test_v16i8_v2f64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v16i8_v2i64:
define void @test_v16i8_v2i64(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.2d }
-; CHECK: rev64 v{{[0-9]+}}.16b
-; CHECK: st1 { v{{[0-9]+}}.16b }
+; CHECK-LABEL: test_v16i8_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.2d }, [x0]
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-NEXT: st1 { v0.16b }, [x1]
+; CHECK-NEXT: ret
%1 = load <2 x i64>, ptr %p
%2 = add <2 x i64> %1, %1
%3 = bitcast <2 x i64> %2 to <16 x i8>
@@ -1255,12 +2024,15 @@ define void @test_v16i8_v2i64(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v16i8_v4f32:
define void @test_v16i8_v4f32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4s }
-; CHECK: rev32 v{{[0-9]+}}.16b
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.16b }
+; CHECK-LABEL: test_v16i8_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: rev32 v0.16b, v0.16b
+; CHECK-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-NEXT: st1 { v0.16b }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x float>, ptr %p
%2 = fadd <4 x float> %1, %1
%3 = bitcast <4 x float> %2 to <16 x i8>
@@ -1269,11 +2041,15 @@ define void @test_v16i8_v4f32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v16i8_v4i32:
define void @test_v16i8_v4i32(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.4s }
-; CHECK: rev32 v{{[0-9]+}}.16b
-; CHECK: st1 { v{{[0-9]+}}.16b }
+; CHECK-LABEL: test_v16i8_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.4s }, [x0]
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: rev32 v0.16b, v0.16b
+; CHECK-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-NEXT: st1 { v0.16b }, [x1]
+; CHECK-NEXT: ret
%1 = load <4 x i32>, ptr %p
%2 = add <4 x i32> %1, %1
%3 = bitcast <4 x i32> %2 to <16 x i8>
@@ -1282,12 +2058,39 @@ define void @test_v16i8_v4i32(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v16i8_v8f16:
define void @test_v16i8_v8f16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8h }
-; CHECK: rev16 v{{[0-9]+}}.16b
-; CHECK-NOT: rev
-; CHECK: st1 { v{{[0-9]+}}.16b }
+; CHECK-SD-LABEL: test_v16i8_v8f16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ld1 { v0.8h }, [x0]
+; CHECK-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-SD-NEXT: mov d0, v0.d[1]
+; CHECK-SD-NEXT: fadd v1.4s, v1.4s, v1.4s
+; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-SD-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-SD-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-SD-NEXT: fcvtn2 v1.8h, v0.4s
+; CHECK-SD-NEXT: rev16 v0.16b, v1.16b
+; CHECK-SD-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-SD-NEXT: st1 { v0.16b }, [x1]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_v16i8_v8f16:
+; CHECK-FI: // %bb.0:
+; CHECK-FI-NEXT: ld1 { v1.8h }, [x0]
+; CHECK-FI-NEXT: fmov d0, d1
+; CHECK-FI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FI-NEXT: fadd v0.4s, v0.4s, v0.4s
+; CHECK-FI-NEXT: fcvtn v2.4h, v0.4s
+; CHECK-FI-NEXT: // implicit-def: $q0
+; CHECK-FI-NEXT: fmov d0, d2
+; CHECK-FI-NEXT: mov d1, v1.d[1]
+; CHECK-FI-NEXT: fcvtl v1.4s, v1.4h
+; CHECK-FI-NEXT: fadd v1.4s, v1.4s, v1.4s
+; CHECK-FI-NEXT: fcvtn2 v0.8h, v1.4s
+; CHECK-FI-NEXT: rev16 v0.16b, v0.16b
+; CHECK-FI-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-FI-NEXT: st1 { v0.16b }, [x1]
+; CHECK-FI-NEXT: ret
%1 = load <8 x half>, ptr %p
%2 = fadd <8 x half> %1, %1
%3 = bitcast <8 x half> %2 to <16 x i8>
@@ -1296,11 +2099,15 @@ define void @test_v16i8_v8f16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v16i8_v8i16:
define void @test_v16i8_v8i16(ptr %p, ptr %q) {
-; CHECK: ld1 { v{{[0-9]+}}.8h }
-; CHECK: rev16 v{{[0-9]+}}.16b
-; CHECK: st1 { v{{[0-9]+}}.16b }
+; CHECK-LABEL: test_v16i8_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1 { v0.8h }, [x0]
+; CHECK-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: rev16 v0.16b, v0.16b
+; CHECK-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-NEXT: st1 { v0.16b }, [x1]
+; CHECK-NEXT: ret
%1 = load <8 x i16>, ptr %p
%2 = add <8 x i16> %1, %1
%3 = bitcast <8 x i16> %2 to <16 x i8>
@@ -1309,14 +2116,75 @@ define void @test_v16i8_v8i16(ptr %p, ptr %q) {
ret void
}
-; CHECK-LABEL: test_v4f16_struct:
%struct.struct1 = type { half, half, half, half }
define %struct.struct1 @test_v4f16_struct(ptr %ret) {
+; CHECK-SD-LABEL: test_v4f16_struct:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ld1 { v0.4h }, [x0]
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: test_v4f16_struct:
+; CHECK-FI: // %bb.0: // %entry
+; CHECK-FI-NEXT: ld1 { v1.4h }, [x0]
+; CHECK-FI-NEXT: // implicit-def: $q0
+; CHECK-FI-NEXT: fmov d0, d1
+; CHECK-FI-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-FI-NEXT: // implicit-def: $h1
+; CHECK-FI-NEXT: // implicit-def: $h2
+; CHECK-FI-NEXT: // implicit-def: $h3
+; CHECK-FI-NEXT: ret
entry:
-; CHECK: ld1 { {{v[0-9]+}}.4h }
-; CHECK-NOT: rev
%0 = load <4 x half>, ptr %ret, align 2
%1 = extractelement <4 x half> %0, i32 0
%.fca.0.insert = insertvalue %struct.struct1 undef, half %1, 0
ret %struct.struct1 %.fca.0.insert
}
+
+define i8 @zextbitconvert_v8i8(i32 %x) {
+; CHECK-SD-LABEL: zextbitconvert_v8i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fmov s0, w0
+; CHECK-SD-NEXT: umov w0, v0.b[4]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: zextbitconvert_v8i8:
+; CHECK-FI: // %bb.0: // %entry
+; CHECK-FI-NEXT: fmov s0, w0
+; CHECK-FI-NEXT: fmov s1, s0
+; CHECK-FI-NEXT: // implicit-def: $q0
+; CHECK-FI-NEXT: fmov d0, d1
+; CHECK-FI-NEXT: umov w0, v0.b[4]
+; CHECK-FI-NEXT: ret
+entry:
+ %z = zext i32 %x to i64
+ %v = bitcast i64 %z to <8 x i8>
+ %r = extractelement <8 x i8> %v, i32 4
+ ret i8 %r
+}
+
+define i16 @zextbitconvert_v4i16(i32 %x) {
+; CHECK-SD-LABEL: zextbitconvert_v4i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov w8, w0
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: rev64 v0.4h, v0.4h
+; CHECK-SD-NEXT: umov w0, v0.h[2]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-FI-LABEL: zextbitconvert_v4i16:
+; CHECK-FI: // %bb.0: // %entry
+; CHECK-FI-NEXT: mov w8, w0
+; CHECK-FI-NEXT: mov w0, w8
+; CHECK-FI-NEXT: fmov d0, x0
+; CHECK-FI-NEXT: rev64 v1.4h, v0.4h
+; CHECK-FI-NEXT: // implicit-def: $q0
+; CHECK-FI-NEXT: fmov d0, d1
+; CHECK-FI-NEXT: umov w0, v0.h[2]
+; CHECK-FI-NEXT: ret
+entry:
+ %z = zext i32 %x to i64
+ %v = bitcast i64 %z to <4 x i16>
+ %r = extractelement <4 x i16> %v, i32 2
+ ret i16 %r
+}
diff --git a/llvm/test/CodeGen/AArch64/arm64-popcnt.ll b/llvm/test/CodeGen/AArch64/arm64-popcnt.ll
index 3d6cc814d157d..2f5b769ca1a08 100644
--- a/llvm/test/CodeGen/AArch64/arm64-popcnt.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-popcnt.ll
@@ -414,7 +414,7 @@ define i1 @ctpop32_ne_one_nonzero(i32 %x) {
; CHECK-CSSC-LABEL: ctpop32_ne_one_nonzero:
; CHECK-CSSC: // %bb.0: // %entry
; CHECK-CSSC-NEXT: sub w8, w0, #1
-; CHECK-CSSC-NEXT: and w8, w0, w8
+; CHECK-CSSC-NEXT: and w8, w0, w8
; CHECK-CSSC-NEXT: umin w0, w8, #1
; CHECK-CSSC-NEXT: ret
;
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