[llvm] [SimpleLoopUnswitch] Do not speculate loads past potentially non-returning on partial switch (PR #222077)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 8 10:52:21 PDT 2026
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/222077
>From cfd940e56f7bfd99497d30ac2c9d4cd924111e1d Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 8 Sep 2026 13:18:01 -0400
Subject: [PATCH 1/2] [SimpleLoopUnswitch] Pre-commit test for partial unswitch
speculation safety (NFC)
---
.../partial-unswitch-speculation-safety.ll | 221 ++++++++++++++++++
1 file changed, 221 insertions(+)
create mode 100644 llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-speculation-safety.ll
diff --git a/llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-speculation-safety.ll b/llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-speculation-safety.ll
new file mode 100644
index 0000000000000..f17c71e687d77
--- /dev/null
+++ b/llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-speculation-safety.ll
@@ -0,0 +1,221 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals
+; RUN: opt -passes='loop-mssa(simple-loop-unswitch<nontrivial>),verify<loops>' -S < %s | FileCheck %s
+
+declare void @barrier() memory(read)
+declare void @clobber()
+
+; The load is after a call to @barrier() which may not return.
+; The load should NOT be hoisted to the preheader because it is
+; not guaranteed to execute and not safe to speculate.
+define i32 @no_partial_unswitch_after_non_returning_call(ptr %ptr, i32 %N) {
+; CHECK-LABEL: @no_partial_unswitch_after_non_returning_call(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 100
+; CHECK-NEXT: br i1 [[TMP1]], label [[ENTRY_SPLIT_US:%.*]], label [[ENTRY:%.*]]
+; CHECK: entry.split.us:
+; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
+; CHECK: loop.header.us:
+; CHECK-NEXT: [[IV_US:%.*]] = phi i32 [ 0, [[ENTRY_SPLIT_US]] ], [ [[IV_NEXT_US:%.*]], [[LOOP_LATCH_US:%.*]] ]
+; CHECK-NEXT: call void @barrier()
+; CHECK-NEXT: br label [[NOCLOBBER_US:%.*]]
+; CHECK: noclobber.us:
+; CHECK-NEXT: br label [[LOOP_LATCH_US]]
+; CHECK: loop.latch.us:
+; CHECK-NEXT: [[C_US:%.*]] = icmp ult i32 [[IV_US]], [[N:%.*]]
+; CHECK-NEXT: [[IV_NEXT_US]] = add i32 [[IV_US]], 1
+; CHECK-NEXT: br i1 [[C_US]], label [[LOOP_HEADER]], label [[EXIT_SPLIT_US:%.*]]
+; CHECK: exit.split.us:
+; CHECK-NEXT: br label [[EXIT:%.*]]
+; CHECK: entry.split:
+; CHECK-NEXT: br label [[LOOP_HEADER1:%.*]]
+; CHECK: loop.header:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
+; CHECK-NEXT: call void @barrier()
+; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT: [[SC:%.*]] = icmp eq i32 [[LV]], 100
+; CHECK-NEXT: br i1 [[SC]], label [[NOCLOBBER:%.*]], label [[CLOBBER:%.*]]
+; CHECK: noclobber:
+; CHECK-NEXT: br label [[LOOP_LATCH]]
+; CHECK: clobber:
+; CHECK-NEXT: call void @clobber()
+; CHECK-NEXT: br label [[LOOP_LATCH]]
+; CHECK: loop.latch:
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV]], [[N]]
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: br i1 [[C]], label [[LOOP_HEADER1]], label [[EXIT_SPLIT:%.*]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: exit.split:
+; CHECK-NEXT: br label [[EXIT]]
+; CHECK: exit:
+; CHECK-NEXT: ret i32 10
+;
+entry:
+ br label %loop.header
+
+loop.header:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
+ call void @barrier()
+ %lv = load i32, ptr %ptr
+ %sc = icmp eq i32 %lv, 100
+ br i1 %sc, label %noclobber, label %clobber
+
+noclobber:
+ br label %loop.latch
+
+clobber:
+ call void @clobber()
+ br label %loop.latch
+
+loop.latch:
+ %c = icmp ult i32 %iv, %N
+ %iv.next = add i32 %iv, 1
+ br i1 %c, label %loop.header, label %exit
+
+exit:
+ ret i32 10
+}
+
+; The load is before any non-returning call, so it is guaranteed to execute.
+; Partial unswitching should still work here.
+define i32 @partial_unswitch_guaranteed_to_execute(ptr %ptr, i32 %N) {
+; CHECK-LABEL: @partial_unswitch_guaranteed_to_execute(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 100
+; CHECK-NEXT: br i1 [[TMP1]], label [[ENTRY_SPLIT_US:%.*]], label [[ENTRY_SPLIT:%.*]]
+; CHECK: entry.split.us:
+; CHECK-NEXT: br label [[LOOP_HEADER_US:%.*]]
+; CHECK: loop.header.us:
+; CHECK-NEXT: [[IV_US:%.*]] = phi i32 [ 0, [[ENTRY_SPLIT_US]] ], [ [[IV_NEXT_US:%.*]], [[LOOP_LATCH_US:%.*]] ]
+; CHECK-NEXT: br label [[NOCLOBBER_US:%.*]]
+; CHECK: noclobber.us:
+; CHECK-NEXT: br label [[LOOP_LATCH_US]]
+; CHECK: loop.latch.us:
+; CHECK-NEXT: [[C_US:%.*]] = icmp ult i32 [[IV_US]], [[N:%.*]]
+; CHECK-NEXT: [[IV_NEXT_US]] = add i32 [[IV_US]], 1
+; CHECK-NEXT: br i1 [[C_US]], label [[LOOP_HEADER_US]], label [[EXIT_SPLIT_US:%.*]]
+; CHECK: exit.split.us:
+; CHECK-NEXT: br label [[EXIT:%.*]]
+; CHECK: entry.split:
+; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
+; CHECK: loop.header:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY_SPLIT]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
+; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT: [[SC:%.*]] = icmp eq i32 [[LV]], 100
+; CHECK-NEXT: br i1 [[SC]], label [[NOCLOBBER:%.*]], label [[CLOBBER:%.*]]
+; CHECK: noclobber:
+; CHECK-NEXT: br label [[LOOP_LATCH]]
+; CHECK: clobber:
+; CHECK-NEXT: call void @clobber()
+; CHECK-NEXT: br label [[LOOP_LATCH]]
+; CHECK: loop.latch:
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV]], [[N]]
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: br i1 [[C]], label [[LOOP_HEADER]], label [[EXIT_SPLIT:%.*]], !llvm.loop [[LOOP2:![0-9]+]]
+; CHECK: exit.split:
+; CHECK-NEXT: br label [[EXIT]]
+; CHECK: exit:
+; CHECK-NEXT: ret i32 10
+;
+entry:
+ br label %loop.header
+
+loop.header:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
+ %lv = load i32, ptr %ptr
+ %sc = icmp eq i32 %lv, 100
+ br i1 %sc, label %noclobber, label %clobber
+
+noclobber:
+ br label %loop.latch
+
+clobber:
+ call void @clobber()
+ br label %loop.latch
+
+loop.latch:
+ %c = icmp ult i32 %iv, %N
+ %iv.next = add i32 %iv, 1
+ br i1 %c, label %loop.header, label %exit
+
+exit:
+ ret i32 10
+}
+
+; The load is from a dereferenceable pointer, so isSafeToSpeculativelyExecute
+; should allow it even after a non-returning call.
+define i32 @partial_unswitch_deref_ptr_after_non_returning_call(ptr dereferenceable(4) %ptr, i32 %N) {
+; CHECK-LABEL: @partial_unswitch_deref_ptr_after_non_returning_call(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 100
+; CHECK-NEXT: br i1 [[TMP1]], label [[ENTRY_SPLIT_US:%.*]], label [[ENTRY:%.*]]
+; CHECK: entry.split.us:
+; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
+; CHECK: loop.header.us:
+; CHECK-NEXT: [[IV_US:%.*]] = phi i32 [ 0, [[ENTRY_SPLIT_US]] ], [ [[IV_NEXT_US:%.*]], [[LOOP_LATCH_US:%.*]] ]
+; CHECK-NEXT: call void @barrier()
+; CHECK-NEXT: br label [[NOCLOBBER_US:%.*]]
+; CHECK: noclobber.us:
+; CHECK-NEXT: br label [[LOOP_LATCH_US]]
+; CHECK: loop.latch.us:
+; CHECK-NEXT: [[C_US:%.*]] = icmp ult i32 [[IV_US]], [[N:%.*]]
+; CHECK-NEXT: [[IV_NEXT_US]] = add i32 [[IV_US]], 1
+; CHECK-NEXT: br i1 [[C_US]], label [[LOOP_HEADER]], label [[EXIT_SPLIT_US:%.*]]
+; CHECK: exit.split.us:
+; CHECK-NEXT: br label [[EXIT:%.*]]
+; CHECK: entry.split:
+; CHECK-NEXT: br label [[LOOP_HEADER1:%.*]]
+; CHECK: loop.header:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
+; CHECK-NEXT: call void @barrier()
+; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT: [[SC:%.*]] = icmp eq i32 [[LV]], 100
+; CHECK-NEXT: br i1 [[SC]], label [[NOCLOBBER:%.*]], label [[CLOBBER:%.*]]
+; CHECK: noclobber:
+; CHECK-NEXT: br label [[LOOP_LATCH]]
+; CHECK: clobber:
+; CHECK-NEXT: call void @clobber()
+; CHECK-NEXT: br label [[LOOP_LATCH]]
+; CHECK: loop.latch:
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV]], [[N]]
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: br i1 [[C]], label [[LOOP_HEADER1]], label [[EXIT_SPLIT:%.*]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: exit.split:
+; CHECK-NEXT: br label [[EXIT]]
+; CHECK: exit:
+; CHECK-NEXT: ret i32 10
+;
+entry:
+ br label %loop.header
+
+loop.header:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
+ call void @barrier()
+ %lv = load i32, ptr %ptr
+ %sc = icmp eq i32 %lv, 100
+ br i1 %sc, label %noclobber, label %clobber
+
+noclobber:
+ br label %loop.latch
+
+clobber:
+ call void @clobber()
+ br label %loop.latch
+
+loop.latch:
+ %c = icmp ult i32 %iv, %N
+ %iv.next = add i32 %iv, 1
+ br i1 %c, label %loop.header, label %exit
+
+exit:
+ ret i32 10
+}
+;.
+; CHECK: attributes #[[ATTR0:[0-9]+]] = { memory(read) }
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.unswitch.partial.disable"}
+; CHECK: [[LOOP2]] = distinct !{[[LOOP2]], [[META1]]}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+;.
>From f46e154a3f1943f79a99b966a60ff40c34e3a78e Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 8 Sep 2026 13:20:21 -0400
Subject: [PATCH 2/2] [SimpleLoopUnswitch] Do not speculate loads past
potentially non-returning calls in partial unswitch
hasPartialIVCondition collects instructions from the loop header to
duplicate into the preheader for partial unswitching. While it checked
for memory clobbers via MemorySSA, it did not verify that the
instructions are safe to speculatively execute when hoisted.
This could lead to hoisting a load past a call that might not return
(e.g. a barrier), introducing a fault that would not have occurred in
the original program.
Add a check that each instruction to duplicate is either safe to
speculatively execute (isSafeToSpeculativelyExecute) or guaranteed to
execute on every loop iteration (isGuaranteedToExecuteForEveryIteration).
Either condition is sufficient to justify moving the instruction to the
preheader.
Fixes https://github.com/llvm/llvm-project/issues/219510
---
llvm/lib/Transforms/Utils/LoopUtils.cpp | 10 ++
.../partial-unswitch-speculation-safety.ll | 102 +-----------------
2 files changed, 15 insertions(+), 97 deletions(-)
diff --git a/llvm/lib/Transforms/Utils/LoopUtils.cpp b/llvm/lib/Transforms/Utils/LoopUtils.cpp
index d3f2f0beacc6a..710c4697ca352 100644
--- a/llvm/lib/Transforms/Utils/LoopUtils.cpp
+++ b/llvm/lib/Transforms/Utils/LoopUtils.cpp
@@ -30,6 +30,9 @@
#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/Analysis/ScalarEvolutionAliasAnalysis.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DIBuilder.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/Instructions.h"
@@ -2403,6 +2406,13 @@ llvm::hasPartialIVCondition(const Loop &L, unsigned MSSAThreshold,
if (LI->isVolatile() || LI->isAtomic())
return {};
+ // TODO: Plumb AssumptionCache and DominatorTree into this function and
+ // pass them to isSafeToSpeculativelyExecute to enable more aggressive
+ // speculation (e.g. for dereferenceable pointers).
+ if (!isSafeToSpeculativelyExecute(I) &&
+ !isGuaranteedToExecuteForEveryIteration(I, &L))
+ return {};
+
InstToDuplicate.push_back(I);
if (MemoryAccess *MA = MSSA.getMemoryAccess(I)) {
if (auto *MemUse = dyn_cast_or_null<MemoryUse>(MA)) {
diff --git a/llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-speculation-safety.ll b/llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-speculation-safety.ll
index f17c71e687d77..5bf609e140692 100644
--- a/llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-speculation-safety.ll
+++ b/llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-speculation-safety.ll
@@ -10,29 +10,11 @@ declare void @clobber()
define i32 @no_partial_unswitch_after_non_returning_call(ptr %ptr, i32 %N) {
; CHECK-LABEL: @no_partial_unswitch_after_non_returning_call(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[PTR:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 100
-; CHECK-NEXT: br i1 [[TMP1]], label [[ENTRY_SPLIT_US:%.*]], label [[ENTRY:%.*]]
-; CHECK: entry.split.us:
-; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
-; CHECK: loop.header.us:
-; CHECK-NEXT: [[IV_US:%.*]] = phi i32 [ 0, [[ENTRY_SPLIT_US]] ], [ [[IV_NEXT_US:%.*]], [[LOOP_LATCH_US:%.*]] ]
-; CHECK-NEXT: call void @barrier()
-; CHECK-NEXT: br label [[NOCLOBBER_US:%.*]]
-; CHECK: noclobber.us:
-; CHECK-NEXT: br label [[LOOP_LATCH_US]]
-; CHECK: loop.latch.us:
-; CHECK-NEXT: [[C_US:%.*]] = icmp ult i32 [[IV_US]], [[N:%.*]]
-; CHECK-NEXT: [[IV_NEXT_US]] = add i32 [[IV_US]], 1
-; CHECK-NEXT: br i1 [[C_US]], label [[LOOP_HEADER]], label [[EXIT_SPLIT_US:%.*]]
-; CHECK: exit.split.us:
-; CHECK-NEXT: br label [[EXIT:%.*]]
-; CHECK: entry.split:
; CHECK-NEXT: br label [[LOOP_HEADER1:%.*]]
; CHECK: loop.header:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
; CHECK-NEXT: call void @barrier()
-; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: [[SC:%.*]] = icmp eq i32 [[LV]], 100
; CHECK-NEXT: br i1 [[SC]], label [[NOCLOBBER:%.*]], label [[CLOBBER:%.*]]
; CHECK: noclobber:
@@ -41,11 +23,9 @@ define i32 @no_partial_unswitch_after_non_returning_call(ptr %ptr, i32 %N) {
; CHECK-NEXT: call void @clobber()
; CHECK-NEXT: br label [[LOOP_LATCH]]
; CHECK: loop.latch:
-; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV]], [[N]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV]], [[N:%.*]]
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
-; CHECK-NEXT: br i1 [[C]], label [[LOOP_HEADER1]], label [[EXIT_SPLIT:%.*]], !llvm.loop [[LOOP0:![0-9]+]]
-; CHECK: exit.split:
-; CHECK-NEXT: br label [[EXIT]]
+; CHECK-NEXT: br i1 [[C]], label [[LOOP_HEADER1]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret i32 10
;
@@ -111,76 +91,7 @@ define i32 @partial_unswitch_guaranteed_to_execute(ptr %ptr, i32 %N) {
; CHECK: loop.latch:
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV]], [[N]]
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
-; CHECK-NEXT: br i1 [[C]], label [[LOOP_HEADER]], label [[EXIT_SPLIT:%.*]], !llvm.loop [[LOOP2:![0-9]+]]
-; CHECK: exit.split:
-; CHECK-NEXT: br label [[EXIT]]
-; CHECK: exit:
-; CHECK-NEXT: ret i32 10
-;
-entry:
- br label %loop.header
-
-loop.header:
- %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
- %lv = load i32, ptr %ptr
- %sc = icmp eq i32 %lv, 100
- br i1 %sc, label %noclobber, label %clobber
-
-noclobber:
- br label %loop.latch
-
-clobber:
- call void @clobber()
- br label %loop.latch
-
-loop.latch:
- %c = icmp ult i32 %iv, %N
- %iv.next = add i32 %iv, 1
- br i1 %c, label %loop.header, label %exit
-
-exit:
- ret i32 10
-}
-
-; The load is from a dereferenceable pointer, so isSafeToSpeculativelyExecute
-; should allow it even after a non-returning call.
-define i32 @partial_unswitch_deref_ptr_after_non_returning_call(ptr dereferenceable(4) %ptr, i32 %N) {
-; CHECK-LABEL: @partial_unswitch_deref_ptr_after_non_returning_call(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[PTR:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 100
-; CHECK-NEXT: br i1 [[TMP1]], label [[ENTRY_SPLIT_US:%.*]], label [[ENTRY:%.*]]
-; CHECK: entry.split.us:
-; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
-; CHECK: loop.header.us:
-; CHECK-NEXT: [[IV_US:%.*]] = phi i32 [ 0, [[ENTRY_SPLIT_US]] ], [ [[IV_NEXT_US:%.*]], [[LOOP_LATCH_US:%.*]] ]
-; CHECK-NEXT: call void @barrier()
-; CHECK-NEXT: br label [[NOCLOBBER_US:%.*]]
-; CHECK: noclobber.us:
-; CHECK-NEXT: br label [[LOOP_LATCH_US]]
-; CHECK: loop.latch.us:
-; CHECK-NEXT: [[C_US:%.*]] = icmp ult i32 [[IV_US]], [[N:%.*]]
-; CHECK-NEXT: [[IV_NEXT_US]] = add i32 [[IV_US]], 1
-; CHECK-NEXT: br i1 [[C_US]], label [[LOOP_HEADER]], label [[EXIT_SPLIT_US:%.*]]
-; CHECK: exit.split.us:
-; CHECK-NEXT: br label [[EXIT:%.*]]
-; CHECK: entry.split:
-; CHECK-NEXT: br label [[LOOP_HEADER1:%.*]]
-; CHECK: loop.header:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
-; CHECK-NEXT: call void @barrier()
-; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[PTR]], align 4
-; CHECK-NEXT: [[SC:%.*]] = icmp eq i32 [[LV]], 100
-; CHECK-NEXT: br i1 [[SC]], label [[NOCLOBBER:%.*]], label [[CLOBBER:%.*]]
-; CHECK: noclobber:
-; CHECK-NEXT: br label [[LOOP_LATCH]]
-; CHECK: clobber:
-; CHECK-NEXT: call void @clobber()
-; CHECK-NEXT: br label [[LOOP_LATCH]]
-; CHECK: loop.latch:
-; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV]], [[N]]
-; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
-; CHECK-NEXT: br i1 [[C]], label [[LOOP_HEADER1]], label [[EXIT_SPLIT:%.*]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-NEXT: br i1 [[C]], label [[LOOP_HEADER]], label [[EXIT_SPLIT:%.*]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: exit.split:
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
@@ -191,7 +102,6 @@ entry:
loop.header:
%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
- call void @barrier()
%lv = load i32, ptr %ptr
%sc = icmp eq i32 %lv, 100
br i1 %sc, label %noclobber, label %clobber
@@ -216,6 +126,4 @@ exit:
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.unswitch.partial.disable"}
-; CHECK: [[LOOP2]] = distinct !{[[LOOP2]], [[META1]]}
-; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
;.
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