[llvm] [AMDGPU] Prevent VOP3 from receiving 64b relocations as immediates (PR #221932)

[Carl Ritson via llvm-commits]

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@@ -5032,6 +5032,20 @@ bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
 
   assert((MO.isTargetIndex() || MO.isFI() || MO.isGlobal()) &&
          "unexpected imm-like operand kind");
+
+  // VOP3 instructions do not support 64b literals so cannot support 64b relocs
+  if (MO.isGlobal() && SIInstrFlags::isVOP3Like(InstDesc)) {
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perlfu wrote:

The operand types have no modelling of this.  For example the operand type can be `AMDGPU::OPERAND_REG_IMM_INT64` (for VOP3 `V_MAD_U64_U32`).  Which implies that any i64 register or immediate is valid; when it is not.

Are you asking me to do this by implementing new operand types, e.g. `OPERAND_REG_IMM_INT64_NOLIT64`, `OPERAND_REG_IMM_FP64_NOLIT64`, etc.  And fix this all down through the operand encodings?

https://github.com/llvm/llvm-project/pull/221932