[llvm] [AMDGPU] Reject 64-bit VOP1 DPP on gfx8/gfx9 (PR #220834)

[Arseniy Obolenskiy via llvm-commits]

https://github.com/aobolensk updated https://github.com/llvm/llvm-project/pull/220834

>From 6689de12312b70c73cf8893a6c5c62136f6a16db Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Thu, 3 Sep 2026 09:47:47 +0200
Subject: [PATCH 1/2] [AMDGPU] Reject 64-bit VOP1 DPP on gfx8/gfx9

64-bit DPP needs FeatureDPALU_DPP (gfx90a+), but the VOP1_Real_vi AssemblerPredicate override dropped that gate from the pseudo
---
 llvm/lib/Target/AMDGPU/VOP1Instructions.td         |  5 +++++
 llvm/test/MC/AMDGPU/dpp-err.s                      | 14 ++++++++++++++
 llvm/test/MC/AMDGPU/gfx9-asm-err.s                 |  2 +-
 llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt |  7 +++++++
 4 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index ed1f38afc298d..8f164767331d3 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -1642,6 +1642,11 @@ multiclass VOP1_Real_vi <bits<10> op> {
       VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>,
       VOP1_DPPe<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp")> {
         let AssemblerPredicate = isGFX8GFX9;
+        // The override above drops the pseudo HasDPALU_DPP AssemblerPredicate.
+        let OtherPredicates = !listconcat(
+            !cast<VOP1_DPP_Pseudo>(NAME#"_dpp").OtherPredicates,
+            !if(!cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExt64BitDPP,
+                [HasDPALU_DPP], []));
       }
 }
 
diff --git a/llvm/test/MC/AMDGPU/dpp-err.s b/llvm/test/MC/AMDGPU/dpp-err.s
index 16fdf5cef0e4e..29533bc69f1a6 100644
--- a/llvm/test/MC/AMDGPU/dpp-err.s
+++ b/llvm/test/MC/AMDGPU/dpp-err.s
@@ -36,3 +36,17 @@ v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1
 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1
 // GFX89:     v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x01,0x43,0x01,0x11]
 // GFX10-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
+
+// DPP with a 64-bit VGPR operand requires gfx90a+ (FeatureDPALU_DPP).
+
+v_cvt_f64_i32_dpp v[0:1], v2 quad_perm:[2,3,0,1] row_mask:0x1 bank_mask:0x1
+// GFX89-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
+// GFX10-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
+
+v_cvt_f64_u32_dpp v[0:1], v2 quad_perm:[2,3,0,1] row_mask:0x1 bank_mask:0x1
+// GFX89-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
+// GFX10-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
+
+v_cvt_f64_f32_dpp v[0:1], v2 quad_perm:[2,3,0,1] row_mask:0x1 bank_mask:0x1
+// GFX89-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
+// GFX10-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
diff --git a/llvm/test/MC/AMDGPU/gfx9-asm-err.s b/llvm/test/MC/AMDGPU/gfx9-asm-err.s
index cef5e7d8fc6e6..2fcf793befbe3 100644
--- a/llvm/test/MC/AMDGPU/gfx9-asm-err.s
+++ b/llvm/test/MC/AMDGPU/gfx9-asm-err.s
@@ -38,7 +38,7 @@ v_cvt_f16_u16_e64 v5, 0.6
 // GFX9ERR: :[[@LINE-1]]:23: error: literal operands are not supported
 
 v_cvt_u32_f64 v5, v[0:1] quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf
-// GFX9ERR: :[[@LINE-1]]:19: error: invalid operand for instruction
+// GFX9ERR: :[[@LINE-1]]:26: error: not a valid operand.
 
 v_subrev_u16_e64 v5, v1, -4.2
 // GFX9ERR: :[[@LINE-1]]:26: error: literal operands are not supported
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
index 6f35752b8e492..6a1f9e577a40d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
@@ -22,3 +22,10 @@
 
 0xf9,0x04,0x00,0x02,0x01,0x06,0x06,0x07
 # GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# v_cvt_f64_i32_dpp and v_ceil_f64_dpp: 64-bit VGPR DPP needs gfx90a+.
+0xfa,0x08,0x00,0x7e,0x02,0x4e,0x00,0xff
+# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+0xfa,0x30,0x00,0x7e,0x02,0x4e,0x00,0xff
+# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding

>From 4a754775ca81f3f7de7bbf5f9e75238b0522bd92 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Tue, 8 Sep 2026 14:09:45 +0200
Subject: [PATCH 2/2] rework

---
 llvm/lib/Target/AMDGPU/VOP1Instructions.td | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 8f164767331d3..2f19a18e6a423 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -1642,11 +1642,9 @@ multiclass VOP1_Real_vi <bits<10> op> {
       VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>,
       VOP1_DPPe<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp")> {
         let AssemblerPredicate = isGFX8GFX9;
-        // The override above drops the pseudo HasDPALU_DPP AssemblerPredicate.
-        let OtherPredicates = !listconcat(
-            !cast<VOP1_DPP_Pseudo>(NAME#"_dpp").OtherPredicates,
+        let OtherPredicates =
             !if(!cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExt64BitDPP,
-                [HasDPALU_DPP], []));
+                [HasDPALU_DPP], []);
       }
 }