[llvm] [AMDGPU][GlobalISel] Fix full width BFX and out of range BFE width (PR #220911)
Arseniy Obolenskiy via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 8 04:13:12 PDT 2026
https://github.com/aobolensk updated https://github.com/llvm/llvm-project/pull/220911
>From e0a65c748218e27898d14218ea80c7bd38d85f52 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Thu, 3 Sep 2026 14:31:52 +0200
Subject: [PATCH 1/2] [AMDGPU][GlobalISel] Fix full width BFX and out of range
BFE width
G_UBFX/G_SBFX allow a width equal to the result size, which no BFE width field can encode, while llvm.amdgcn.{s,u}bfe take width and offset modulo the result size
---
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 85 +-
.../AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll | 834 +++++++++++++++-
.../AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll | 913 +++++++++++++++++-
.../AMDGPU/GlobalISel/regbankselect-sbfx.mir | 107 +-
.../AMDGPU/GlobalISel/regbankselect-ubfx.mir | 107 +-
5 files changed, 1976 insertions(+), 70 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index a9eda0a8406a2..1e9d92ed5fbf8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -714,11 +714,36 @@ static bool isSignedBFE(MachineInstr &MI) {
return MI.getOpcode() == AMDGPU::G_SBFX;
}
+// Width == result size is legal for BFX but unencodable in a BFE width field.
+static bool tryLowerFullWidthBFX(MachineIRBuilder &B, MachineInstr &MI,
+ MachineRegisterInfo &MRI) {
+ if (isa<GIntrinsic>(MI))
+ return false;
+
+ // Not an intrinsic, so the operands are Dst, Src, LSBit, Width.
+ Register Dst = MI.getOperand(0).getReg();
+ auto ConstWidth =
+ getIConstantVRegValWithLookThrough(MI.getOperand(3).getReg(), MRI);
+ // Width above the result size is out of contract, lower it as full width.
+ if (!ConstWidth ||
+ ConstWidth->Value.getZExtValue() < MRI.getType(Dst).getSizeInBits())
+ return false;
+
+ B.buildInstr(isSignedBFE(MI) ? AMDGPU::G_ASHR : AMDGPU::G_LSHR, {Dst},
+ {MI.getOperand(1).getReg(), MI.getOperand(2).getReg()});
+ MI.eraseFromParent();
+ return true;
+}
+
bool RegBankLegalizeHelper::lowerV_BFE(MachineInstr &MI) {
Register Dst = MI.getOperand(0).getReg();
assert(MRI.getType(Dst) == LLT::scalar(64));
+ if (tryLowerFullWidthBFX(B, MI, MRI))
+ return true;
+
bool Signed = isSignedBFE(MI);
- unsigned FirstOpnd = isa<GIntrinsic>(MI) ? 2 : 1;
+ bool IsIntrinsic = isa<GIntrinsic>(MI);
+ unsigned FirstOpnd = IsIntrinsic ? 2 : 1;
// Extract bitfield from Src, LSBit is the least-significant bit for the
// extraction (field offset) and Width is size of bitfield.
Register Src = MI.getOperand(FirstOpnd).getReg();
@@ -727,24 +752,49 @@ bool RegBankLegalizeHelper::lowerV_BFE(MachineInstr &MI) {
// Comments are for signed bitfield extract, similar for unsigned. x is sign
// bit. s is sign, l is LSB and y are remaining bits of bitfield to extract.
+ // llvm.amdgcn.{s,u}bfe take Width modulo 64, a masked 0 extracts nothing.
+ auto ConstWidth = getIConstantVRegValWithLookThrough(Width, MRI);
+ uint64_t WidthImm = 0;
+ if (ConstWidth) {
+ WidthImm = ConstWidth->Value.getZExtValue();
+ if (IsIntrinsic) {
+ WidthImm &= 63;
+ if (WidthImm == 0) {
+ B.buildConstant(Dst, 0);
+ MI.eraseFromParent();
+ return true;
+ }
+ // The Width operand is out of range, use the masked value.
+ if (WidthImm != ConstWidth->Value.getZExtValue())
+ Width = B.buildConstant(VgprRB_I32, WidthImm).getReg(0);
+ }
+ }
+
// Src >> LSBit Hi|Lo: x?????syyyyyyl??? -> xxxx?????syyyyyyl
unsigned SHROpc = Signed ? AMDGPU::G_ASHR : AMDGPU::G_LSHR;
auto SHRSrc = B.buildInstr(SHROpc, {VgprRB_I64}, {Src, LSBit});
- auto ConstWidth = getIConstantVRegValWithLookThrough(Width, MRI);
-
// Expand to Src >> LSBit << (64 - Width) >> (64 - Width)
// << (64 - Width): Hi|Lo: xxxx?????syyyyyyl -> syyyyyyl000000000
// >> (64 - Width): Hi|Lo: syyyyyyl000000000 -> ssssssssssyyyyyyl
if (!ConstWidth) {
auto Amt = B.buildSub(VgprRB_I32, B.buildConstant(SgprRB_I32, 64), Width);
- auto SignBit = B.buildShl(VgprRB_I64, SHRSrc, Amt);
+ // For G_UBFX/G_SBFX Width is in [1, 64], so 64 - Width is in [0, 63].
+ Register ShlSrc = SHRSrc.getReg(0);
+ Register ShlAmt = Amt.getReg(0);
+ if (IsIntrinsic) {
+ // Shifts are modulo 64, so Width 0 needs 1 + (63 - Width) to clear.
+ ShlSrc = B.buildShl(VgprRB_I64, SHRSrc, B.buildConstant(VgprRB_I32, 1))
+ .getReg(0);
+ ShlAmt = B.buildSub(VgprRB_I32, B.buildConstant(SgprRB_I32, 63), Width)
+ .getReg(0);
+ }
+ auto SignBit = B.buildShl(VgprRB_I64, ShlSrc, ShlAmt);
B.buildInstr(SHROpc, {Dst}, {SignBit, Amt});
MI.eraseFromParent();
return true;
}
- uint64_t WidthImm = ConstWidth->Value.getZExtValue();
auto UnmergeSHRSrc = B.buildUnmerge(VgprRB_I32, SHRSrc);
Register SHRSrcLo = UnmergeSHRSrc.getReg(0);
Register SHRSrcHi = UnmergeSHRSrc.getReg(1);
@@ -782,19 +832,36 @@ bool RegBankLegalizeHelper::lowerV_BFE(MachineInstr &MI) {
bool RegBankLegalizeHelper::lowerS_BFE(MachineInstr &MI) {
Register DstReg = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(DstReg);
+ assert(Ty == S32 || Ty == S64);
+
+ if (tryLowerFullWidthBFX(B, MI, MRI))
+ return true;
+
bool Signed = isSignedBFE(MI);
- unsigned FirstOpnd = isa<GIntrinsic>(MI) ? 2 : 1;
+ bool IsIntrinsic = isa<GIntrinsic>(MI);
+ unsigned FirstOpnd = IsIntrinsic ? 2 : 1;
Register Src = MI.getOperand(FirstOpnd).getReg();
Register LSBit = MI.getOperand(FirstOpnd + 1).getReg();
Register Width = MI.getOperand(FirstOpnd + 2).getReg();
+ unsigned TySize = Ty.getSizeInBits();
+
// For uniform bit field extract there are 4 available instructions, but
// LSBit(field offset) and Width(size of bitfield) need to be packed in S32,
// field offset in low and size in high 16 bits.
// Src1 Hi16|Lo16 = Size|FieldOffset
- auto Mask = B.buildConstant(SgprRB_I32, maskTrailingOnes<unsigned>(6));
- auto FieldOffset = B.buildAnd(SgprRB_I32, LSBit, Mask);
- auto Size = B.buildShl(SgprRB_I32, Width, B.buildConstant(SgprRB_I32, 16));
+ // llvm.amdgcn.{s,u}bfe take LSBit and Width modulo TySize. G_UBFX/G_SBFX
+ // guarantee LSBit < TySize and Width <= TySize.
+ // FIXME: a non-constant Width of TySize yields an out of range S_BFE width.
+ Register FieldOffset = LSBit;
+ Register MaskedWidth = Width;
+ if (IsIntrinsic) {
+ auto Mask = B.buildConstant(SgprRB_I32, TySize - 1);
+ FieldOffset = B.buildAnd(SgprRB_I32, LSBit, Mask).getReg(0);
+ MaskedWidth = B.buildAnd(SgprRB_I32, Width, Mask).getReg(0);
+ }
+ auto Size =
+ B.buildShl(SgprRB_I32, MaskedWidth, B.buildConstant(SgprRB_I32, 16));
auto Src1 = B.buildOr(SgprRB_I32, FieldOffset, Size);
unsigned Opc32 = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;
unsigned Opc64 = Signed ? AMDGPU::S_BFE_I64 : AMDGPU::S_BFE_U64;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
index 939633ba9c748..b0389941dd1ba 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgpu6.00-amd-amdpal -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=GFX11 %s
define i32 @v_bfe_i32_arg_arg_arg(i32 %src0, i32 %src1, i32 %src2) #0 {
; GFX6-LABEL: v_bfe_i32_arg_arg_arg:
@@ -7,6 +8,12 @@ define i32 @v_bfe_i32_arg_arg_arg(i32 %src0, i32 %src1, i32 %src2) #0 {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_bfe_i32 v0, v0, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i32_arg_arg_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_bfe_i32 v0, v0, v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 %src1, i32 %src2)
ret i32 %bfe_i32
}
@@ -14,11 +21,22 @@ define i32 @v_bfe_i32_arg_arg_arg(i32 %src0, i32 %src1, i32 %src2) #0 {
define amdgpu_ps i32 @s_bfe_i32_arg_arg_arg(i32 inreg %src0, i32 inreg %src1, i32 inreg %src2) #0 {
; GFX6-LABEL: s_bfe_i32_arg_arg_arg:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s1, s1, 63
+; GFX6-NEXT: s_and_b32 s2, s2, 31
+; GFX6-NEXT: s_and_b32 s1, s1, 31
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_bfe_i32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i32_arg_arg_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s2, s2, 31
+; GFX11-NEXT: s_and_b32 s1, s1, 31
+; GFX11-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s1, s1, s2
+; GFX11-NEXT: s_bfe_i32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 %src1, i32 %src2)
ret i32 %bfe_i32
}
@@ -28,10 +46,25 @@ define i64 @v_bfe_i64_arg_arg_arg(i64 %src0, i32 %src1, i32 %src2) #0 {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], v2
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 64, v3
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 63, v3
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v2
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 64, v3
; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i64_arg_arg_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]
+; GFX11-NEXT: v_sub_nc_u32_e32 v2, 63, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
+; GFX11-NEXT: v_sub_nc_u32_e32 v2, 64, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%bfe_i64 = call i64 @llvm.amdgcn.sbfe.i64(i64 %src0, i32 %src1, i32 %src2)
ret i64 %bfe_i64
}
@@ -43,6 +76,14 @@ define i64 @v_bfe_i64_arg_arg_imm_width_32(i64 %src0, i32 %src1) #0 {
; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], v2
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i64_arg_arg_imm_width_32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%bfe_i64 = call i64 @llvm.amdgcn.sbfe.i64(i64 %src0, i32 %src1, i32 32)
ret i64 %bfe_i64
}
@@ -54,18 +95,92 @@ define i64 @v_bfe_i64_arg_arg_imm_width_33(i64 %src0, i32 %src1) #0 {
; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], v2
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 1
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i64_arg_arg_imm_width_33:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_bfe_i32 v1, v1, 0, 1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%bfe_i64 = call i64 @llvm.amdgcn.sbfe.i64(i64 %src0, i32 %src1, i32 33)
ret i64 %bfe_i64
}
+define i64 @v_bfe_i64_arg_arg_imm_width_0(i64 %src0, i32 %src1) #0 {
+; GFX6-LABEL: v_bfe_i64_arg_arg_imm_width_0:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, 0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i64_arg_arg_imm_width_0:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %bfe_i64 = call i64 @llvm.amdgcn.sbfe.i64(i64 %src0, i32 %src1, i32 0)
+ ret i64 %bfe_i64
+}
+
+define i64 @v_bfe_i64_arg_arg_imm_width_64(i64 %src0, i32 %src1) #0 {
+; GFX6-LABEL: v_bfe_i64_arg_arg_imm_width_64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, 0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i64_arg_arg_imm_width_64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %bfe_i64 = call i64 @llvm.amdgcn.sbfe.i64(i64 %src0, i32 %src1, i32 64)
+ ret i64 %bfe_i64
+}
+
+define i64 @v_bfe_i64_arg_arg_imm_width_65(i64 %src0, i32 %src1) #0 {
+; GFX6-LABEL: v_bfe_i64_arg_arg_imm_width_65:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], v2
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i64_arg_arg_imm_width_65:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %bfe_i64 = call i64 @llvm.amdgcn.sbfe.i64(i64 %src0, i32 %src1, i32 65)
+ ret i64 %bfe_i64
+}
+
define amdgpu_ps i64 @s_bfe_i64_arg_arg_arg(i64 inreg %src0, i32 inreg %src1, i32 inreg %src2) #0 {
; GFX6-LABEL: s_bfe_i64_arg_arg_arg:
; GFX6: ; %bb.0:
+; GFX6-NEXT: s_and_b32 s3, s3, 63
; GFX6-NEXT: s_and_b32 s2, s2, 63
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], s2
; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i64_arg_arg_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s3, s3, 63
+; GFX11-NEXT: s_and_b32 s2, s2, 63
+; GFX11-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s2, s2, s3
+; GFX11-NEXT: s_bfe_i64 s[0:1], s[0:1], s2
+; GFX11-NEXT: ; return to shader part epilog
%bfe_i32 = call i64 @llvm.amdgcn.sbfe.i64(i64 %src0, i32 %src1, i32 %src2)
ret i64 %bfe_i32
}
@@ -75,14 +190,28 @@ define amdgpu_kernel void @bfe_i32_arg_arg_imm(ptr addrspace(1) %out, i32 %src0,
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_and_b32 s3, s3, 63
-; GFX6-NEXT: s_or_b32 s3, s3, 0x7b0000
+; GFX6-NEXT: s_and_b32 s3, s3, 31
+; GFX6-NEXT: s_or_b32 s3, s3, 0x1b0000
; GFX6-NEXT: s_bfe_i32 s3, s2, s3
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mov_b32_e32 v0, s3
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_arg_arg_imm:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s3, s3, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s3, s3, 0x1b0000
+; GFX11-NEXT: s_bfe_i32 s2, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 %src1, i32 123)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -93,14 +222,30 @@ define amdgpu_kernel void @bfe_i32_arg_imm_arg(ptr addrspace(1) %out, i32 %src0,
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_and_b32 s3, s3, 31
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: s_or_b32 s3, 59, s3
+; GFX6-NEXT: s_or_b32 s3, 27, s3
; GFX6-NEXT: s_bfe_i32 s3, s2, s3
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mov_b32_e32 v0, s3
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_arg_imm_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s3, s3, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-NEXT: s_or_b32 s3, 27, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 123, i32 %src2)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -111,7 +256,8 @@ define amdgpu_kernel void @bfe_i32_imm_arg_arg(ptr addrspace(1) %out, i32 %src1,
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_and_b32 s4, s2, 63
+; GFX6-NEXT: s_and_b32 s3, s3, 31
+; GFX6-NEXT: s_and_b32 s4, s2, 31
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s3, s4, s3
; GFX6-NEXT: s_bfe_i32 s3, 0x7b, s3
@@ -120,6 +266,22 @@ define amdgpu_kernel void @bfe_i32_imm_arg_arg(ptr addrspace(1) %out, i32 %src1,
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_imm_arg_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s3, s3, 31
+; GFX11-NEXT: s_and_b32 s2, s2, 31
+; GFX11-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s2, s2, s3
+; GFX11-NEXT: s_bfe_i32 s2, 0x7b, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 123, i32 %src1, i32 %src2)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -138,6 +300,19 @@ define amdgpu_kernel void @v_bfe_print_arg(ptr addrspace(1) %out, ptr addrspace(
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: v_bfe_print_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x80002
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i32, ptr addrspace(1) %src0, align 4
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 2, i32 8)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
@@ -149,13 +324,25 @@ define amdgpu_kernel void @bfe_i32_arg_0_width_reg_offset(ptr addrspace(1) %out,
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_and_b32 s3, s3, 63
+; GFX6-NEXT: s_and_b32 s3, s3, 31
; GFX6-NEXT: s_bfe_i32 s3, s2, s3
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mov_b32_e32 v0, s3
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_arg_0_width_reg_offset:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s3, s3, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 %src1, i32 0)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -173,6 +360,19 @@ define amdgpu_kernel void @bfe_i32_arg_0_width_imm_offset(ptr addrspace(1) %out,
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_arg_0_width_imm_offset:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 8, i32 0)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -192,6 +392,20 @@ define amdgpu_kernel void @bfe_i32_test_6(ptr addrspace(1) %out, ptr addrspace(1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_test_6:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_lshl_b32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x1f0001
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = shl i32 %x, 31
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shl, i32 1, i32 31)
@@ -213,6 +427,20 @@ define amdgpu_kernel void @bfe_i32_test_7(ptr addrspace(1) %out, ptr addrspace(1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_test_7:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_lshl_b32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x1f0000
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = shl i32 %x, 31
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shl, i32 0, i32 31)
@@ -234,6 +462,20 @@ define amdgpu_kernel void @bfe_i32_test_8(ptr addrspace(1) %out, ptr addrspace(1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_test_8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_lshl_b32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x1001f
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = shl i32 %x, 31
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shl, i32 31, i32 1)
@@ -254,6 +496,19 @@ define amdgpu_kernel void @bfe_i32_test_9(ptr addrspace(1) %out, ptr addrspace(1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_test_9:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x1001f
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %x, i32 31, i32 1)
store i32 %bfe, ptr addrspace(1) %out, align 4
@@ -273,6 +528,19 @@ define amdgpu_kernel void @bfe_i32_test_10(ptr addrspace(1) %out, ptr addrspace(
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_test_10:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x1f0001
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %x, i32 1, i32 31)
store i32 %bfe, ptr addrspace(1) %out, align 4
@@ -292,6 +560,19 @@ define amdgpu_kernel void @bfe_i32_test_11(ptr addrspace(1) %out, ptr addrspace(
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_test_11:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x180008
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %x, i32 8, i32 24)
store i32 %bfe, ptr addrspace(1) %out, align 4
@@ -311,6 +592,19 @@ define amdgpu_kernel void @bfe_i32_test_12(ptr addrspace(1) %out, ptr addrspace(
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_test_12:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x80018
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %x, i32 24, i32 8)
store i32 %bfe, ptr addrspace(1) %out, align 4
@@ -331,6 +625,20 @@ define amdgpu_kernel void @bfe_i32_test_13(ptr addrspace(1) %out, ptr addrspace(
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_test_13:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_ashr_i32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x1001f
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = ashr i32 %x, 31
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shl, i32 31, i32 1)
@@ -351,6 +659,20 @@ define amdgpu_kernel void @bfe_i32_test_14(ptr addrspace(1) %out, ptr addrspace(
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_test_14:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_lshr_b32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x1001f
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = lshr i32 %x, 31
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shl, i32 31, i32 1)
@@ -368,6 +690,16 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_0(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_0:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_bfe_i32 s2, 0, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 0, i32 0, i32 0)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -384,6 +716,16 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_1(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_1:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_bfe_i32 s2, 0x302e, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 12334, i32 0, i32 0)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -400,6 +742,16 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_2(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_2:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_bfe_i32 s2, 0, 0x10000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 0, i32 0, i32 1)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -416,6 +768,16 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_3(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_3:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_bfe_i32 s2, 1, 0x10000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 1, i32 0, i32 1)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -432,6 +794,16 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_4(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_4:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_bfe_i32 s2, -1, 0x10000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 4294967295, i32 0, i32 1)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -449,6 +821,18 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_5(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x10007
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_i32 s2, 0x80, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 128, i32 7, i32 1)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -466,6 +850,18 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_6(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_6:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x80000
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_i32 s2, 0x80, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 128, i32 0, i32 8)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -483,6 +879,18 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_7(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_7:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x80000
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_i32 s2, 0x7f, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 127, i32 0, i32 8)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -500,6 +908,18 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_8(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x80006
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_i32 s2, 0x7f, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 127, i32 6, i32 8)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -517,6 +937,18 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_9(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_9:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x80010
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_i32 s2, 0x10000, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 65536, i32 16, i32 8)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -534,6 +966,18 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_10(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_10:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x100010
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_i32 s2, 0xffff, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 65535, i32 16, i32 16)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -551,6 +995,18 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_11(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_11:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x40004
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_i32 s2, 0xa0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 160, i32 4, i32 4)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -568,6 +1024,18 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_12(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_12:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x1001f
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_i32 s2, 0xa0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 160, i32 31, i32 1)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -585,6 +1053,18 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_13(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_13:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x100010
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_i32 s2, 0x1fffe, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 131070, i32 16, i32 16)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -602,6 +1082,18 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_14(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_14:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x1e0002
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_i32 s2, 0xa0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 160, i32 2, i32 30)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -619,6 +1111,18 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_15(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_15:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x1c0004
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_i32 s2, 0xa0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 160, i32 4, i32 28)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -635,6 +1139,16 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_16(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_bfe_i32 s2, -1, 0x70001
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 4294967295, i32 1, i32 7)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -652,6 +1166,18 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_17(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_17:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x1f0001
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_i32 s2, 0xff, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 255, i32 1, i32 31)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -669,6 +1195,18 @@ define amdgpu_kernel void @bfe_i32_constant_fold_test_18(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_i32_constant_fold_test_18:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x1001f
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_i32 s2, 0xff, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_i32 = call i32 @llvm.amdgcn.sbfe.i32(i32 255, i32 31, i32 1)
store i32 %bfe_i32, ptr addrspace(1) %out, align 4
ret void
@@ -688,6 +1226,20 @@ define amdgpu_kernel void @bfe_sext_in_reg_i24(ptr addrspace(1) %out, ptr addrsp
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_sext_in_reg_i24:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x180000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x180000
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %x, i32 0, i32 24)
%shl = shl i32 %bfe, 8
@@ -713,6 +1265,25 @@ define amdgpu_kernel void @simplify_demanded_bfe_sdiv(ptr addrspace(1) %out, ptr
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: simplify_demanded_bfe_sdiv:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x100001
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_ashr_i32 s3, s2, 31
+; GFX11-NEXT: s_lshr_b32 s3, s3, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_add_i32 s2, s2, s3
+; GFX11-NEXT: s_ashr_i32 s2, s2, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%src = load i32, ptr addrspace(1) %in, align 4
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %src, i32 1, i32 16)
%div = sdiv i32 %bfe, 2
@@ -733,6 +1304,19 @@ define amdgpu_kernel void @bfe_0_width(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_0_width:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i32, ptr addrspace(1) %ptr, align 4
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 8, i32 0)
store i32 %bfe, ptr addrspace(1) %out, align 4
@@ -753,6 +1337,20 @@ define amdgpu_kernel void @bfe_8_bfe_8(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_8_bfe_8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x80000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x80000
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i32, ptr addrspace(1) %ptr, align 4
%bfe0 = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 0, i32 8)
%bfe1 = call i32 @llvm.amdgcn.sbfe.i32(i32 %bfe0, i32 0, i32 8)
@@ -774,6 +1372,20 @@ define amdgpu_kernel void @bfe_8_bfe_16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_8_bfe_16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x80000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x100000
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i32, ptr addrspace(1) %ptr, align 4
%bfe0 = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 0, i32 8)
%bfe1 = call i32 @llvm.amdgcn.sbfe.i32(i32 %bfe0, i32 0, i32 16)
@@ -796,6 +1408,20 @@ define amdgpu_kernel void @bfe_16_bfe_8(ptr addrspace(1) %out, ptr addrspace(1)
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_16_bfe_8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x100000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x80000
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i32, ptr addrspace(1) %ptr, align 4
%bfe0 = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 0, i32 16)
%bfe1 = call i32 @llvm.amdgcn.sbfe.i32(i32 %bfe0, i32 0, i32 8)
@@ -817,6 +1443,20 @@ define amdgpu_kernel void @sext_in_reg_i8_to_i32_bfe(ptr addrspace(1) %out, i32
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: sext_in_reg_i8_to_i32_bfe:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_add_i32 s2, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x80000
+; GFX11-NEXT: s_sext_i32_i8 s2, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%c = add i32 %a, %b ; add to prevent folding into extload
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %c, i32 0, i32 8)
%shl = shl i32 %bfe, 24
@@ -838,6 +1478,20 @@ define amdgpu_kernel void @sext_in_reg_i8_to_i32_bfe_wrong(ptr addrspace(1) %out
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: sext_in_reg_i8_to_i32_bfe_wrong:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_add_i32 s2, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 8
+; GFX11-NEXT: s_sext_i32_i8 s2, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%c = add i32 %a, %b ; add to prevent folding into extload
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %c, i32 8, i32 0)
%shl = shl i32 %bfe, 24
@@ -863,6 +1517,21 @@ define amdgpu_kernel void @sextload_i8_to_i32_bfe(ptr addrspace(1) %out, ptr add
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: sextload_i8_to_i32_bfe:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_load_i8 v1, v0, s[2:3]
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_readfirstlane_b32 s2, v1
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x80000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_sext_i32_i8 s2, s2
+; GFX11-NEXT: v_mov_b32_e32 v1, s2
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i8, ptr addrspace(1) %ptr, align 1
%sext = sext i8 %load to i32
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %sext, i32 0, i32 8)
@@ -889,6 +1558,21 @@ define amdgpu_kernel void @sextload_i8_to_i32_bfe_0(ptr addrspace(1) %out, ptr a
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: sextload_i8_to_i32_bfe_0:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_load_i8 v1, v0, s[2:3]
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_readfirstlane_b32 s2, v1
+; GFX11-NEXT: s_bfe_i32 s2, s2, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_sext_i32_i8 s2, s2
+; GFX11-NEXT: v_mov_b32_e32 v1, s2
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i8, ptr addrspace(1) %ptr, align 1
%sext = sext i8 %load to i32
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %sext, i32 8, i32 0)
@@ -912,6 +1596,20 @@ define amdgpu_kernel void @sext_in_reg_i1_bfe_offset_0(ptr addrspace(1) %out, pt
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: sext_in_reg_i1_bfe_offset_0:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x10000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x10000
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = shl i32 %x, 31
%shr = ashr i32 %shl, 31
@@ -934,6 +1632,20 @@ define amdgpu_kernel void @sext_in_reg_i1_bfe_offset_1(ptr addrspace(1) %out, pt
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: sext_in_reg_i1_bfe_offset_1:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x20000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x10001
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = shl i32 %x, 30
%shr = ashr i32 %shl, 30
@@ -956,6 +1668,20 @@ define amdgpu_kernel void @sext_in_reg_i2_bfe_offset_1(ptr addrspace(1) %out, pt
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: sext_in_reg_i2_bfe_offset_1:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x20000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x20001
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = shl i32 %x, 30
%shr = ashr i32 %shl, 30
@@ -964,6 +1690,100 @@ define amdgpu_kernel void @sext_in_reg_i2_bfe_offset_1(ptr addrspace(1) %out, pt
ret void
}
+define amdgpu_ps i64 @s_bfe_i64_arg_arg_imm_width_32(i64 inreg %src0, i32 inreg %src1) #0 {
+; GFX6-LABEL: s_bfe_i64_arg_arg_imm_width_32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_and_b32 s2, s2, 63
+; GFX6-NEXT: s_bitset1_b32 s2, 21
+; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], s2
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i64_arg_arg_imm_width_32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s2, s2, 63
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bitset1_b32 s2, 21
+; GFX11-NEXT: s_bfe_i64 s[0:1], s[0:1], s2
+; GFX11-NEXT: ; return to shader part epilog
+ %bfe = call i64 @llvm.amdgcn.sbfe.i64(i64 %src0, i32 %src1, i32 32)
+ ret i64 %bfe
+}
+
+define amdgpu_ps i64 @s_bfe_i64_arg_arg_imm_width_64(i64 inreg %src0, i32 inreg %src1) #0 {
+; GFX6-LABEL: s_bfe_i64_arg_arg_imm_width_64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_and_b32 s2, s2, 63
+; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], s2
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i64_arg_arg_imm_width_64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s2, s2, 63
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i64 s[0:1], s[0:1], s2
+; GFX11-NEXT: ; return to shader part epilog
+ %bfe = call i64 @llvm.amdgcn.sbfe.i64(i64 %src0, i32 %src1, i32 64)
+ ret i64 %bfe
+}
+
+define amdgpu_ps i32 @s_bfe_i32_arg_arg_imm_width_32(i32 inreg %src0, i32 inreg %src1) #0 {
+; GFX6-LABEL: s_bfe_i32_arg_arg_imm_width_32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_and_b32 s1, s1, 31
+; GFX6-NEXT: s_bfe_i32 s0, s0, s1
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i32_arg_arg_imm_width_32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s1, s1, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
+ %bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 %src1, i32 32)
+ ret i32 %bfe
+}
+
+define amdgpu_ps i64 @s_bfe_i64_arg_arg_imm_width_96(i64 inreg %src0, i32 inreg %src1) #0 {
+; GFX6-LABEL: s_bfe_i64_arg_arg_imm_width_96:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_and_b32 s2, s2, 63
+; GFX6-NEXT: s_bitset1_b32 s2, 21
+; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], s2
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i64_arg_arg_imm_width_96:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s2, s2, 63
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bitset1_b32 s2, 21
+; GFX11-NEXT: s_bfe_i64 s[0:1], s[0:1], s2
+; GFX11-NEXT: ; return to shader part epilog
+ %bfe = call i64 @llvm.amdgcn.sbfe.i64(i64 %src0, i32 %src1, i32 96)
+ ret i64 %bfe
+}
+
+define amdgpu_ps i32 @s_bfe_i32_arg_imm_offset_40_arg(i32 inreg %src0, i32 inreg %src2) #0 {
+; GFX6-LABEL: s_bfe_i32_arg_imm_offset_40_arg:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_and_b32 s1, s1, 31
+; GFX6-NEXT: s_lshl_b32 s1, s1, 16
+; GFX6-NEXT: s_or_b32 s1, 8, s1
+; GFX6-NEXT: s_bfe_i32 s0, s0, s1
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i32_arg_imm_offset_40_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s1, s1, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-NEXT: s_or_b32 s1, 8, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_i32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
+ %bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 40, i32 %src2)
+ ret i32 %bfe
+}
+
declare i32 @llvm.amdgcn.sbfe.i32(i32, i32, i32) #1
declare i64 @llvm.amdgcn.sbfe.i64(i64, i32, i32) #1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
index bec929f60d153..d96507332155b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgpu6.00-amd-amdpal -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=GFX11 %s
define i32 @v_bfe_i32_arg_arg_arg(i32 %src0, i32 %src1, i32 %src2) #0 {
; GFX6-LABEL: v_bfe_i32_arg_arg_arg:
@@ -7,6 +8,12 @@ define i32 @v_bfe_i32_arg_arg_arg(i32 %src0, i32 %src1, i32 %src2) #0 {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_bfe_u32 v0, v0, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i32_arg_arg_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_bfe_u32 v0, v0, v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%bfe_i32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 %src1, i32 %src2)
ret i32 %bfe_i32
}
@@ -14,11 +21,22 @@ define i32 @v_bfe_i32_arg_arg_arg(i32 %src0, i32 %src1, i32 %src2) #0 {
define amdgpu_ps i32 @s_bfe_i32_arg_arg_arg(i32 inreg %src0, i32 inreg %src1, i32 inreg %src2) #0 {
; GFX6-LABEL: s_bfe_i32_arg_arg_arg:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s1, s1, 63
+; GFX6-NEXT: s_and_b32 s2, s2, 31
+; GFX6-NEXT: s_and_b32 s1, s1, 31
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_bfe_u32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i32_arg_arg_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s2, s2, 31
+; GFX11-NEXT: s_and_b32 s1, s1, 31
+; GFX11-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s1, s1, s2
+; GFX11-NEXT: s_bfe_u32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
%bfe_i32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 %src1, i32 %src2)
ret i32 %bfe_i32
}
@@ -28,10 +46,25 @@ define i64 @v_bfe_i64_arg_arg_arg(i64 %src0, i32 %src1, i32 %src2) #0 {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v2
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 64, v3
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 63, v3
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v2
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 64, v3
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i64_arg_arg_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
+; GFX11-NEXT: v_sub_nc_u32_e32 v2, 63, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
+; GFX11-NEXT: v_sub_nc_u32_e32 v2, 64, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%bfe_i64 = call i64 @llvm.amdgcn.ubfe.i64(i64 %src0, i32 %src1, i32 %src2)
ret i64 %bfe_i64
}
@@ -43,6 +76,13 @@ define i64 @v_bfe_i64_arg_arg_imm_width_32(i64 %src0, i32 %src1) #0 {
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v2
; GFX6-NEXT: v_mov_b32_e32 v1, 0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i64_arg_arg_imm_width_32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%bfe_i64 = call i64 @llvm.amdgcn.ubfe.i64(i64 %src0, i32 %src1, i32 32)
ret i64 %bfe_i64
}
@@ -54,18 +94,92 @@ define i64 @v_bfe_i64_arg_arg_imm_width_33(i64 %src0, i32 %src1) #0 {
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v2
; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 1
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i64_arg_arg_imm_width_33:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_bfe_u32 v1, v1, 0, 1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%bfe_i64 = call i64 @llvm.amdgcn.ubfe.i64(i64 %src0, i32 %src1, i32 33)
ret i64 %bfe_i64
}
+define i64 @v_bfe_i64_arg_arg_imm_width_0(i64 %src0, i32 %src1) #0 {
+; GFX6-LABEL: v_bfe_i64_arg_arg_imm_width_0:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, 0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i64_arg_arg_imm_width_0:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %bfe_i64 = call i64 @llvm.amdgcn.ubfe.i64(i64 %src0, i32 %src1, i32 0)
+ ret i64 %bfe_i64
+}
+
+define i64 @v_bfe_i64_arg_arg_imm_width_64(i64 %src0, i32 %src1) #0 {
+; GFX6-LABEL: v_bfe_i64_arg_arg_imm_width_64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, 0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i64_arg_arg_imm_width_64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %bfe_i64 = call i64 @llvm.amdgcn.ubfe.i64(i64 %src0, i32 %src1, i32 64)
+ ret i64 %bfe_i64
+}
+
+define i64 @v_bfe_i64_arg_arg_imm_width_65(i64 %src0, i32 %src1) #0 {
+; GFX6-LABEL: v_bfe_i64_arg_arg_imm_width_65:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v2
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 1
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_bfe_i64_arg_arg_imm_width_65:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v0, v0, 0, 1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %bfe_i64 = call i64 @llvm.amdgcn.ubfe.i64(i64 %src0, i32 %src1, i32 65)
+ ret i64 %bfe_i64
+}
+
define amdgpu_ps i64 @s_bfe_i64_arg_arg_arg(i64 inreg %src0, i32 inreg %src1, i32 inreg %src2) #0 {
; GFX6-LABEL: s_bfe_i64_arg_arg_arg:
; GFX6: ; %bb.0:
+; GFX6-NEXT: s_and_b32 s3, s3, 63
; GFX6-NEXT: s_and_b32 s2, s2, 63
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: s_bfe_u64 s[0:1], s[0:1], s2
; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i64_arg_arg_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s3, s3, 63
+; GFX11-NEXT: s_and_b32 s2, s2, 63
+; GFX11-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s2, s2, s3
+; GFX11-NEXT: s_bfe_u64 s[0:1], s[0:1], s2
+; GFX11-NEXT: ; return to shader part epilog
%bfe_i32 = call i64 @llvm.amdgcn.ubfe.i64(i64 %src0, i32 %src1, i32 %src2)
ret i64 %bfe_i32
}
@@ -75,15 +189,30 @@ define amdgpu_kernel void @bfe_u32_arg_arg_arg(ptr addrspace(1) %out, i32 %src0,
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_and_b32 s4, s3, 63
-; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: s_or_b32 s3, s4, s3
+; GFX6-NEXT: s_and_b32 s3, s3, 31
+; GFX6-NEXT: s_lshl_b32 s4, s3, 16
+; GFX6-NEXT: s_or_b32 s3, s3, s4
; GFX6-NEXT: s_bfe_u32 s3, s2, s3
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mov_b32_e32 v0, s3
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_arg_arg_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s3, s3, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_lshl_b32 s4, s3, 16
+; GFX11-NEXT: s_or_b32 s3, s3, s4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s2, s2, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 %src1, i32 %src1)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -94,14 +223,28 @@ define amdgpu_kernel void @bfe_u32_arg_arg_imm(ptr addrspace(1) %out, i32 %src0,
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_and_b32 s3, s3, 63
-; GFX6-NEXT: s_or_b32 s3, s3, 0x7b0000
+; GFX6-NEXT: s_and_b32 s3, s3, 31
+; GFX6-NEXT: s_or_b32 s3, s3, 0x1b0000
; GFX6-NEXT: s_bfe_u32 s3, s2, s3
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mov_b32_e32 v0, s3
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_arg_arg_imm:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s3, s3, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s3, s3, 0x1b0000
+; GFX11-NEXT: s_bfe_u32 s2, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 %src1, i32 123)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -112,14 +255,30 @@ define amdgpu_kernel void @bfe_u32_arg_imm_arg(ptr addrspace(1) %out, i32 %src0,
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_and_b32 s3, s3, 31
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: s_or_b32 s3, 59, s3
+; GFX6-NEXT: s_or_b32 s3, 27, s3
; GFX6-NEXT: s_bfe_u32 s3, s2, s3
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mov_b32_e32 v0, s3
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_arg_imm_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s3, s3, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-NEXT: s_or_b32 s3, 27, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s2, s2, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 123, i32 %src2)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -130,7 +289,8 @@ define amdgpu_kernel void @bfe_u32_imm_arg_arg(ptr addrspace(1) %out, i32 %src1,
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_and_b32 s4, s2, 63
+; GFX6-NEXT: s_and_b32 s3, s3, 31
+; GFX6-NEXT: s_and_b32 s4, s2, 31
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s3, s4, s3
; GFX6-NEXT: s_bfe_u32 s3, 0x7b, s3
@@ -139,6 +299,22 @@ define amdgpu_kernel void @bfe_u32_imm_arg_arg(ptr addrspace(1) %out, i32 %src1,
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_imm_arg_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s3, s3, 31
+; GFX11-NEXT: s_and_b32 s2, s2, 31
+; GFX11-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s2, s2, s3
+; GFX11-NEXT: s_bfe_u32 s2, 0x7b, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 123, i32 %src1, i32 %src2)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -149,13 +325,25 @@ define amdgpu_kernel void @bfe_u32_arg_0_width_reg_offset(ptr addrspace(1) %out,
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_and_b32 s3, s3, 63
+; GFX6-NEXT: s_and_b32 s3, s3, 31
; GFX6-NEXT: s_bfe_u32 s3, s2, s3
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mov_b32_e32 v0, s3
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_arg_0_width_reg_offset:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s3, s3, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s2, s2, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 %src1, i32 0)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -173,6 +361,19 @@ define amdgpu_kernel void @bfe_u32_arg_0_width_imm_offset(ptr addrspace(1) %out,
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_arg_0_width_imm_offset:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 8, i32 0)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -194,6 +395,20 @@ define amdgpu_kernel void @bfe_u32_zextload_i8(ptr addrspace(1) %out, ptr addrsp
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_zextload_i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_load_u8 v1, v0, s[2:3]
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_readfirstlane_b32 s2, v1
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x80000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v1, s2
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i8, ptr addrspace(1) %in
%ext = zext i8 %load to i32
%bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %ext, i32 0, i32 8)
@@ -217,6 +432,22 @@ define amdgpu_kernel void @bfe_u32_zext_in_reg_i8(ptr addrspace(1) %out, ptr add
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_zext_in_reg_i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_add_i32 s2, s2, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, 0xff
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x80000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i32, ptr addrspace(1) %in, align 4
%add = add i32 %load, 1
%ext = and i32 %add, 255
@@ -240,6 +471,22 @@ define amdgpu_kernel void @bfe_u32_zext_in_reg_i16(ptr addrspace(1) %out, ptr ad
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_zext_in_reg_i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_add_i32 s2, s2, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x100000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i32, ptr addrspace(1) %in, align 4
%add = add i32 %load, 1
%ext = and i32 %add, 65535
@@ -263,6 +510,22 @@ define amdgpu_kernel void @bfe_u32_zext_in_reg_i8_offset_1(ptr addrspace(1) %out
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_zext_in_reg_i8_offset_1:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_add_i32 s2, s2, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, 0xff
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x80001
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i32, ptr addrspace(1) %in, align 4
%add = add i32 %load, 1
%ext = and i32 %add, 255
@@ -286,6 +549,22 @@ define amdgpu_kernel void @bfe_u32_zext_in_reg_i8_offset_3(ptr addrspace(1) %out
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_zext_in_reg_i8_offset_3:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_add_i32 s2, s2, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, 0xff
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x80003
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i32, ptr addrspace(1) %in, align 4
%add = add i32 %load, 1
%ext = and i32 %add, 255
@@ -309,6 +588,22 @@ define amdgpu_kernel void @bfe_u32_zext_in_reg_i8_offset_7(ptr addrspace(1) %out
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_zext_in_reg_i8_offset_7:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_add_i32 s2, s2, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, 0xff
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x80007
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i32, ptr addrspace(1) %in, align 4
%add = add i32 %load, 1
%ext = and i32 %add, 255
@@ -332,6 +627,22 @@ define amdgpu_kernel void @bfe_u32_zext_in_reg_i16_offset_8(ptr addrspace(1) %ou
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_zext_in_reg_i16_offset_8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_add_i32 s2, s2, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x80008
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%load = load i32, ptr addrspace(1) %in, align 4
%add = add i32 %load, 1
%ext = and i32 %add, 65535
@@ -353,6 +664,19 @@ define amdgpu_kernel void @bfe_u32_test_1(ptr addrspace(1) %out, ptr addrspace(1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_1:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x10000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %x, i32 0, i32 1)
store i32 %bfe, ptr addrspace(1) %out, align 4
@@ -373,6 +697,20 @@ define amdgpu_kernel void @bfe_u32_test_2(ptr addrspace(1) %out, ptr addrspace(1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_2:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_lshl_b32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x80000
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = shl i32 %x, 31
%bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 0, i32 8)
@@ -394,6 +732,20 @@ define amdgpu_kernel void @bfe_u32_test_3(ptr addrspace(1) %out, ptr addrspace(1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_3:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_lshl_b32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x10000
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = shl i32 %x, 31
%bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 0, i32 1)
@@ -415,6 +767,20 @@ define amdgpu_kernel void @bfe_u32_test_4(ptr addrspace(1) %out, ptr addrspace(1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_4:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x10000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x1001f
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = shl i32 %x, 31
%shr = lshr i32 %shl, 31
@@ -437,6 +803,20 @@ define amdgpu_kernel void @bfe_u32_test_5(ptr addrspace(1) %out, ptr addrspace(1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_i32 s2, s2, 0x10000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x10000
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = shl i32 %x, 31
%shr = ashr i32 %shl, 31
@@ -459,6 +839,20 @@ define amdgpu_kernel void @bfe_u32_test_6(ptr addrspace(1) %out, ptr addrspace(1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_6:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_lshl_b32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x1f0001
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = shl i32 %x, 31
%bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 1, i32 31)
@@ -480,6 +874,20 @@ define amdgpu_kernel void @bfe_u32_test_7(ptr addrspace(1) %out, ptr addrspace(1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_7:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_lshl_b32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x1f0000
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = shl i32 %x, 31
%bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 0, i32 31)
@@ -501,6 +909,20 @@ define amdgpu_kernel void @bfe_u32_test_8(ptr addrspace(1) %out, ptr addrspace(1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_lshl_b32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x1001f
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = shl i32 %x, 31
%bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 31, i32 1)
@@ -521,6 +943,19 @@ define amdgpu_kernel void @bfe_u32_test_9(ptr addrspace(1) %out, ptr addrspace(1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_9:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x1001f
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %x, i32 31, i32 1)
store i32 %bfe, ptr addrspace(1) %out, align 4
@@ -540,6 +975,19 @@ define amdgpu_kernel void @bfe_u32_test_10(ptr addrspace(1) %out, ptr addrspace(
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_10:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x1f0001
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %x, i32 1, i32 31)
store i32 %bfe, ptr addrspace(1) %out, align 4
@@ -559,6 +1007,19 @@ define amdgpu_kernel void @bfe_u32_test_11(ptr addrspace(1) %out, ptr addrspace(
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_11:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x180008
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %x, i32 8, i32 24)
store i32 %bfe, ptr addrspace(1) %out, align 4
@@ -578,6 +1039,19 @@ define amdgpu_kernel void @bfe_u32_test_12(ptr addrspace(1) %out, ptr addrspace(
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_12:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x80018
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %x, i32 24, i32 8)
store i32 %bfe, ptr addrspace(1) %out, align 4
@@ -599,6 +1073,20 @@ define amdgpu_kernel void @bfe_u32_test_13(ptr addrspace(1) %out, ptr addrspace(
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_13:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_ashr_i32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x1001f
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = ashr i32 %x, 31
%bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 31, i32 1)
@@ -619,6 +1107,20 @@ define amdgpu_kernel void @bfe_u32_test_14(ptr addrspace(1) %out, ptr addrspace(
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_test_14:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_lshr_b32 s2, s2, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x1001f
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%x = load i32, ptr addrspace(1) %in, align 4
%shl = lshr i32 %x, 31
%bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 31, i32 1)
@@ -636,6 +1138,16 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_0(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_0:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_bfe_u32 s2, 0, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 0, i32 0, i32 0)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -652,6 +1164,16 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_1(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_1:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_bfe_u32 s2, 0x302e, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 12334, i32 0, i32 0)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -668,6 +1190,16 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_2(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_2:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_bfe_u32 s2, 0, 0x10000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 0, i32 0, i32 1)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -684,6 +1216,16 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_3(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_3:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_bfe_u32 s2, 1, 0x10000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 1, i32 0, i32 1)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -700,6 +1242,16 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_4(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_4:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_bfe_u32 s2, -1, 0x10000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 4294967295, i32 0, i32 1)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -717,6 +1269,18 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_5(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x10007
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_u32 s2, 0x80, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 128, i32 7, i32 1)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -734,6 +1298,18 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_6(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_6:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x80000
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_u32 s2, 0x80, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 128, i32 0, i32 8)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -751,6 +1327,18 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_7(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_7:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x80000
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_u32 s2, 0x7f, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 127, i32 0, i32 8)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -768,6 +1356,18 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_8(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x80006
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_u32 s2, 0x7f, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 127, i32 6, i32 8)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -785,6 +1385,18 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_9(ptr addrspace(1) %out) #
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_9:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x80010
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_u32 s2, 0x10000, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 65536, i32 16, i32 8)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -802,6 +1414,18 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_10(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_10:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x100010
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_u32 s2, 0xffff, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 65535, i32 16, i32 16)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -819,6 +1443,18 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_11(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_11:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x40004
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_u32 s2, 0xa0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 160, i32 4, i32 4)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -836,6 +1472,18 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_12(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_12:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x1001f
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_u32 s2, 0xa0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 160, i32 31, i32 1)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -853,6 +1501,18 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_13(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_13:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x100010
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_u32 s2, 0x1fffe, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 131070, i32 16, i32 16)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -870,6 +1530,18 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_14(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_14:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x1e0002
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_u32 s2, 0xa0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 160, i32 2, i32 30)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -887,6 +1559,18 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_15(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_15:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x1c0004
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_u32 s2, 0xa0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 160, i32 4, i32 28)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -903,6 +1587,16 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_16(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_bfe_u32 s2, -1, 0x70001
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 4294967295, i32 1, i32 7)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -920,6 +1614,18 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_17(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_17:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x1f0001
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_u32 s2, 0xff, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 255, i32 1, i32 31)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -937,6 +1643,18 @@ define amdgpu_kernel void @bfe_u32_constant_fold_test_18(ptr addrspace(1) %out)
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: bfe_u32_constant_fold_test_18:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_mov_b32 s2, 0x1001f
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_bfe_u32 s2, 0xff, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 255, i32 31, i32 1)
store i32 %bfe_u32, ptr addrspace(1) %out, align 4
ret void
@@ -965,6 +1683,23 @@ define amdgpu_kernel void @simplify_bfe_u32_multi_use_arg(ptr addrspace(1) %out0
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: simplify_bfe_u32_multi_use_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x10
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b32 s6, s[0:1], 0x0
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s4, s6, 63
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s5, s4, 0x20002
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
+; GFX11-NEXT: v_mov_b32_e32 v2, s4
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: global_store_b32 v0, v2, s[2:3]
+; GFX11-NEXT: s_endpgm
ptr addrspace(1) %out1,
ptr addrspace(1) %in) #0 {
%src = load i32, ptr addrspace(1) %in, align 4
@@ -987,6 +1722,19 @@ define amdgpu_kernel void @lshr_and(ptr addrspace(1) %out, i32 %a) #0 {
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: lshr_and:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x30006
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%b = lshr i32 %a, 6
%c = and i32 %b, 7
store i32 %c, ptr addrspace(1) %out, align 8
@@ -1005,6 +1753,18 @@ define amdgpu_kernel void @v_lshr_and(ptr addrspace(1) %out, i32 %a, i32 %b) #0
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: v_lshr_and:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_lshr_b32 s2, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, 7
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%c = lshr i32 %a, %b
%d = and i32 %c, 7
store i32 %d, ptr addrspace(1) %out, align 8
@@ -1023,6 +1783,19 @@ define amdgpu_kernel void @and_lshr(ptr addrspace(1) %out, i32 %a) #0 {
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: and_lshr:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x30006
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%b = and i32 %a, 448
%c = lshr i32 %b, 6
store i32 %c, ptr addrspace(1) %out, align 8
@@ -1041,6 +1814,19 @@ define amdgpu_kernel void @and_lshr2(ptr addrspace(1) %out, i32 %a) #0 {
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: and_lshr2:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x30006
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%b = and i32 %a, 511
%c = lshr i32 %b, 6
store i32 %c, ptr addrspace(1) %out, align 8
@@ -1059,12 +1845,119 @@ define amdgpu_kernel void @shl_lshr(ptr addrspace(1) %out, i32 %a) #0 {
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
+;
+; GFX11-LABEL: shl_lshr:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bfe_u32 s2, s2, 0x150002
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_endpgm
%b = shl i32 %a, 9
%c = lshr i32 %b, 11
store i32 %c, ptr addrspace(1) %out, align 8
ret void
}
+define amdgpu_ps i64 @s_bfe_i64_arg_arg_imm_width_32(i64 inreg %src0, i32 inreg %src1) #0 {
+; GFX6-LABEL: s_bfe_i64_arg_arg_imm_width_32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_and_b32 s2, s2, 63
+; GFX6-NEXT: s_bitset1_b32 s2, 21
+; GFX6-NEXT: s_bfe_u64 s[0:1], s[0:1], s2
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i64_arg_arg_imm_width_32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s2, s2, 63
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bitset1_b32 s2, 21
+; GFX11-NEXT: s_bfe_u64 s[0:1], s[0:1], s2
+; GFX11-NEXT: ; return to shader part epilog
+ %bfe = call i64 @llvm.amdgcn.ubfe.i64(i64 %src0, i32 %src1, i32 32)
+ ret i64 %bfe
+}
+
+define amdgpu_ps i64 @s_bfe_i64_arg_arg_imm_width_64(i64 inreg %src0, i32 inreg %src1) #0 {
+; GFX6-LABEL: s_bfe_i64_arg_arg_imm_width_64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_and_b32 s2, s2, 63
+; GFX6-NEXT: s_bfe_u64 s[0:1], s[0:1], s2
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i64_arg_arg_imm_width_64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s2, s2, 63
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u64 s[0:1], s[0:1], s2
+; GFX11-NEXT: ; return to shader part epilog
+ %bfe = call i64 @llvm.amdgcn.ubfe.i64(i64 %src0, i32 %src1, i32 64)
+ ret i64 %bfe
+}
+
+define amdgpu_ps i32 @s_bfe_i32_arg_arg_imm_width_32(i32 inreg %src0, i32 inreg %src1) #0 {
+; GFX6-LABEL: s_bfe_i32_arg_arg_imm_width_32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_and_b32 s1, s1, 31
+; GFX6-NEXT: s_bfe_u32 s0, s0, s1
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i32_arg_arg_imm_width_32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s1, s1, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
+ %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 %src1, i32 32)
+ ret i32 %bfe
+}
+
+define amdgpu_ps i64 @s_bfe_i64_arg_arg_imm_width_96(i64 inreg %src0, i32 inreg %src1) #0 {
+; GFX6-LABEL: s_bfe_i64_arg_arg_imm_width_96:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_and_b32 s2, s2, 63
+; GFX6-NEXT: s_bitset1_b32 s2, 21
+; GFX6-NEXT: s_bfe_u64 s[0:1], s[0:1], s2
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i64_arg_arg_imm_width_96:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s2, s2, 63
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_bitset1_b32 s2, 21
+; GFX11-NEXT: s_bfe_u64 s[0:1], s[0:1], s2
+; GFX11-NEXT: ; return to shader part epilog
+ %bfe = call i64 @llvm.amdgcn.ubfe.i64(i64 %src0, i32 %src1, i32 96)
+ ret i64 %bfe
+}
+
+define amdgpu_ps i32 @s_bfe_i32_arg_imm_offset_40_arg(i32 inreg %src0, i32 inreg %src2) #0 {
+; GFX6-LABEL: s_bfe_i32_arg_imm_offset_40_arg:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_and_b32 s1, s1, 31
+; GFX6-NEXT: s_lshl_b32 s1, s1, 16
+; GFX6-NEXT: s_or_b32 s1, 8, s1
+; GFX6-NEXT: s_bfe_u32 s0, s0, s1
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bfe_i32_arg_imm_offset_40_arg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s1, s1, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-NEXT: s_or_b32 s1, 8, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_bfe_u32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
+ %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 40, i32 %src2)
+ ret i32 %bfe
+}
+
declare i32 @llvm.amdgcn.ubfe.i32(i32, i32, i32) #1
declare i64 @llvm.amdgcn.ubfe.i64(i64, i32, i32) #1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
index 61d1d746f9c85..b617dfe26d760 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
@@ -227,6 +227,31 @@ body: |
$vgpr0_vgpr1 = COPY %3(s64)
...
+---
+name: test_sbfx_s64_vii_full
+legalized: true
+
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sbfx_s64_vii_full
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 64
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_CONSTANT i32 0
+ %2:_(s32) = G_CONSTANT i32 64
+ %3:_(s64) = G_SBFX %0, %1(s32), %2
+ $vgpr0_vgpr1 = COPY %3(s64)
+...
+
---
name: test_sbfx_s64_svv
legalized: true
@@ -295,11 +320,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 63
- ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(i32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(i32) = G_SHL [[COPY2]], [[C1]](i32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:sgpr(i32) = G_OR [[AND]], [[SHL]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(i32) = G_SHL [[COPY2]], [[C]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:sgpr(i32) = G_OR [[COPY1]], [[SHL]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32(s32) = COPY [[COPY]](s32)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32(i32) = COPY [[OR]](i32)
; CHECK-NEXT: [[S_BFE_I32_:%[0-9]+]]:sreg_32(s32) = S_BFE_I32 [[COPY3]](s32), [[COPY4]](i32), implicit-def $scc
@@ -326,13 +349,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 63
- ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[C5:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655360
- ; CHECK-NEXT: [[C6:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655361
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655360
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655361
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32(i32) = COPY [[C6]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32(i32) = COPY [[C4]](i32)
; CHECK-NEXT: [[S_BFE_I32_:%[0-9]+]]:sreg_32(s32) = S_BFE_I32 [[COPY1]](s32), [[COPY2]](i32), implicit-def $scc
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[S_BFE_I32_]](s32)
; CHECK-NEXT: $sgpr0 = COPY [[COPY3]](s32)
@@ -359,11 +380,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 63
- ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(i32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(i32) = G_SHL [[COPY2]], [[C1]](i32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:sgpr(i32) = G_OR [[AND]], [[SHL]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(i32) = G_SHL [[COPY2]], [[C]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:sgpr(i32) = G_OR [[COPY1]], [[SHL]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_64(s64) = COPY [[COPY]](s64)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32(i32) = COPY [[OR]](i32)
; CHECK-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64(s64) = S_BFE_I64 [[COPY3]](s64), [[COPY4]](i32), implicit-def $scc
@@ -390,13 +409,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 63
- ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[C5:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655360
- ; CHECK-NEXT: [[C6:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655361
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655360
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655361
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64(s64) = COPY [[COPY]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32(i32) = COPY [[C6]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32(i32) = COPY [[C4]](i32)
; CHECK-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64(s64) = S_BFE_I64 [[COPY1]](s64), [[COPY2]](i32), implicit-def $scc
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s64) = COPY [[S_BFE_I64_]](s64)
%0:_(s64) = COPY $sgpr0_sgpr1
@@ -404,3 +421,49 @@ body: |
%2:_(s32) = G_CONSTANT i32 10
%3:_(s64) = G_SBFX %0, %1(s32), %2
...
+
+---
+name: test_sbfx_s64_sii_full
+legalized: true
+
+body: |
+ bb.0.entry:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: test_sbfx_s64_sii_full
+ ; CHECK: liveins: $sgpr0_sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 64
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:sgpr(s64) = G_ASHR [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[ASHR]](s64)
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_CONSTANT i32 0
+ %2:_(s32) = G_CONSTANT i32 64
+ %3:_(s64) = G_SBFX %0, %1(s32), %2
+ $sgpr0_sgpr1 = COPY %3(s64)
+...
+
+---
+name: test_sbfx_s32_sii_full
+legalized: true
+
+body: |
+ bb.0.entry:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: test_sbfx_s32_sii_full
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: $sgpr0 = COPY [[ASHR]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_CONSTANT i32 0
+ %2:_(s32) = G_CONSTANT i32 32
+ %3:_(s32) = G_SBFX %0, %1(s32), %2
+ $sgpr0 = COPY %3(s32)
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
index 73b59bb86c1f0..0cc2e896be184 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
@@ -195,6 +195,31 @@ body: |
$vgpr0_vgpr1 = COPY %3(s64)
...
+---
+name: test_ubfx_s64_vii_full
+legalized: true
+
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_ubfx_s64_vii_full
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 64
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(s64) = G_LSHR [[COPY]], [[COPY1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_CONSTANT i32 0
+ %2:_(s32) = G_CONSTANT i32 64
+ %3:_(s64) = G_UBFX %0, %1(s32), %2
+ $vgpr0_vgpr1 = COPY %3(s64)
+...
+
---
name: test_ubfx_s64_svv
legalized: true
@@ -263,11 +288,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 63
- ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(i32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(i32) = G_SHL [[COPY2]], [[C1]](i32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:sgpr(i32) = G_OR [[AND]], [[SHL]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(i32) = G_SHL [[COPY2]], [[C]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:sgpr(i32) = G_OR [[COPY1]], [[SHL]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32(s32) = COPY [[COPY]](s32)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32(i32) = COPY [[OR]](i32)
; CHECK-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32(s32) = S_BFE_U32 [[COPY3]](s32), [[COPY4]](i32), implicit-def $scc
@@ -294,13 +317,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 63
- ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[C5:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655360
- ; CHECK-NEXT: [[C6:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655361
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655360
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655361
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32(i32) = COPY [[C6]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32(i32) = COPY [[C4]](i32)
; CHECK-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32(s32) = S_BFE_U32 [[COPY1]](s32), [[COPY2]](i32), implicit-def $scc
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[S_BFE_U32_]](s32)
; CHECK-NEXT: $sgpr0 = COPY [[COPY3]](s32)
@@ -327,11 +348,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 63
- ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(i32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(i32) = G_SHL [[COPY2]], [[C1]](i32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:sgpr(i32) = G_OR [[AND]], [[SHL]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(i32) = G_SHL [[COPY2]], [[C]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:sgpr(i32) = G_OR [[COPY1]], [[SHL]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_64(s64) = COPY [[COPY]](s64)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32(i32) = COPY [[OR]](i32)
; CHECK-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64(s64) = S_BFE_U64 [[COPY3]](s64), [[COPY4]](i32), implicit-def $scc
@@ -358,13 +377,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 63
- ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[C5:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655360
- ; CHECK-NEXT: [[C6:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655361
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655360
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 655361
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64(s64) = COPY [[COPY]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32(i32) = COPY [[C6]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32(i32) = COPY [[C4]](i32)
; CHECK-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64(s64) = S_BFE_U64 [[COPY1]](s64), [[COPY2]](i32), implicit-def $scc
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s64) = COPY [[S_BFE_U64_]](s64)
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[COPY3]](s64)
@@ -374,3 +391,49 @@ body: |
%3:_(s64) = G_UBFX %0, %1(s32), %2
$sgpr0_sgpr1 = COPY %3(s64)
...
+
+---
+name: test_ubfx_s64_sii_full
+legalized: true
+
+body: |
+ bb.0.entry:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: test_ubfx_s64_sii_full
+ ; CHECK: liveins: $sgpr0_sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 64
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s64) = G_LSHR [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[LSHR]](s64)
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_CONSTANT i32 0
+ %2:_(s32) = G_CONSTANT i32 64
+ %3:_(s64) = G_UBFX %0, %1(s32), %2
+ $sgpr0_sgpr1 = COPY %3(s64)
+...
+
+---
+name: test_ubfx_s32_sii_full
+legalized: true
+
+body: |
+ bb.0.entry:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: test_ubfx_s32_sii_full
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: $sgpr0 = COPY [[LSHR]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_CONSTANT i32 0
+ %2:_(s32) = G_CONSTANT i32 32
+ %3:_(s32) = G_UBFX %0, %1(s32), %2
+ $sgpr0 = COPY %3(s32)
+...
>From 5ea7f67a2af2568b22e37c8b00958f21a936d55e Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Tue, 8 Sep 2026 13:12:59 +0200
Subject: [PATCH 2/2] address comment
---
llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp | 10 ++++++
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 5 ---
llvm/unittests/CodeGen/GlobalISel/CSETest.cpp | 36 +++++++++++++++++++
3 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
index f6bdb470219d9..a35f21898ae23 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
@@ -239,6 +239,16 @@ MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc,
return buildConstant(DstOps[0], *Cst);
break;
}
+ case TargetOpcode::G_UBFX:
+ case TargetOpcode::G_SBFX: {
+ assert(SrcOps.size() == 3 && "Invalid sources");
+ assert(DstOps.size() == 1 && "Invalid dsts");
+ if (auto Width =
+ getIConstantVRegValWithLookThrough(SrcOps[2].getReg(), *getMRI());
+ Width && Width->Value.isZero())
+ return buildConstant(DstOps[0], 0);
+ break;
+ }
case TargetOpcode::G_FADD:
case TargetOpcode::G_FSUB:
case TargetOpcode::G_FMUL:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 1e9d92ed5fbf8..477ecf741e9d1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -759,11 +759,6 @@ bool RegBankLegalizeHelper::lowerV_BFE(MachineInstr &MI) {
WidthImm = ConstWidth->Value.getZExtValue();
if (IsIntrinsic) {
WidthImm &= 63;
- if (WidthImm == 0) {
- B.buildConstant(Dst, 0);
- MI.eraseFromParent();
- return true;
- }
// The Width operand is out of range, use the masked value.
if (WidthImm != ConstWidth->Value.getZExtValue())
Width = B.buildConstant(VgprRB_I32, WidthImm).getReg(0);
diff --git a/llvm/unittests/CodeGen/GlobalISel/CSETest.cpp b/llvm/unittests/CodeGen/GlobalISel/CSETest.cpp
index 6255ac3293a08..8be17d731ffeb 100644
--- a/llvm/unittests/CodeGen/GlobalISel/CSETest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/CSETest.cpp
@@ -668,4 +668,40 @@ TEST_F(AArch64GISelMITest, TestConstantFoldICMP) {
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
}
+TEST_F(AArch64GISelMITest, TestConstantFoldBFX) {
+ setUp();
+ if (!TM)
+ GTEST_SKIP();
+
+ LLT s32 = LLT::scalar(32);
+ LLT s64 = LLT::scalar(64);
+
+ GISelCSEInfo CSEInfo;
+ CSEInfo.setCSEConfig(std::make_unique<CSEConfigConstantOnly>());
+ CSEInfo.analyze(*MF);
+ B.setCSEInfo(&CSEInfo);
+ CSEMIRBuilder CSEB(B.getState());
+
+ auto Lsb = CSEB.buildConstant(s32, 4);
+ auto Width0 = CSEB.buildConstant(s32, 0);
+ auto Width8 = CSEB.buildConstant(s32, 8);
+
+ // A zero-width extract always folds to 0, regardless of Src.
+ auto *Ubfx0 = &*CSEB.buildUbfx(s64, Copies[0], Lsb, Width0);
+ EXPECT_TRUE(Ubfx0->getOpcode() == TargetOpcode::G_CONSTANT);
+ EXPECT_EQ(Ubfx0->getOperand(1).getCImm()->getZExtValue(), 0U);
+
+ auto *Sbfx0 = &*CSEB.buildSbfx(s64, Copies[0], Lsb, Width0);
+ EXPECT_TRUE(Sbfx0->getOpcode() == TargetOpcode::G_CONSTANT);
+ EXPECT_EQ(Sbfx0->getOperand(1).getCImm()->getZExtValue(), 0U);
+
+ // Non-zero constant width, or non-constant width: no fold.
+ auto *Ubfx8 = &*CSEB.buildUbfx(s64, Copies[0], Lsb, Width8);
+ EXPECT_TRUE(Ubfx8->getOpcode() == TargetOpcode::G_UBFX);
+
+ auto TruncWidth = CSEB.buildInstr(TargetOpcode::G_TRUNC, {s32}, {Copies[1]});
+ auto *SbfxVar = &*CSEB.buildSbfx(s64, Copies[0], Lsb, TruncWidth);
+ EXPECT_TRUE(SbfxVar->getOpcode() == TargetOpcode::G_SBFX);
+}
+
} // namespace
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