[llvm] [GlobalISel][AArch64] Do not remove dst type predicates from pattern children nodes. (PR #221576)

[Matt Arsenault via llvm-commits]

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@@ -1628,8 +1628,15 @@ void InstructionMatcher::optimize() {
 
   if (InsnVarID > 0) {
     assert(!Operands.empty() && "Nested instruction is expected to def a vreg");
-    for (auto &OP : Operands[0]->predicates())
+    for (auto &OP : Operands[0]->predicates()) {
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arsenm wrote:

I don't understand this loop, previously it was just removing all predicted? Should this check be somewhere else?

https://github.com/llvm/llvm-project/pull/221576