[llvm] [AMDGPU] Prevent VOP3 from receiving 64b relocations as immediates (PR #221932)

[Matt Arsenault via llvm-commits]

================
@@ -5032,6 +5032,20 @@ bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
 
   assert((MO.isTargetIndex() || MO.isFI() || MO.isGlobal()) &&
          "unexpected imm-like operand kind");
+
+  // VOP3 instructions do not support 64b literals so cannot support 64b relocs
+  if (MO.isGlobal() && SIInstrFlags::isVOP3Like(InstDesc)) {
----------------
arsenm wrote:

This shouldn't need the encoding special case, I'd expect isLiteralOperandLegal to report the correct answer 

https://github.com/llvm/llvm-project/pull/221932