[llvm] [AMDGPU] Prevent VOP3 from receiving 64b relocations as immediates (PR #221932)

[Carl Ritson via llvm-commits]

https://github.com/perlfu created https://github.com/llvm/llvm-project/pull/221932

SIInstrInfo::isImmOperandLegal must block 64b immediates on VOP3 instructions, specifically memory addresses (via relocations). This fixes an issues allowing SIFoldOperands to create illegal instructions.

>From 1a45bd81507e6c4936afda06c07ce6dfb7b8739d Mon Sep 17 00:00:00 2001
From: Carl Ritson <carl.ritson at amd.com>
Date: Tue, 8 Sep 2026 18:04:31 +0900
Subject: [PATCH] [AMDGPU] Prevent VOP3 from receiving 64b relocations as
 immediates

SIInstrInfo::isImmOperandLegal must block 64b immediates on VOP3
instructions, specifically memory addresses (via relocations).
This fixes an issues allowing SIFoldOperands to create illegal
instructions.
---
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp        | 14 +++++
 .../AMDGPU/si-fold-operands-64b-reloc.mir     | 60 +++++++++++++++++++
 2 files changed, 74 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/si-fold-operands-64b-reloc.mir

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 173c88f6c17fd..9b1fbbdbfbede 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5032,6 +5032,20 @@ bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
 
   assert((MO.isTargetIndex() || MO.isFI() || MO.isGlobal()) &&
          "unexpected imm-like operand kind");
+
+  // VOP3 instructions do not support 64b literals so cannot support 64b relocs
+  if (MO.isGlobal() && SIInstrFlags::isVOP3Like(InstDesc)) {
+    switch (MO.getTargetFlags() & SIInstrInfo::MO_MASK) {
+    case SIInstrInfo::MO_ABS64:
+    case SIInstrInfo::MO_GOTPCREL:
+    case SIInstrInfo::MO_GOTPCREL64:
+    case SIInstrInfo::MO_REL64:
+      return false;
+    default:
+      break;
+    }
+  }
+
   const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];
   return isLiteralOperandLegal(InstDesc, OpInfo);
 }
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-operands-64b-reloc.mir b/llvm/test/CodeGen/AMDGPU/si-fold-operands-64b-reloc.mir
new file mode 100644
index 0000000000000..68a9dba012370
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-operands-64b-reloc.mir
@@ -0,0 +1,60 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgpu13.10 -run-pass=si-fold-operands -o - %s | FileCheck -check-prefixes=GFX1310
+
+--- |
+  @mem = internal unnamed_addr addrspace(4) constant [4 x <4 x i32>] [<4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>]
+
+  define amdgpu_cs void @fold_vop3_abs64_sgpr() { ret void }
+  define amdgpu_cs void @fold_vop3_abs64_vgpr() { ret void }
+  define amdgpu_cs void @fold_vop3_rel64_sgpr() { ret void }
+  define amdgpu_cs void @fold_vop3_rel64_vgpr() { ret void }
+---
+
+# Cannot fold 64b immediates into VOP3 instructions
+---
+name: fold_vop3_abs64_sgpr
+tracksRegLiveness: true
+body: |
+  bb.0:
+    ; GFX1310-LABEL: name: fold_vop3_abs64_sgpr
+    ; GFX1310: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-abs64) @mem
+    ; GFX1310-NEXT: %1:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 0, 0, [[S_MOV_B64_]], 0, implicit $exec
+    %0:sreg_64 = S_MOV_B64 target-flags(amdgpu-abs64) @mem
+    %1:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 0, 0, %0:sreg_64, 0, implicit $exec
+...
+
+---
+name: fold_vop3_abs64_vgpr
+tracksRegLiveness: true
+body: |
+  bb.0:
+    ; GFX1310-LABEL: name: fold_vop3_abs64_vgpr
+    ; GFX1310: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO target-flags(amdgpu-abs64) @mem, implicit $exec
+    ; GFX1310-NEXT: %1:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 0, 0, [[V_MOV_B]], 0, implicit $exec
+    %0:vreg_64 = V_MOV_B64_PSEUDO target-flags(amdgpu-abs64) @mem, implicit $exec
+    %1:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 0, 0, %0:vreg_64, 0, implicit $exec
+...
+
+---
+name: fold_vop3_rel64_sgpr
+tracksRegLiveness: true
+body: |
+  bb.0:
+    ; GFX1310-LABEL: name: fold_vop3_rel64_sgpr
+    ; GFX1310: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-rel64) @mem
+    ; GFX1310-NEXT: %1:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 0, 0, [[S_MOV_B64_]], 0, implicit $exec
+    %0:sreg_64 = S_MOV_B64 target-flags(amdgpu-rel64) @mem
+    %1:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 0, 0, %0:sreg_64, 0, implicit $exec
+...
+
+---
+name: fold_vop3_rel64_vgpr
+tracksRegLiveness: true
+body: |
+  bb.0:
+    ; GFX1310-LABEL: name: fold_vop3_rel64_vgpr
+    ; GFX1310: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO target-flags(amdgpu-rel64) @mem, implicit $exec
+    ; GFX1310-NEXT: %1:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 0, 0, [[V_MOV_B]], 0, implicit $exec
+    %0:vreg_64 = V_MOV_B64_PSEUDO target-flags(amdgpu-rel64) @mem, implicit $exec
+    %1:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 0, 0, %0:vreg_64, 0, implicit $exec
+...