[llvm] llvm: Remove phantom fp-contract-model attributes from tests (PR #221925)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

<details>
<summary>Changes</summary>

This attribute has never been consumed by upstream llvm,
or emitted by upstream clang. I can only guess this existed in
at least one downstream fork.

---
Full diff: https://github.com/llvm/llvm-project/pull/221925.diff


8 Files Affected:

- (modified) llvm/test/CodeGen/AArch64/arm64-abi_align.ll (+4-4) 
- (modified) llvm/test/CodeGen/AMDGPU/loop-address.ll (+1-1) 
- (modified) llvm/test/CodeGen/Hexagon/insert4.ll (+1-1) 
- (modified) llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll (+1-1) 
- (modified) llvm/test/CodeGen/Hexagon/vect/vect-xor.ll (+1-1) 
- (modified) llvm/test/Transforms/LoopVectorize/dbg.value.ll (+1-1) 
- (modified) llvm/test/Transforms/LoopVectorize/vectorize-once.ll (+1-1) 
- (modified) llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll (+2-2) 


``````````diff
diff --git a/llvm/test/CodeGen/AArch64/arm64-abi_align.ll b/llvm/test/CodeGen/AArch64/arm64-abi_align.ll
index 7b779ddbab55f..f2f97ba4a9e71 100644
--- a/llvm/test/CodeGen/AArch64/arm64-abi_align.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-abi_align.ll
@@ -507,10 +507,10 @@ entry:
   ret i32 %call
 }
 
-attributes #0 = { noinline nounwind readnone "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" }
-attributes #1 = { nounwind readonly "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" }
-attributes #2 = { noinline nounwind readonly "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" }
-attributes #3 = { nounwind "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" }
+attributes #0 = { noinline nounwind readnone "relocation-model"="pic" "ssp-buffers-size"="8" }
+attributes #1 = { nounwind readonly "relocation-model"="pic" "ssp-buffers-size"="8" }
+attributes #2 = { noinline nounwind readonly "relocation-model"="pic" "ssp-buffers-size"="8" }
+attributes #3 = { nounwind "relocation-model"="pic" "ssp-buffers-size"="8" }
 attributes #4 = { nounwind }
 attributes #5 = { nobuiltin }
 
diff --git a/llvm/test/CodeGen/AMDGPU/loop-address.ll b/llvm/test/CodeGen/AMDGPU/loop-address.ll
index cd7297ece25ed..8ec52a9444fb6 100644
--- a/llvm/test/CodeGen/AMDGPU/loop-address.ll
+++ b/llvm/test/CodeGen/AMDGPU/loop-address.ll
@@ -24,7 +24,7 @@ for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
-attributes #0 = { nounwind "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" }
+attributes #0 = { nounwind "relocation-model"="pic" "ssp-buffers-size"="8" }
 
 !opencl.kernels = !{!0, !1, !2, !3}
 
diff --git a/llvm/test/CodeGen/Hexagon/insert4.ll b/llvm/test/CodeGen/Hexagon/insert4.ll
index 1e27a4450a4ce..2ed9f31c6ad7f 100644
--- a/llvm/test/CodeGen/Hexagon/insert4.ll
+++ b/llvm/test/CodeGen/Hexagon/insert4.ll
@@ -103,7 +103,7 @@ declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) #1
 
 declare i64 @llvm.hexagon.A2.vaddhs(i64, i64) #1
 
-attributes #0 = { nounwind "fp-contract-model"="standard" "frame-pointer"="non-leaf" "realign-stack" "relocation-model"="static" "ssp-buffers-size"="8" }
+attributes #0 = { nounwind "frame-pointer"="non-leaf" "realign-stack" "relocation-model"="static" "ssp-buffers-size"="8" }
 attributes #1 = { nounwind readnone }
 
 !0 = !{!"short", !1}
diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll b/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
index eb54124d636ed..a85f3e9214ff9 100644
--- a/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
+++ b/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
@@ -67,4 +67,4 @@ polly.stmt.for.body29:                            ; preds = %polly.stmt.for.body
   br i1 %exitcond, label %for.end.loopexit, label %polly.stmt.for.body29
 }
 
-attributes #0 = { nounwind "fp-contract-model"="standard" "frame-pointer"="non-leaf" "realign-stack" "relocation-model"="static" "ssp-buffers-size"="8" }
+attributes #0 = { nounwind "frame-pointer"="non-leaf" "realign-stack" "relocation-model"="static" "ssp-buffers-size"="8" }
diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-xor.ll b/llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
index 0f8526a436248..4d5f6f8802d0e 100644
--- a/llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
+++ b/llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
@@ -34,4 +34,4 @@ polly.loop_body:                                  ; preds = %entry, %polly.loop_
   br i1 %0, label %polly.loop_body, label %polly.loop_after
 }
 
-attributes #0 = { nounwind "fp-contract-model"="standard" "frame-pointer"="non-leaf" "realign-stack" "relocation-model"="static" "ssp-buffers-size"="8" }
+attributes #0 = { nounwind "frame-pointer"="non-leaf" "realign-stack" "relocation-model"="static" "ssp-buffers-size"="8" }
diff --git a/llvm/test/Transforms/LoopVectorize/dbg.value.ll b/llvm/test/Transforms/LoopVectorize/dbg.value.ll
index 01134d8e2d4a6..9996a8b011e1c 100644
--- a/llvm/test/Transforms/LoopVectorize/dbg.value.ll
+++ b/llvm/test/Transforms/LoopVectorize/dbg.value.ll
@@ -35,7 +35,7 @@ for.end:
 }
 
 
-attributes #0 = { "fp-contract-model"="standard" "frame-pointer"="non-leaf" "relocation-model"="pic" "ssp-buffers-size"="8" }
+attributes #0 = { "frame-pointer"="non-leaf" "relocation-model"="pic" "ssp-buffers-size"="8" }
 
 !llvm.dbg.cu = !{!11}
 !llvm.module.flags = !{!14}
diff --git a/llvm/test/Transforms/LoopVectorize/vectorize-once.ll b/llvm/test/Transforms/LoopVectorize/vectorize-once.ll
index 0a0bb5d1b8132..56a4172c51bbe 100644
--- a/llvm/test/Transforms/LoopVectorize/vectorize-once.ll
+++ b/llvm/test/Transforms/LoopVectorize/vectorize-once.ll
@@ -67,7 +67,7 @@ _ZSt10accumulateIPiiET0_T_S2_S1_.exit:
   ret i32 %__init.addr.0.lcssa.i
 }
 
-attributes #0 = { nounwind readonly ssp uwtable "fp-contract-model"="standard" "frame-pointer"="non-leaf" "realign-stack" "relocation-model"="pic" "ssp-buffers-size"="8" }
+attributes #0 = { nounwind readonly ssp uwtable "frame-pointer"="non-leaf" "realign-stack" "relocation-model"="pic" "ssp-buffers-size"="8" }
 
 ; CHECK:      [[VEC_LOOP1]] = distinct !{[[VEC_LOOP1]], [[MD_IS_VEC:![0-9]+]], [[MD_RT_UNROLL_DIS:![0-9]+]]}
 ; CHECK-NEXT: [[MD_IS_VEC:![0-9]+]] = !{!"llvm.loop.isvectorized", i32 1}
diff --git a/llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll b/llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
index 8d775596a2d9a..8ea416b3f9b58 100644
--- a/llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
+++ b/llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
@@ -57,8 +57,8 @@ end:
 }
 declare i32 @Trace(...) #1
 
-attributes #0 = { nounwind ssp uwtable "fp-contract-model"="standard" "frame-pointer"="non-leaf" "relocation-model"="pic" "ssp-buffers-size"="8" }
-attributes #1 = { "fp-contract-model"="standard" "frame-pointer"="non-leaf" "relocation-model"="pic" "ssp-buffers-size"="8" }
+attributes #0 = { nounwind ssp uwtable "frame-pointer"="non-leaf" "relocation-model"="pic" "ssp-buffers-size"="8" }
+attributes #1 = { "frame-pointer"="non-leaf" "relocation-model"="pic" "ssp-buffers-size"="8" }
 attributes #2 = { nounwind }
 
 !0 = !{i32 1039}

``````````

</details>


https://github.com/llvm/llvm-project/pull/221925