[llvm] [AggressiveInstCombine] Add shufflevector support to TruncInstCombine (PR #220218)

[via llvm-commits]

https://github.com/zhangweize9-cyber commented:

If you have verified that the newly generated IR logic is indeed correct for `i32 -> i16`, just running `utils/update_test_checks.py` script on your test file to refresh the `CHECK` lines.

https://github.com/llvm/llvm-project/pull/220218