[llvm] [GVN] MemorySSA for GVN: switch to using MemorySSA by default (PR #221916)
Antonio Frighetto via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 8 01:23:03 PDT 2026
https://github.com/antoniofrighetto created https://github.com/llvm/llvm-project/pull/221916
Enable MemorySSA by default, as part of transitioning away from MemoryDependenceAnalysis and leveraging more redundant load elimination opportunities.
---
Original patch: https://reviews.llvm.org/D120421.
>From 0d39924f8f0c50c6045c2b105f091791cdd2f383 Mon Sep 17 00:00:00 2001
From: Momchil Velikov <momchil.velikov at arm.com>
Date: Tue, 8 Sep 2026 10:20:46 +0200
Subject: [PATCH] [GVN] MemorySSA for GVN: switch to using MemorySSA by default
Enable MemorySSA by default, as part of transitioning away from
MemoryDependenceAnalysis and leveraging more redundant load
elimination opportunities.
---
llvm/lib/Transforms/Scalar/GVN.cpp | 4 +-
.../MemoryDependenceAnalysis/InvariantLoad.ll | 17 ++-
.../gvn-nonlocal-type-mismatch.ll | 73 +++-------
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll | 4 +-
llvm/test/Other/new-pm-defaults.ll | 1 -
llvm/test/Other/new-pm-lto-defaults.ll | 1 -
.../Other/new-pm-thinlto-postlink-defaults.ll | 1 -
.../new-pm-thinlto-postlink-pgo-defaults.ll | 1 -
...-pm-thinlto-postlink-samplepgo-defaults.ll | 1 -
.../Other/new-pm-thinlto-prelink-defaults.ll | 1 -
.../new-pm-thinlto-prelink-pgo-defaults.ll | 1 -
...w-pm-thinlto-prelink-samplepgo-defaults.ll | 1 -
llvm/test/Transforms/GVN/PRE/rle.ll | 134 ++++++------------
llvm/test/Transforms/GVN/no-mem-dep-info.ll | 4 +-
.../X86/loop-vectorize-metadata.ll | 2 +-
15 files changed, 83 insertions(+), 163 deletions(-)
diff --git a/llvm/lib/Transforms/Scalar/GVN.cpp b/llvm/lib/Transforms/Scalar/GVN.cpp
index 2f34f9124e580..dab94286e9526 100644
--- a/llvm/lib/Transforms/Scalar/GVN.cpp
+++ b/llvm/lib/Transforms/Scalar/GVN.cpp
@@ -116,9 +116,9 @@ static cl::opt<bool> GVNEnableLoadInLoopPRE("enable-load-in-loop-pre",
static cl::opt<bool>
GVNEnableSplitBackedgeInLoadPRE("enable-split-backedge-in-load-pre",
cl::init(false));
-static cl::opt<bool> GVNEnableMemDep("enable-gvn-memdep", cl::init(true));
+static cl::opt<bool> GVNEnableMemDep("enable-gvn-memdep", cl::init(false));
static cl::opt<bool> GVNEnableMemorySSA("enable-gvn-memoryssa",
- cl::init(false));
+ cl::init(true));
static cl::opt<unsigned> ScanUsersLimit(
"gvn-scan-users-limit", cl::Hidden, cl::init(100),
diff --git a/llvm/test/Analysis/MemoryDependenceAnalysis/InvariantLoad.ll b/llvm/test/Analysis/MemoryDependenceAnalysis/InvariantLoad.ll
index e49db3d8c3e8e..acd3b42e25afe 100644
--- a/llvm/test/Analysis/MemoryDependenceAnalysis/InvariantLoad.ll
+++ b/llvm/test/Analysis/MemoryDependenceAnalysis/InvariantLoad.ll
@@ -10,20 +10,19 @@ declare void @foo(ptr)
define i8 @test(i1 %cmp) {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[P:%.*]] = alloca i8
-; CHECK-NEXT: store i8 5, ptr [[P]]
+; CHECK-NEXT: [[P:%.*]] = alloca i8, align 1
+; CHECK-NEXT: store i8 5, ptr [[P]], align 1
; CHECK-NEXT: br label [[HEADER:%.*]]
; CHECK: header:
-; CHECK-NEXT: [[V:%.*]] = phi i8 [ 5, [[ENTRY:%.*]] ], [ -5, [[ALIVE:%.*]] ]
-; CHECK-NEXT: [[I:%.*]] = phi i8 [ 0, [[ENTRY]] ], [ [[I_INC:%.*]], [[ALIVE]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i8 [ 0, [[ENTRY:%.*]] ], [ [[I_INC:%.*]], [[ALIVE:%.*]] ]
; CHECK-NEXT: br i1 [[CMP:%.*]], label [[ALIVE]], label [[DEAD:%.*]]
; CHECK: dead:
; CHECK-NEXT: call void @foo(ptr [[P]])
-; CHECK-NEXT: [[I_1:%.*]] = add i8 [[I]], [[V]]
+; CHECK-NEXT: [[I_1:%.*]] = add i8 [[I]], 5
; CHECK-NEXT: br label [[ALIVE]]
; CHECK: alive:
; CHECK-NEXT: [[I_2:%.*]] = phi i8 [ [[I]], [[HEADER]] ], [ [[I_1]], [[DEAD]] ]
-; CHECK-NEXT: store i8 -5, ptr [[P]]
+; CHECK-NEXT: store i8 -5, ptr [[P]], align 1
; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[P]], i8 0, i32 1, i1 false)
; CHECK-NEXT: [[I_INC]] = add i8 [[I_2]], 1
; CHECK-NEXT: [[CMP_LOOP:%.*]] = icmp ugt i8 [[I_INC]], 100
@@ -67,7 +66,7 @@ define i8 @test2(i1 %cmp, ptr %p) {
; CHECK-NEXT: call void @foo(ptr [[P]])
; CHECK-NEXT: br i1 [[CMP:%.*]], label [[B2:%.*]], label [[B1:%.*]]
; CHECK: b1:
-; CHECK-NEXT: [[RES2:%.*]] = load i8, ptr [[P]]
+; CHECK-NEXT: [[RES2:%.*]] = load i8, ptr [[P]], align 1
; CHECK-NEXT: [[RES3:%.*]] = add i8 [[RES1]], [[RES2]]
; CHECK-NEXT: br label [[ALIVE:%.*]]
; CHECK: b2:
@@ -105,7 +104,7 @@ define i8 @test3(i1 %cmp, ptr %p) {
; CHECK-NEXT: call void @foo(ptr [[P]])
; CHECK-NEXT: br i1 [[CMP:%.*]], label [[B1:%.*]], label [[B2:%.*]]
; CHECK: b1:
-; CHECK-NEXT: [[RES2:%.*]] = load i8, ptr [[P]]
+; CHECK-NEXT: [[RES2:%.*]] = load i8, ptr [[P]], align 1
; CHECK-NEXT: [[RES3:%.*]] = add i8 [[RES1]], [[RES2]]
; CHECK-NEXT: br label [[ALIVE:%.*]]
; CHECK: b2:
@@ -148,7 +147,7 @@ define void @test4() null_pointer_is_valid {
; CHECK-NEXT: [[TMP4:%.*]] = fmul float [[TMP2]], [[TMP2]]
; CHECK-NEXT: [[INVAR_INC3]] = add nuw nsw i64 [[FUSION_INVAR_ADDRESS_DIM_0_03]], 1
; CHECK-NEXT: [[DOTPHI_TRANS_INSERT:%.*]] = getelementptr inbounds [2 x [1 x [4 x float]]], ptr null, i64 0, i64 [[INVAR_INC3]], i64 0, i64 2
-; CHECK-NEXT: [[DOTPRE]] = load float, ptr [[DOTPHI_TRANS_INSERT]], align 4, !invariant.load !0
+; CHECK-NEXT: [[DOTPRE]] = load float, ptr [[DOTPHI_TRANS_INSERT]], align 4, !invariant.load [[META0:![0-9]+]]
; CHECK-NEXT: br label [[FUSION_LOOP_HEADER_DIM_1_PREHEADER]]
;
entry:
diff --git a/llvm/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll b/llvm/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll
index f314bcadfa516..dd4df48ab0cba 100644
--- a/llvm/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll
+++ b/llvm/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -aa-pipeline=tbaa,basic-aa -passes=gvn -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-MEMDEP
-; RUN: opt -aa-pipeline=tbaa,basic-aa -passes='gvn<memoryssa>' -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-MEMSSA
+; RUN: opt -aa-pipeline=tbaa,basic-aa -passes=gvn -S < %s | FileCheck %s --check-prefixes=CHECK
target datalayout = "e-p:64:64:64"
@@ -40,34 +39,19 @@ if.else:
; should just be conservative.
define void @watch_out_for_type_change(i1 %c, ptr %p, ptr %p1, ptr %q) nounwind {
-; CHECK-MEMDEP-LABEL: define void @watch_out_for_type_change(
-; CHECK-MEMDEP-SAME: i1 [[C:%.*]], ptr [[P:%.*]], ptr [[P1:%.*]], ptr [[Q:%.*]]) #[[ATTR0]] {
-; CHECK-MEMDEP-NEXT: [[ENTRY:.*:]]
-; CHECK-MEMDEP-NEXT: store i32 0, ptr [[P]], align 4, !tbaa [[RED_TBAA0]]
-; CHECK-MEMDEP-NEXT: store i32 1, ptr [[P1]], align 4, !tbaa [[BLU_TBAA3]]
-; CHECK-MEMDEP-NEXT: br i1 [[C]], label %[[IF_ELSE:.*]], label %[[IF_THEN:.*]]
-; CHECK-MEMDEP: [[IF_THEN]]:
-; CHECK-MEMDEP-NEXT: [[T:%.*]] = load i32, ptr [[P]], align 4, !tbaa [[OUTER_SPACE_TBAA5:![0-9]+]]
-; CHECK-MEMDEP-NEXT: store i32 [[T]], ptr [[Q]], align 4
-; CHECK-MEMDEP-NEXT: ret void
-; CHECK-MEMDEP: [[IF_ELSE]]:
-; CHECK-MEMDEP-NEXT: [[U:%.*]] = load i32, ptr [[P]], align 4, !tbaa [[BRICK_RED_TBAA8:![0-9]+]]
-; CHECK-MEMDEP-NEXT: store i32 [[U]], ptr [[Q]], align 4
-; CHECK-MEMDEP-NEXT: ret void
-;
-; CHECK-MEMSSA-LABEL: define void @watch_out_for_type_change(
-; CHECK-MEMSSA-SAME: i1 [[C:%.*]], ptr [[P:%.*]], ptr [[P1:%.*]], ptr [[Q:%.*]]) #[[ATTR0]] {
-; CHECK-MEMSSA-NEXT: [[ENTRY:.*:]]
-; CHECK-MEMSSA-NEXT: store i32 0, ptr [[P]], align 4, !tbaa [[RED_TBAA0]]
-; CHECK-MEMSSA-NEXT: store i32 1, ptr [[P1]], align 4, !tbaa [[BLU_TBAA3]]
-; CHECK-MEMSSA-NEXT: br i1 [[C]], label %[[IF_ELSE:.*]], label %[[IF_THEN:.*]]
-; CHECK-MEMSSA: [[IF_THEN]]:
-; CHECK-MEMSSA-NEXT: [[T:%.*]] = load i32, ptr [[P]], align 4, !tbaa [[OUTER_SPACE_TBAA5:![0-9]+]]
-; CHECK-MEMSSA-NEXT: store i32 [[T]], ptr [[Q]], align 4
-; CHECK-MEMSSA-NEXT: ret void
-; CHECK-MEMSSA: [[IF_ELSE]]:
-; CHECK-MEMSSA-NEXT: store i32 0, ptr [[Q]], align 4
-; CHECK-MEMSSA-NEXT: ret void
+; CHECK-LABEL: define void @watch_out_for_type_change(
+; CHECK-SAME: i1 [[C:%.*]], ptr [[P:%.*]], ptr [[P1:%.*]], ptr [[Q:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: store i32 0, ptr [[P]], align 4, !tbaa [[RED_TBAA0]]
+; CHECK-NEXT: store i32 1, ptr [[P1]], align 4, !tbaa [[BLU_TBAA3]]
+; CHECK-NEXT: br i1 [[C]], label %[[IF_ELSE:.*]], label %[[IF_THEN:.*]]
+; CHECK: [[IF_THEN]]:
+; CHECK-NEXT: [[T:%.*]] = load i32, ptr [[P]], align 4, !tbaa [[OUTER_SPACE_TBAA5:![0-9]+]]
+; CHECK-NEXT: store i32 [[T]], ptr [[Q]], align 4
+; CHECK-NEXT: ret void
+; CHECK: [[IF_ELSE]]:
+; CHECK-NEXT: store i32 0, ptr [[Q]], align 4
+; CHECK-NEXT: ret void
;
entry:
store i32 0, ptr %p, !tbaa !1
@@ -99,7 +83,7 @@ define void @watch_out_for_another_type_change(i1 %c, ptr %p, ptr %p1, ptr %q) n
; CHECK-NEXT: store i32 0, ptr [[Q]], align 4
; CHECK-NEXT: ret void
; CHECK: [[IF_ELSE]]:
-; CHECK-NEXT: [[U:%.*]] = load i32, ptr [[P]], align 4, !tbaa [[OUTER_SPACE_TBAA5:![0-9]+]]
+; CHECK-NEXT: [[U:%.*]] = load i32, ptr [[P]], align 4, !tbaa [[OUTER_SPACE_TBAA5]]
; CHECK-NEXT: store i32 [[U]], ptr [[Q]], align 4
; CHECK-NEXT: ret void
;
@@ -130,23 +114,12 @@ if.else:
!8 = !{!"brick red", !5}
!9 = !{!"observable universe"}
;.
-; CHECK-MEMDEP: [[RED_TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
-; CHECK-MEMDEP: [[META1]] = !{!"red", [[META2:![0-9]+]]}
-; CHECK-MEMDEP: [[META2]] = !{}
-; CHECK-MEMDEP: [[BLU_TBAA3]] = !{[[META4:![0-9]+]], [[META4]], i64 0}
-; CHECK-MEMDEP: [[META4]] = !{!"blu", [[META2]]}
-; CHECK-MEMDEP: [[OUTER_SPACE_TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0}
-; CHECK-MEMDEP: [[META6]] = !{!"outer space", [[META7:![0-9]+]]}
-; CHECK-MEMDEP: [[META7]] = !{!"observable universe"}
-; CHECK-MEMDEP: [[BRICK_RED_TBAA8]] = !{[[META9:![0-9]+]], [[META9]], i64 0}
-; CHECK-MEMDEP: [[META9]] = !{!"brick red", [[META1]]}
-;.
-; CHECK-MEMSSA: [[RED_TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
-; CHECK-MEMSSA: [[META1]] = !{!"red", [[META2:![0-9]+]]}
-; CHECK-MEMSSA: [[META2]] = !{}
-; CHECK-MEMSSA: [[BLU_TBAA3]] = !{[[META4:![0-9]+]], [[META4]], i64 0}
-; CHECK-MEMSSA: [[META4]] = !{!"blu", [[META2]]}
-; CHECK-MEMSSA: [[OUTER_SPACE_TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0}
-; CHECK-MEMSSA: [[META6]] = !{!"outer space", [[META7:![0-9]+]]}
-; CHECK-MEMSSA: [[META7]] = !{!"observable universe"}
+; CHECK: [[RED_TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
+; CHECK: [[META1]] = !{!"red", [[META2:![0-9]+]]}
+; CHECK: [[META2]] = !{}
+; CHECK: [[BLU_TBAA3]] = !{[[META4:![0-9]+]], [[META4]], i64 0}
+; CHECK: [[META4]] = !{!"blu", [[META2]]}
+; CHECK: [[OUTER_SPACE_TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0}
+; CHECK: [[META6]] = !{!"outer space", [[META7:![0-9]+]]}
+; CHECK: [[META7]] = !{!"observable universe"}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
index bb7ed3b58f8af..06308dfc2ef3c 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
@@ -1190,11 +1190,11 @@
; GCN-O3-NEXT: Straight line strength reduction
; GCN-O3-NEXT: Basic Alias Analysis (stateless AA impl)
; GCN-O3-NEXT: Function Alias Analysis Results
-; GCN-O3-NEXT: Memory Dependence Analysis
; GCN-O3-NEXT: Cycle Info Analysis
; GCN-O3-NEXT: Lazy Branch Probability Analysis
; GCN-O3-NEXT: Lazy Block Frequency Analysis
; GCN-O3-NEXT: Optimization Remark Emitter
+; GCN-O3-NEXT: Memory SSA
; GCN-O3-NEXT: Global Value Numbering
; GCN-O3-NEXT: Scalar Evolution Analysis
; GCN-O3-NEXT: Nary reassociation
@@ -1235,11 +1235,11 @@
; GCN-O3-NEXT: Natural Loop Information
; GCN-O3-NEXT: Basic Alias Analysis (stateless AA impl)
; GCN-O3-NEXT: Function Alias Analysis Results
-; GCN-O3-NEXT: Memory Dependence Analysis
; GCN-O3-NEXT: Cycle Info Analysis
; GCN-O3-NEXT: Lazy Branch Probability Analysis
; GCN-O3-NEXT: Lazy Block Frequency Analysis
; GCN-O3-NEXT: Optimization Remark Emitter
+; GCN-O3-NEXT: Memory SSA
; GCN-O3-NEXT: Global Value Numbering
; GCN-O3-NEXT: AMDGPU Preload Kernel Arguments
; GCN-O3-NEXT: FunctionPass Manager
diff --git a/llvm/test/Other/new-pm-defaults.ll b/llvm/test/Other/new-pm-defaults.ll
index 2c1a57e00c9f1..ad51c4ca9cba1 100644
--- a/llvm/test/Other/new-pm-defaults.ll
+++ b/llvm/test/Other/new-pm-defaults.ll
@@ -182,7 +182,6 @@
; CHECK-O23-NEXT: Running pass: VectorCombinePass
; CHECK-O23-NEXT: Running pass: MergedLoadStoreMotionPass
; CHECK-O23-NEXT: Running pass: GVNPass
-; CHECK-O23-NEXT: Running analysis: MemoryDependenceAnalysis
; CHECK-O1-NEXT: Running pass: MemCpyOptPass
; CHECK-O1-NEXT: Running analysis: PostDominatorTreeAnalysis
; CHECK-O-NEXT: Running pass: SCCPPass
diff --git a/llvm/test/Other/new-pm-lto-defaults.ll b/llvm/test/Other/new-pm-lto-defaults.ll
index 14f189194d0e3..1217faf1c8e25 100644
--- a/llvm/test/Other/new-pm-lto-defaults.ll
+++ b/llvm/test/Other/new-pm-lto-defaults.ll
@@ -111,7 +111,6 @@
; CHECK-O23-NEXT: Running analysis: InnerAnalysisManagerProxy
; CHECK-O23-NEXT: Running pass: LICMPass on loop
; CHECK-O23-NEXT: Running pass: GVNPass on foo
-; CHECK-O23-NEXT: Running analysis: MemoryDependenceAnalysis on foo
; CHECK-O23-NEXT: Running pass: MemCpyOptPass on foo
; CHECK-O23-NEXT: Running analysis: PostDominatorTreeAnalysis on foo
; CHECK-O23-NEXT: Running pass: DSEPass on foo
diff --git a/llvm/test/Other/new-pm-thinlto-postlink-defaults.ll b/llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
index b1fde57902b05..60e70e1fe1050 100644
--- a/llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
+++ b/llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
@@ -120,7 +120,6 @@
; CHECK-O23-NEXT: Running pass: VectorCombinePass
; CHECK-O23-NEXT: Running pass: MergedLoadStoreMotionPass
; CHECK-O23-NEXT: Running pass: GVNPass
-; CHECK-O23-NEXT: Running analysis: MemoryDependenceAnalysis
; CHECK-O1-NEXT: Running pass: MemCpyOptPass
; CHECK-O1-NEXT: Running analysis: PostDominatorTreeAnalysis
; CHECK-O-NEXT: Running pass: SCCPPass
diff --git a/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
index 441344250e2ff..1f3b30623ea60 100644
--- a/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
+++ b/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
@@ -108,7 +108,6 @@
; CHECK-O23-NEXT: Running pass: VectorCombinePass
; CHECK-O23-NEXT: Running pass: MergedLoadStoreMotionPass
; CHECK-O23-NEXT: Running pass: GVNPass
-; CHECK-O23-NEXT: Running analysis: MemoryDependenceAnalysis
; CHECK-O1-NEXT: Running pass: MemCpyOptPass
; CHECK-O-NEXT: Running pass: SCCPPass
; CHECK-O-NEXT: Running pass: BDCEPass
diff --git a/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
index 477e36e8d9aba..3304b9bc45a36 100644
--- a/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
+++ b/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
@@ -115,7 +115,6 @@
; CHECK-O23-NEXT: Running pass: VectorCombinePass
; CHECK-O23-NEXT: Running pass: MergedLoadStoreMotionPass
; CHECK-O23-NEXT: Running pass: GVNPass
-; CHECK-O23-NEXT: Running analysis: MemoryDependenceAnalysis
; CHECK-O1-NEXT: Running pass: MemCpyOptPass
; CHECK-O-NEXT: Running pass: SCCPPass
; CHECK-O-NEXT: Running pass: BDCEPass
diff --git a/llvm/test/Other/new-pm-thinlto-prelink-defaults.ll b/llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
index b07825faaa873..98119b8531694 100644
--- a/llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
+++ b/llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
@@ -146,7 +146,6 @@
; CHECK-O23-NEXT: Running pass: VectorCombinePass
; CHECK-O23-NEXT: Running pass: MergedLoadStoreMotionPass
; CHECK-O23-NEXT: Running pass: GVNPass
-; CHECK-O23-NEXT: Running analysis: MemoryDependenceAnalysis
; CHECK-O1-NEXT: Running pass: MemCpyOptPass
; CHECK-O1-NEXT: Running analysis: PostDominatorTreeAnalysis
; CHECK-O-NEXT: Running pass: SCCPPass
diff --git a/llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
index eafd8aad98e7a..9f5bf1d8363f7 100644
--- a/llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
+++ b/llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
@@ -155,7 +155,6 @@
; CHECK-O23-NEXT: Running pass: VectorCombinePass
; CHECK-O23-NEXT: Running pass: MergedLoadStoreMotionPass
; CHECK-O23-NEXT: Running pass: GVNPass
-; CHECK-O23-NEXT: Running analysis: MemoryDependenceAnalysis
; CHECK-O1-NEXT: Running pass: MemCpyOptPass
; CHECK-O-NEXT: Running pass: SCCPPass
; CHECK-O-NEXT: Running pass: BDCEPass
diff --git a/llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
index 8d42a45475c27..6a89e25cbadee 100644
--- a/llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
+++ b/llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
@@ -119,7 +119,6 @@
; CHECK-O23-NEXT: Running pass: VectorCombinePass
; CHECK-O23-NEXT: Running pass: MergedLoadStoreMotionPass
; CHECK-O23-NEXT: Running pass: GVNPass
-; CHECK-O23-NEXT: Running analysis: MemoryDependenceAnalysis
; CHECK-O1-NEXT: Running pass: MemCpyOptPass
; CHECK-O-NEXT: Running pass: SCCPPass
; CHECK-O-NEXT: Running pass: BDCEPass
diff --git a/llvm/test/Transforms/GVN/PRE/rle.ll b/llvm/test/Transforms/GVN/PRE/rle.ll
index 49fe873c0141f..b222f0de86874 100644
--- a/llvm/test/Transforms/GVN/PRE/rle.ll
+++ b/llvm/test/Transforms/GVN/PRE/rle.ll
@@ -1,8 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; RUN: opt < %s -data-layout="e-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes=gvn,dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,LE,LE-MEMDEP
-; RUN: opt < %s -data-layout="e-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes='gvn<memoryssa>',dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,LE,LE-MEMSSA
-; RUN: opt < %s -data-layout="E-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-n32" -passes=gvn,dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,BE,BE-MEMDEP
-; RUN: opt < %s -data-layout="E-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-n32" -passes='gvn<memoryssa>',dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,BE,BE-MEMSSA
+; RUN: opt < %s -data-layout="e-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes=gvn,dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,LE
+; RUN: opt < %s -data-layout="E-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-n32" -passes=gvn,dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,BE
;; Trivial RLE test.
define i32 @test0(i32 %V, ptr %P) {
@@ -809,7 +807,7 @@ define i32 @phi_trans6(ptr noalias nocapture readonly %x, i1 %cond) {
; CHECK: [[HEADER]]:
; CHECK-NEXT: [[L1:%.*]] = phi i32 [ [[L0]], %[[ENTRY]] ], [ [[L1_PRE:%.*]], %[[LATCH_HEADER_CRIT_EDGE:.*]] ]
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH_HEADER_CRIT_EDGE]] ]
-; CHECK-NEXT: indirectbr ptr blockaddress(@phi_trans6, %[[LATCH:.*]]), [label %latch]
+; CHECK-NEXT: indirectbr ptr blockaddress(@phi_trans6, %[[LATCH:.*]]), [label %[[LATCH]]]
; CHECK: [[LATCH]]:
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
; CHECK-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LATCH_HEADER_CRIT_EDGE]]
@@ -850,7 +848,7 @@ define i32 @phi_trans7(ptr noalias nocapture readonly %x, i1 %cond) {
; CHECK: [[HEADER]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 2, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH_HEADER_CRIT_EDGE:.*]] ]
; CHECK-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
-; CHECK-NEXT: indirectbr ptr blockaddress(@phi_trans7, %[[LATCH:.*]]), [label %latch]
+; CHECK-NEXT: indirectbr ptr blockaddress(@phi_trans7, %[[LATCH:.*]]), [label %[[LATCH]]]
; CHECK: [[LATCH]]:
; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
@@ -891,7 +889,7 @@ define i32 @phi_trans8(ptr noalias nocapture readonly %x, i1 %cond) {
; CHECK-NEXT: br label %[[HEADER:.*]]
; CHECK: [[HEADER]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 2, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH_HEADER_CRIT_EDGE:.*]] ]
-; CHECK-NEXT: indirectbr ptr blockaddress(@phi_trans8, %[[LATCH:.*]]), [label %latch]
+; CHECK-NEXT: indirectbr ptr blockaddress(@phi_trans8, %[[LATCH:.*]]), [label %[[LATCH]]]
; CHECK: [[LATCH]]:
; CHECK-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
@@ -1024,89 +1022,47 @@ if.end:
}
define i32 @load_load_partial_alias_cross_block_phi_trans(ptr %P) nounwind {
-; LE-MEMDEP-LABEL: define i32 @load_load_partial_alias_cross_block_phi_trans(
-; LE-MEMDEP-SAME: ptr [[P:%.*]]) #[[ATTR3]] {
-; LE-MEMDEP-NEXT: [[ENTRY:.*:]]
-; LE-MEMDEP-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
-; LE-MEMDEP-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
-; LE-MEMDEP-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 16
-; LE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; LE-MEMDEP-NEXT: [[TMP2:%.*]] = lshr i32 [[X1]], 8
-; LE-MEMDEP-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
-; LE-MEMDEP-NEXT: br i1 [[CMP]], label %[[IF:.*]], label %[[ELSE:.*]]
-; LE-MEMDEP: [[IF]]:
-; LE-MEMDEP-NEXT: br label %[[JOIN:.*]]
-; LE-MEMDEP: [[ELSE]]:
-; LE-MEMDEP-NEXT: br label %[[JOIN]]
-; LE-MEMDEP: [[JOIN]]:
-; LE-MEMDEP-NEXT: [[TTMP5:%.*]] = phi i8 [ [[TMP3]], %[[IF]] ], [ [[TMP1]], %[[ELSE]] ]
-; LE-MEMDEP-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
-; LE-MEMDEP-NEXT: ret i32 [[CONV6]]
-; LE-MEMDEP: [[IF_END:.*:]]
-; LE-MEMDEP-NEXT: ret i32 52
-;
-; LE-MEMSSA-LABEL: define i32 @load_load_partial_alias_cross_block_phi_trans(
-; LE-MEMSSA-SAME: ptr [[P:%.*]]) #[[ATTR3]] {
-; LE-MEMSSA-NEXT: [[ENTRY:.*:]]
-; LE-MEMSSA-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
-; LE-MEMSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
-; LE-MEMSSA-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 8
-; LE-MEMSSA-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; LE-MEMSSA-NEXT: [[TMP2:%.*]] = lshr i32 [[X1]], 16
-; LE-MEMSSA-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
-; LE-MEMSSA-NEXT: br i1 [[CMP]], label %[[IF:.*]], label %[[ELSE:.*]]
-; LE-MEMSSA: [[IF]]:
-; LE-MEMSSA-NEXT: br label %[[JOIN:.*]]
-; LE-MEMSSA: [[ELSE]]:
-; LE-MEMSSA-NEXT: br label %[[JOIN]]
-; LE-MEMSSA: [[JOIN]]:
-; LE-MEMSSA-NEXT: [[TTMP5:%.*]] = phi i8 [ [[TMP1]], %[[IF]] ], [ [[TMP3]], %[[ELSE]] ]
-; LE-MEMSSA-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
-; LE-MEMSSA-NEXT: ret i32 [[CONV6]]
-; LE-MEMSSA: [[IF_END:.*:]]
-; LE-MEMSSA-NEXT: ret i32 52
-;
-; BE-MEMDEP-LABEL: define i32 @load_load_partial_alias_cross_block_phi_trans(
-; BE-MEMDEP-SAME: ptr [[P:%.*]]) #[[ATTR3]] {
-; BE-MEMDEP-NEXT: [[ENTRY:.*:]]
-; BE-MEMDEP-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
-; BE-MEMDEP-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
-; BE-MEMDEP-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 8
-; BE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; BE-MEMDEP-NEXT: [[TMP2:%.*]] = lshr i32 [[X1]], 16
-; BE-MEMDEP-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
-; BE-MEMDEP-NEXT: br i1 [[CMP]], label %[[IF:.*]], label %[[ELSE:.*]]
-; BE-MEMDEP: [[IF]]:
-; BE-MEMDEP-NEXT: br label %[[JOIN:.*]]
-; BE-MEMDEP: [[ELSE]]:
-; BE-MEMDEP-NEXT: br label %[[JOIN]]
-; BE-MEMDEP: [[JOIN]]:
-; BE-MEMDEP-NEXT: [[TTMP5:%.*]] = phi i8 [ [[TMP3]], %[[IF]] ], [ [[TMP1]], %[[ELSE]] ]
-; BE-MEMDEP-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
-; BE-MEMDEP-NEXT: ret i32 [[CONV6]]
-; BE-MEMDEP: [[IF_END:.*:]]
-; BE-MEMDEP-NEXT: ret i32 52
+; LE-LABEL: define i32 @load_load_partial_alias_cross_block_phi_trans(
+; LE-SAME: ptr [[P:%.*]]) #[[ATTR3]] {
+; LE-NEXT: [[ENTRY:.*:]]
+; LE-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
+; LE-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
+; LE-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 8
+; LE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
+; LE-NEXT: [[TMP2:%.*]] = lshr i32 [[X1]], 16
+; LE-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
+; LE-NEXT: br i1 [[CMP]], label %[[IF:.*]], label %[[ELSE:.*]]
+; LE: [[IF]]:
+; LE-NEXT: br label %[[JOIN:.*]]
+; LE: [[ELSE]]:
+; LE-NEXT: br label %[[JOIN]]
+; LE: [[JOIN]]:
+; LE-NEXT: [[TTMP5:%.*]] = phi i8 [ [[TMP1]], %[[IF]] ], [ [[TMP3]], %[[ELSE]] ]
+; LE-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
+; LE-NEXT: ret i32 [[CONV6]]
+; LE: [[IF_END:.*:]]
+; LE-NEXT: ret i32 52
;
-; BE-MEMSSA-LABEL: define i32 @load_load_partial_alias_cross_block_phi_trans(
-; BE-MEMSSA-SAME: ptr [[P:%.*]]) #[[ATTR3]] {
-; BE-MEMSSA-NEXT: [[ENTRY:.*:]]
-; BE-MEMSSA-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
-; BE-MEMSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
-; BE-MEMSSA-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 16
-; BE-MEMSSA-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; BE-MEMSSA-NEXT: [[TMP2:%.*]] = lshr i32 [[X1]], 8
-; BE-MEMSSA-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
-; BE-MEMSSA-NEXT: br i1 [[CMP]], label %[[IF:.*]], label %[[ELSE:.*]]
-; BE-MEMSSA: [[IF]]:
-; BE-MEMSSA-NEXT: br label %[[JOIN:.*]]
-; BE-MEMSSA: [[ELSE]]:
-; BE-MEMSSA-NEXT: br label %[[JOIN]]
-; BE-MEMSSA: [[JOIN]]:
-; BE-MEMSSA-NEXT: [[TTMP5:%.*]] = phi i8 [ [[TMP1]], %[[IF]] ], [ [[TMP3]], %[[ELSE]] ]
-; BE-MEMSSA-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
-; BE-MEMSSA-NEXT: ret i32 [[CONV6]]
-; BE-MEMSSA: [[IF_END:.*:]]
-; BE-MEMSSA-NEXT: ret i32 52
+; BE-LABEL: define i32 @load_load_partial_alias_cross_block_phi_trans(
+; BE-SAME: ptr [[P:%.*]]) #[[ATTR3]] {
+; BE-NEXT: [[ENTRY:.*:]]
+; BE-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
+; BE-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
+; BE-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 16
+; BE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
+; BE-NEXT: [[TMP2:%.*]] = lshr i32 [[X1]], 8
+; BE-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
+; BE-NEXT: br i1 [[CMP]], label %[[IF:.*]], label %[[ELSE:.*]]
+; BE: [[IF]]:
+; BE-NEXT: br label %[[JOIN:.*]]
+; BE: [[ELSE]]:
+; BE-NEXT: br label %[[JOIN]]
+; BE: [[JOIN]]:
+; BE-NEXT: [[TTMP5:%.*]] = phi i8 [ [[TMP1]], %[[IF]] ], [ [[TMP3]], %[[ELSE]] ]
+; BE-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
+; BE-NEXT: ret i32 [[CONV6]]
+; BE: [[IF_END:.*:]]
+; BE-NEXT: ret i32 52
;
entry:
%x1 = load i32, ptr %P, align 4
diff --git a/llvm/test/Transforms/GVN/no-mem-dep-info.ll b/llvm/test/Transforms/GVN/no-mem-dep-info.ll
index 837f85d78e50f..ae9463e3e886e 100644
--- a/llvm/test/Transforms/GVN/no-mem-dep-info.ll
+++ b/llvm/test/Transforms/GVN/no-mem-dep-info.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt %s -passes=gvn -S -enable-gvn-memdep=false | FileCheck %s
-; RUN: opt %s -passes=gvn -S -enable-gvn-memdep=true | FileCheck %s
+; RUN: opt %s -passes=gvn -S -enable-gvn-memoryssa=false | FileCheck %s
+; RUN: opt %s -passes=gvn -S -enable-gvn-memoryssa=true | FileCheck %s
; Check that llvm.x86.avx2.gather.d.ps.256 intrinsic is not eliminated by GVN
; with and without memory dependence info.
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/loop-vectorize-metadata.ll b/llvm/test/Transforms/PhaseOrdering/X86/loop-vectorize-metadata.ll
index 15c4b10ec71b2..3d3432871ec8f 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/loop-vectorize-metadata.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/loop-vectorize-metadata.ll
@@ -1072,7 +1072,7 @@ define i32 @disabled(ptr noalias nocapture %a, ptr noalias nocapture readonly %b
; O3DEFAULT-NEXT: [[TMP24:%.*]] = load <4 x i32>, ptr [[ARRAYIDX_44]], align 4
; O3DEFAULT-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[TMP24]], [[TMP2]]
; O3DEFAULT-NEXT: store <4 x i32> [[TMP25]], ptr [[ARRAYIDX2_44]], align 4
-; O3DEFAULT-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 4
+; O3DEFAULT-NEXT: [[TMP26:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0
; O3DEFAULT-NEXT: ret i32 [[TMP26]]
;
; Os-LABEL: @disabled(
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