[llvm] [SystemZ] Expand and automate .insn directive coverage (PR #221914)
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Tue Sep 8 01:14:56 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-systemz
Author: Dominik Steenken (dominik-steenken)
<details>
<summary>Changes</summary>
This PR expands the set of supported instruction formats for the `.insn` directive to all published instruction formats. This includes all of the sub-formats (e.g., `RI-a`, `RI-b`, etc.). Sub-formats are indicated by an underscore `_`, followed by the subscript letter of the sub-format in the assembly (e.g. `ri_a` for `RI-a`). Newly supported formats are:
- `I`
- `IE`
- `MII`
- `RI-[abc]`
- `RIE-[abcdefg]`
- `RIL-[abc]`
- `RRD`
- `RRF-[abcde]`
- `RS-[ab]`
- `RSL-[ab]`
- `RSY-[ab]`
- `RX-[ab]`
- `RXY-[abc]`
- `SMI`
- `SS-[abcdef]`
- `VRI-[abcdefghijkl]`
- `VRR-[abcdefghijk]`
- `VRS-[abcd]`
Further, the way the `.insn` directives are implemented is changed in order to reduce maintenance overhead in keeping them up to date. Specifically:
- a new TableGen backend autogenerates the match table in `SystemZAsmParser.cpp`
- The `DirectiveInsn*` intermediate TableGen class layer was removed in favor of having the relevant definitions in a marker class, as well as the individual `Insn*` records themselves.
Note that some of the newly supported formats have immediate operands which are interpreted inconsistently by the instructions using the format, i.e. some instructions use them as signed immediates, while some use them as unsigned immediates.
This PR adds assembler operand types (`X(8|16|32)Imm`) to support a range check on these immediates that uses the union of the signed and unsigned ranges. So, an 8-bit immediate in a format that is used in both signed and unsigned forms will accept the range `[-128..255]`.
This PR also reorganizes the tests for the `.insn` directives to group them by machine, to mirror the regular assembly tests, and expands them to include all supported instruction formats.
Finally, the PR introduces a rule for picking the operand order for the `.insn` directives: since the individual supported instructions themselves have varying operand orders, the operands to the `.insn` directives are ordered by their index, e.g. `R1` > `I2` > `R3` > `BDL4`. So far, this has not been applied to the formats that are already supported, so as not to potentially break existing uses of the `.insn` format directives.
This PR was assisted by IBM Bob (for the `SystemZInsnDirectiveEmitter`, and some enhanced test coverage). I manually reviewed the autogenerated code to the best of my ability.
---
Patch is 84.08 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/221914.diff
18 Files Affected:
- (modified) llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp (+15-66)
- (modified) llvm/lib/Target/SystemZ/CMakeLists.txt (+1)
- (modified) llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp (+27)
- (modified) llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h (+3)
- (modified) llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp (+12)
- (modified) llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h (+7)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrFormats.td (+7-232)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrInfo.td (+867-115)
- (modified) llvm/lib/Target/SystemZ/SystemZOperands.td (+15)
- (added) llvm/test/MC/SystemZ/directive-insn-bad.s (+113)
- (added) llvm/test/MC/SystemZ/directive-insn-z13.s (+64)
- (added) llvm/test/MC/SystemZ/directive-insn-z14.s (+33)
- (added) llvm/test/MC/SystemZ/directive-insn-z16.s (+14)
- (added) llvm/test/MC/SystemZ/directive-insn-z17.s (+23)
- (modified) llvm/test/MC/SystemZ/directive-insn.s (+141-2)
- (added) llvm/test/TableGen/SystemZInsnDirectiveEmitter.td (+56)
- (modified) llvm/utils/TableGen/CMakeLists.txt (+1)
- (added) llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp (+133)
``````````diff
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index 761cbaaedd22d..6bd3d0242bbc3 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -397,11 +397,14 @@ class SystemZOperand : public MCParsedAsmOperand {
bool isU4Imm() const { return isImm(0, 15); }
bool isU8Imm() const { return isImm(0, 255); }
bool isS8Imm() const { return isImm(-128, 127); }
+ bool isX8Imm() const { return isS8Imm() || isU8Imm(); }
bool isU12Imm() const { return isImm(0, 4095); }
bool isU16Imm() const { return isImm(0, 65535); }
bool isS16Imm() const { return isImm(-32768, 32767); }
+ bool isX16Imm() const { return isS16Imm() || isU16Imm(); }
bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
+ bool isX32Imm() const { return isS32Imm() || isU32Imm(); }
bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
};
@@ -657,76 +660,15 @@ struct CompareInsn {
return LHS < RHS.Format;
}
bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
- return LHS.Format < RHS.Format;
+ if (LHS.Format != RHS.Format)
+ return LHS.Format < RHS.Format;
+ return LHS.Opcode < RHS.Opcode;
}
};
// Table initializing information for parsing the .insn directive.
static struct InsnMatchEntry InsnMatchTable[] = {
- /* Format, Opcode, NumOperands, OperandKinds */
- { "e", SystemZ::InsnE, 1,
- { MCK_U16Imm } },
- { "ri", SystemZ::InsnRI, 3,
- { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
- { "rie", SystemZ::InsnRIE, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
- { "ril", SystemZ::InsnRIL, 3,
- { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
- { "rilu", SystemZ::InsnRILU, 3,
- { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
- { "ris", SystemZ::InsnRIS, 5,
- { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
- { "rr", SystemZ::InsnRR, 3,
- { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
- { "rre", SystemZ::InsnRRE, 3,
- { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
- { "rrf", SystemZ::InsnRRF, 5,
- { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
- { "rrs", SystemZ::InsnRRS, 5,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
- { "rs", SystemZ::InsnRS, 4,
- { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
- { "rse", SystemZ::InsnRSE, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
- { "rsi", SystemZ::InsnRSI, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
- { "rsy", SystemZ::InsnRSY, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
- { "rx", SystemZ::InsnRX, 3,
- { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
- { "rxe", SystemZ::InsnRXE, 3,
- { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
- { "rxf", SystemZ::InsnRXF, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
- { "rxy", SystemZ::InsnRXY, 3,
- { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
- { "s", SystemZ::InsnS, 2,
- { MCK_U32Imm, MCK_BDAddr64Disp12 } },
- { "si", SystemZ::InsnSI, 3,
- { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
- { "sil", SystemZ::InsnSIL, 3,
- { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
- { "siy", SystemZ::InsnSIY, 3,
- { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
- { "ss", SystemZ::InsnSS, 4,
- { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
- { "sse", SystemZ::InsnSSE, 3,
- { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
- { "ssf", SystemZ::InsnSSF, 4,
- { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
- { "vri", SystemZ::InsnVRI, 6,
- { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
- { "vrr", SystemZ::InsnVRR, 7,
- { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
- MCK_U4Imm } },
- { "vrs", SystemZ::InsnVRS, 5,
- { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
- { "vrv", SystemZ::InsnVRV, 4,
- { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
- { "vrx", SystemZ::InsnVRX, 4,
- { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
- { "vsi", SystemZ::InsnVSI, 4,
- { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
+#include "SystemZGenInsnMatchTable.inc"
};
void SystemZOperand::print(raw_ostream &OS, const MCAsmInfo &MAI) const {
@@ -1311,6 +1253,12 @@ bool SystemZAsmParser::parseDirectiveInsn(SMLoc L) {
ResTy = parsePCRel32(Operands);
else if (Kind == MCK_PCRel16)
ResTy = parsePCRel16(Operands);
+ else if (Kind == MCK_PCRel12)
+ ResTy = parsePCRel12(Operands);
+ else if (Kind == MCK_PCRel24)
+ ResTy = parsePCRel24(Operands);
+ else if (Kind == MCK_BDLAddr64Disp12Len4 || Kind == MCK_BDLAddr64Disp12Len8)
+ ResTy = parseBDLAddr64(Operands);
else {
// Only remaining operand kind is an immediate.
const MCExpr *Expr;
@@ -1319,7 +1267,6 @@ bool SystemZAsmParser::parseDirectiveInsn(SMLoc L) {
// Expect immediate expression.
if (Parser.parseExpression(Expr))
return Error(StartLoc, "unexpected token in directive");
-
SMLoc EndLoc =
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
@@ -1353,6 +1300,8 @@ bool SystemZAsmParser::parseDirectiveInsn(SMLoc L) {
ZOperand.addBDXAddrOperands(Inst, 3);
else if (ZOperand.isMem(BDVMem))
ZOperand.addBDVAddrOperands(Inst, 3);
+ else if (ZOperand.isMem(BDLMem))
+ ZOperand.addBDLAddrOperands(Inst, 3);
else if (ZOperand.isMem(LXAMem))
ZOperand.addLXAAddrOperands(Inst, 3);
else if (ZOperand.isImm())
diff --git a/llvm/lib/Target/SystemZ/CMakeLists.txt b/llvm/lib/Target/SystemZ/CMakeLists.txt
index 51021b30fd073..c990acff16d58 100644
--- a/llvm/lib/Target/SystemZ/CMakeLists.txt
+++ b/llvm/lib/Target/SystemZ/CMakeLists.txt
@@ -8,6 +8,7 @@ tablegen(LLVM SystemZGenHLASMAsmWriter.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM SystemZGenCallingConv.inc -gen-callingconv)
tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM SystemZGenDisassemblerTables.inc -gen-disassembler)
+tablegen(LLVM SystemZGenInsnMatchTable.inc -gen-insn-directive-match-table)
tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM SystemZGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM SystemZGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp
index a24543b699ab4..1e9936194c94a 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp
@@ -118,6 +118,15 @@ void SystemZInstPrinterCommon::printU8ImmOperand(const MCInst *MI, int OpNum,
printUImmOperand<8>(MI, OpNum, O);
}
+void SystemZInstPrinterCommon::printX8ImmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ if (Value >= 0)
+ printUImmOperand<8>(MI, OpNum, O);
+ else
+ printSImmOperand<8>(MI, OpNum, O);
+}
+
void SystemZInstPrinterCommon::printU12ImmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
printUImmOperand<12>(MI, OpNum, O);
@@ -133,6 +142,15 @@ void SystemZInstPrinterCommon::printU16ImmOperand(const MCInst *MI, int OpNum,
printUImmOperand<16>(MI, OpNum, O);
}
+void SystemZInstPrinterCommon::printX16ImmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ if (Value >= 0)
+ printUImmOperand<16>(MI, OpNum, O);
+ else
+ printSImmOperand<16>(MI, OpNum, O);
+}
+
void SystemZInstPrinterCommon::printS32ImmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
printSImmOperand<32>(MI, OpNum, O);
@@ -143,6 +161,15 @@ void SystemZInstPrinterCommon::printU32ImmOperand(const MCInst *MI, int OpNum,
printUImmOperand<32>(MI, OpNum, O);
}
+void SystemZInstPrinterCommon::printX32ImmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ if (Value >= 0)
+ printUImmOperand<32>(MI, OpNum, O);
+ else
+ printSImmOperand<32>(MI, OpNum, O);
+}
+
void SystemZInstPrinterCommon::printU48ImmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
printUImmOperand<48>(MI, OpNum, O);
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h
index 427dbba6ad1b4..3d6aa3c12eb52 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h
@@ -65,11 +65,14 @@ class SystemZInstPrinterCommon : public MCInstPrinter {
void printU4ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printX8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU12ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printS16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printX16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printS32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printX32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU48ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printPCRelOperand(const MCInst *MI, uint64_t Address, int OpNum,
raw_ostream &O);
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
index d692cbed129ca..0cfe4db5cae65 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
@@ -54,6 +54,12 @@ static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value,
return Value;
};
+ auto handleXImmValue = [&](unsigned W) -> uint64_t {
+ if (!checkFixupInRange(minIntN(W), maxUIntN(W)))
+ return 0;
+ return Value;
+ };
+
switch (unsigned(Kind)) {
case SystemZ::FK_390_PC12DBL:
return handlePCRelFixupValue(12);
@@ -91,12 +97,18 @@ static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value,
return handleImmValue(false, 4);
case SystemZ::FK_390_U8Imm:
return handleImmValue(false, 8);
+ case SystemZ::FK_390_X8Imm:
+ return handleXImmValue(8);
case SystemZ::FK_390_U12Imm:
return handleImmValue(false, 12);
case SystemZ::FK_390_U16Imm:
return handleImmValue(false, 16);
+ case SystemZ::FK_390_X16Imm:
+ return handleXImmValue(16);
case SystemZ::FK_390_U32Imm:
return handleImmValue(false, 32);
+ case SystemZ::FK_390_X32Imm:
+ return handleXImmValue(32);
case SystemZ::FK_390_U48Imm:
return handleImmValue(false, 48);
}
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h
index 1ff4217018f1f..aa8ca7e2312d0 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h
@@ -36,6 +36,10 @@ enum FixupKind {
FK_390_U32Imm,
FK_390_U48Imm,
+ FK_390_X8Imm,
+ FK_390_X16Imm,
+ FK_390_X32Imm,
+
// Marker
LastTargetFixupKind,
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
@@ -61,6 +65,9 @@ const static MCFixupKindInfo MCFixupKindInfos[SystemZ::NumTargetFixupKinds] = {
{"FK_390_U16Imm", 0, 16, 0},
{"FK_390_U32Imm", 0, 32, 0},
{"FK_390_U48Imm", 0, 48, 0},
+ {"FK_390_X8Imm", 0, 8, 0},
+ {"FK_390_X16Imm", 0, 16, 0},
+ {"FK_390_X32Imm", 0, 32, 0},
};
// clang-format on
} // end namespace SystemZ
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 82415f412509f..b13cc318671da 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -1758,241 +1758,16 @@ class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
}
//===----------------------------------------------------------------------===//
-// Instruction classes for .insn directives
+// Base class for all .insn directive instructions
//===----------------------------------------------------------------------===//
-
-class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstE<0, outs, ins, asmstr, pattern> {
- bits<16> enc;
-
- let Inst = enc;
-}
-
-class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIa<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
- let Inst{19-16} = enc{19-16};
-}
-
-class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIEd<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRILa<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
- string type;
-
- let Inst{47-40} = enc{47-40};
- let Inst{35-32} = enc{35-32};
-}
-
-class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIS<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRR<0, outs, ins, asmstr, pattern> {
- bits<16> enc;
-
- let Inst{15-8} = enc{15-8};
-}
-
-class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRRE<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
-}
-
-class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRRFa<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
-}
-
-class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRRS<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSa<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
-}
-
-class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSEa<6, outs, ins, asmstr, pattern> {
- bits <48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSI<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
-}
-
-class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSYa<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRXa<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
-}
-
-class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRXE<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let M3 = 0;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
+// This marker class is used to identify .insn directive instructions
+// for the SystemZInsnDirectiveEmitter. It must be the rightmost parent
+// in the inheritance list to ensure these properties take precedence.
+class InsnDirectiveBase {
+ bit isCodeGenOnly = 1;
+ bit hasSideEffects = 1;
}
-class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRXF<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRXYa<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstS<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
-}
-
-class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSI<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
-}
-
-class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSIY<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSIL<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-32} = enc{47-32};
-}
-
-class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSSd<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
-}
-
-class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSSE<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-32} = enc{47-32};
-}
-
-class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSSF<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{35-32} = enc{35-32};
-}
-
-class DirectiveInsnVRI<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRIe<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnVRR<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRRc<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnVRS<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRSc<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnVRV<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRV<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnVRX<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRX<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnVSI<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVSI<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-
//===----------------------------------------------------------------------===//
// Variants of instructions with condition mask
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index f53716a663ed8..8ca612260121d 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -2275,121 +2275,873 @@ let hasSideEffects = 1 in {
// .insn directive instructions
//===----------------------------------------------------------------------===//
-let isCodeGenOnly = 1, hasSideEffects = 1 in {
- def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>;
- def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1,
- imm32sx16:$I2),
- ".insn ri,$enc,$R1,$I2", []>;
- def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
- ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/221914
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