[llvm] [GlobalISel] Restrict value offset tracking to aggregates (NFC) (PR #221287)

[Cullen Rhodes via llvm-commits]

https://github.com/c-rhodes updated https://github.com/llvm/llvm-project/pull/221287

>From 2aeb9d236a2cacf8ab93722b8b629243384bae68 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Sun, 3 May 2026 13:45:33 +0000
Subject: [PATCH] [GlobalISel] Restrict value offset tracking to aggregates
 (NFC)

The single-vreg fast path added in d30d5fe8dd5d3 still populated an
offset list, although offsets are only necessary for aggregate values.

This wasn't the only place doing so. Avoid creating or updating offset
lists for non-aggregate values and add an assertion to enforce this
invariant.

Assisted-by: codex
---
 llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index ee4bcf773433d..5c6c8c1906345 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -137,6 +137,8 @@ class IRTranslatorImpl {
     }
 
     OffsetListT *getOffsets(const Value &V) {
+      assert(V.getType()->isAggregateType() &&
+             "Offsets are for aggregate values");
       auto It = TypeToOffsets.find(V.getType());
       if (It != TypeToOffsets.end())
         return It->second;
@@ -774,14 +776,11 @@ class IRTranslatorImpl {
 
     auto Reg = MRI->createGenericVirtualRegister(LLT::token());
     Regs.push_back(Reg);
-    auto &Offsets = *VMap.getOffsets(Token);
-    if (Offsets.empty())
-      Offsets.push_back(0);
     return Reg;
   }
 
-  /// Allocate some vregs and offsets in the VMap. Then populate just the
-  /// offsets while leaving the vregs empty.
+  /// Allocate empty vregs for \p Val. For aggregate values, also populate
+  /// their offsets.
   ValueToVRegInfo::VRegListT &allocateVRegs(const Value &Val);
 
   /// Get the frame index that represents \p Val.
@@ -950,6 +949,11 @@ IRTranslatorImpl::allocateVRegs(const Value &Val) {
   if (VRegsIt != VMap.vregs_end())
     return *VRegsIt->second;
   auto *Regs = VMap.getVRegs(Val);
+  if (!Val.getType()->isAggregateType()) {
+    Regs->push_back(0);
+    return *Regs;
+  }
+
   auto *Offsets = VMap.getOffsets(Val);
   SmallVector<LLT, 4> SplitTys;
   computeValueLLTs(*DL, *Val.getType(), SplitTys,
@@ -969,7 +973,6 @@ ArrayRef<Register> IRTranslatorImpl::getOrCreateVRegs(const Value &Val) {
 
   // Create entry for this type.
   auto *VRegs = VMap.getVRegs(Val);
-  auto *Offsets = VMap.getOffsets(Val);
 
   if (!Val.getType()->isTokenTy())
     assert(Val.getType()->isSized() &&
@@ -978,8 +981,6 @@ ArrayRef<Register> IRTranslatorImpl::getOrCreateVRegs(const Value &Val) {
   // Fast-path values that lower to a single vreg.
   if (!Val.getType()->isAggregateType()) {
     LLT Ty = getLLTForType(*Val.getType(), *DL);
-    if (Offsets->empty())
-      Offsets->push_back(0);
     VRegs->push_back(MRI->createGenericVirtualRegister(Ty));
     if (isa<Constant>(Val)) {
       bool Success = translate(cast<Constant>(Val), VRegs->front());
@@ -995,6 +996,7 @@ ArrayRef<Register> IRTranslatorImpl::getOrCreateVRegs(const Value &Val) {
   }
 
   SmallVector<LLT, 4> SplitTys;
+  auto *Offsets = VMap.getOffsets(Val);
   computeValueLLTs(*DL, *Val.getType(), SplitTys,
                    Offsets->empty() ? Offsets : nullptr);
 
@@ -2330,7 +2332,6 @@ bool IRTranslatorImpl::translateCopy(const User &U, Register Src,
   auto &Regs = *VMap.getVRegs(U);
   if (Regs.empty()) {
     Regs.push_back(Src);
-    VMap.getOffsets(U)->push_back(0);
   } else {
     // If we already assigned a vreg for this instruction, we can't change that.
     // Emit a copy to satisfy the users we already emitted.