[llvm] [Mips] Fix buildbot failure of MIPS I double store using SWC1 (PR #221912)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-mips

Author: yingopq

<details>
<summary>Changes</summary>

Expand ExtractElementF64_FPR to FMOV_S instead of MFC1 to avoid incorrect integer store.

Fix x86_64-expensive-checks compile error as for pr https://github.com/llvm/llvm-project/pull/209362.

Fix #<!-- -->62190.

---
Full diff: https://github.com/llvm/llvm-project/pull/221912.diff


2 Files Affected:

- (modified) llvm/lib/Target/Mips/MipsSEInstrInfo.cpp (+16-1) 
- (modified) llvm/test/CodeGen/Mips/mips1-not-support-ldc1-sdc1.ll (+4-4) 


``````````diff
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
index e31f5f5009200..f120376ccb6cb 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -532,7 +532,22 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
   case Mips::BuildPairF64_64:
     expandBuildPairF64(MBB, MI, isMicroMips, true);
     break;
-  case Mips::ExtractElementF64_FPR:
+  case Mips::ExtractElementF64_FPR: {
+    Register DstReg = MI.getOperand(0).getReg();
+    Register SrcReg = MI.getOperand(1).getReg();
+    int64_t Index = MI.getOperand(2).getImm();
+
+    unsigned SubRegIdx = (Index == 0) ? Mips::sub_lo : Mips::sub_hi;
+    Register SubReg = TRI->getSubReg(SrcReg, SubRegIdx);
+
+    if (SubReg && SubReg != DstReg) {
+      BuildMI(MBB, MI, MI.getDebugLoc(), get(Mips::FMOV_S), DstReg)
+          .addReg(SubReg, RegState::Kill);
+    }
+
+    MI.eraseFromParent();
+    return true;
+  }
   case Mips::ExtractElementF64:
     expandExtractElementF64(MBB, MI, isMicroMips, false);
     break;
diff --git a/llvm/test/CodeGen/Mips/mips1-not-support-ldc1-sdc1.ll b/llvm/test/CodeGen/Mips/mips1-not-support-ldc1-sdc1.ll
index aa0ea2347e091..18f19ce626877 100644
--- a/llvm/test/CodeGen/Mips/mips1-not-support-ldc1-sdc1.ll
+++ b/llvm/test/CodeGen/Mips/mips1-not-support-ldc1-sdc1.ll
@@ -27,19 +27,19 @@ entry:
 define void @test_swc1(double %a) #0 {
 ; MIPS1-LE-LABEL: test_swc1:
 ; MIPS1-LE:       # %bb.0: # %entry
-; MIPS1-LE-NEXT:    mfc1 $f0, $f13
+; MIPS1-LE-NEXT:    mov.s $f0, $f13
 ; MIPS1-LE-NEXT:    lui	$1, %hi(test)
 ; MIPS1-LE-NEXT:    swc1 $f0, %lo(test+4)($1)
-; MIPS1-LE-NEXT:    mfc1 $f0, $f12
+; MIPS1-LE-NEXT:    mov.s $f0, $f12
 ; MIPS1-LE-NEXT:    jr $ra
 ; MIPS1-LE-NEXT:    swc1 $f0, %lo(test)($1)
 
 ; MIPS1-BE-LABEL: test_swc1:
 ; MIPS1-BE:       # %bb.0: # %entry
-; MIPS1-BE-NEXT:    mfc1 $f0, $f12
+; MIPS1-BE-NEXT:    mov.s $f0, $f12
 ; MIPS1-BE-NEXT:    lui	$1, %hi(test)
 ; MIPS1-BE-NEXT:    swc1 $f0, %lo(test+4)($1)
-; MIPS1-BE-NEXT:    mfc1 $f0, $f13
+; MIPS1-BE-NEXT:    mov.s $f0, $f13
 ; MIPS1-BE-NEXT:    jr $ra
 ; MIPS1-BE-NEXT:    swc1 $f0, %lo(test)($1)
 entry:

``````````

</details>


https://github.com/llvm/llvm-project/pull/221912