[llvm] bea94ba - [AMDGPU][True16][CodeGen] Do not fold hi16 SGPR copy (#220858)

[via llvm-commits]

Author: Arseniy Obolenskiy
Date: 2026-09-07T22:20:13Z
New Revision: bea94ba6d6424468b60478c4ef1933e4c598f58f

URL: https://github.com/llvm/llvm-project/commit/bea94ba6d6424468b60478c4ef1933e4c598f58f
DIFF: https://github.com/llvm/llvm-project/commit/bea94ba6d6424468b60478c4ef1933e4c598f58f.diff

LOG: [AMDGPU][True16][CodeGen] Do not fold hi16 SGPR copy (#220858)

Dropping the subreg on a hi16 copy would read the low half instead

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    llvm/test/CodeGen/AMDGPU/true16-fold.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index d55067c963a89..e5490b390db08 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -2215,7 +2215,9 @@ bool SIFoldOperandsImpl::tryFoldFoldableCopy(
       OpToFold.getSubReg()) {
     if (DstRC == &AMDGPU::SReg_32RegClass &&
         DstRC == MRI->getRegClass(OpToFold.getReg())) {
-      assert(OpToFold.getSubReg() == AMDGPU::lo16);
+      if (!TRI->getMatchingSuperRegClass(DstRC, &AMDGPU::SGPR_LO16RegClass,
+                                         OpToFold.getSubReg()))
+        return false;
       OpToFold.setSubReg(0);
     }
   }

diff  --git a/llvm/test/CodeGen/AMDGPU/true16-fold.mir b/llvm/test/CodeGen/AMDGPU/true16-fold.mir
index 29be6c55e6f30..5dfabb938f1f9 100644
--- a/llvm/test/CodeGen/AMDGPU/true16-fold.mir
+++ b/llvm/test/CodeGen/AMDGPU/true16-fold.mir
@@ -265,3 +265,21 @@ body:             |
     $vgpr0 = COPY %5
     SI_RETURN implicit $vgpr0
 ...
+
+---
+name:            sgpr_hi16_copy_not_folded
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: sgpr_hi16_copy_not_folded
+    ; CHECK: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].hi16
+    ; CHECK-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF1]], killed [[COPY]], implicit-def dead $scc
+    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    %0:sreg_32 = IMPLICIT_DEF
+    %1:sreg_32 = IMPLICIT_DEF
+    %2:sreg_32 = COPY %0.hi16
+    %3:sreg_32 = S_PACK_LL_B32_B16 %1, killed %2, implicit-def dead $scc
+    S_ENDPGM 0, implicit %3
+...