[llvm] [RISCV] Fix infinite DAGCombine loop with SETCC and SIGN_EXTEND_INREG (PR #221593)

[via llvm-commits]

AZero13 wrote:

> We generalized (X & -(1 << C1) & 0xffffffff) == C2 << C1 using `sraiw`. The combine generates a `SIGN_EXTEND_INREG` when simplifying.
> 
> However, when C1 is 0 and the sign bit (bit 31) of X is already known to be zero, `DAGCombiner` sees that `SIGN_EXTEND_INREG` is semantically equivalent to `AND X, 0xFFFFFFFF` (zext). Because `DAGCombiner` considers `AND` to be more canonical than `SIGN_EXTEND_INREG` in this context, it immediately reverts the node back to `AND`.
> 
> This caused an infinite DAGCombine loop. This patch prevents folding back in this state.
> 
> Fixes: #221521

Can you merge and add this to 23.x release so we can do the cherry-pick bot thing

https://github.com/llvm/llvm-project/pull/221593